From: Sascha Hauer <s.hauer@pengutronix.de>
To: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: barebox@lists.infradead.org
Subject: Re: [PATCH v2] usb: dwc3: Toggle GCTL.CORESOFTRESET as a first step
Date: Mon, 18 Mar 2019 09:03:48 +0100 [thread overview]
Message-ID: <20190318080348.vt3nuauqjcipgxwl@pengutronix.de> (raw)
In-Reply-To: <20190313072519.25873-1-andrew.smirnov@gmail.com>
On Wed, Mar 13, 2019 at 12:25:19AM -0700, Andrey Smirnov wrote:
> Toggle GCTL.CORESOFTRESET before trying to access any of the block's
> registers. Without this additional step, first read of DWC3_GHWPARAMS*
> that follows results in assertion of GSTS.CSRTIMEOUT and IP block
> stuck in a non-functional state.
>
> Note that all above has only been observerd on i.MX8MQ (ZII Zest
> board) for USB1 controller. USB2 doesn't seem to be affected by this.
>
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> ---
Applied, thanks
Sascha
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prev parent reply other threads:[~2019-03-18 8:03 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-13 7:25 Andrey Smirnov
2019-03-18 8:03 ` Sascha Hauer [this message]
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