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From: Sam Ravnborg <sam@ravnborg.org>
To: Ahmad Fatoum <a.fatoum@pengutronix.de>
Cc: barebox@lists.infradead.org, lst@pengutronix.de,
	ore@pengutronix.de, rcz@pengutronix.de
Subject: Re: [PATCH 1/5] ARM: cache-armv7: add work-around for errata 814220
Date: Tue, 23 Apr 2019 19:39:44 +0200	[thread overview]
Message-ID: <20190423173944.GA8801@ravnborg.org> (raw)
In-Reply-To: <20190423171852.26126-2-a.fatoum@pengutronix.de>

Hi Ahmad.

On Tue, Apr 23, 2019 at 07:18:48PM +0200, Ahmad Fatoum wrote:
> The v7 ARM states that all cache and branch predictor maintenance operations
> that do not specify an address execute, relative to each other, in program
> order. However, because of this erratum, an L2 set/way cache maintenance
> operation can overtake an L1 set/way cache maintenance operation, this would
> cause the data corruption.
> 
> This ERRATA affected the Cortex-A7 and present in r0p2, r0p3, r0p4, r0p5.
> 
> This patch is the SW workaround by adding a DSB before changing cache levels as
> the ARM ERRATA: ARM/MP: 814220 told in the ARM ERRATA documentation.
> 
> Signed-off-by: Jason Liu <r64343@freescale.com>
> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
> Acked-by: Arnd Bergmann <arnd@arndb.de>
> [afa: picked from LKML: <20190214083145.15148-1-benjamin.gaignard@linaro.org>]
> [afa: edited commit message headline]
> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
>  arch/arm/Kconfig           | 12 ++++++++++++
>  arch/arm/cpu/cache-armv7.S |  3 +++
>  2 files changed, 15 insertions(+)
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index a683c9c86661..fc622640aa2b 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -448,4 +448,16 @@ config ARM_PSCI_DEBUG
>  	  putc function.
>  	  Only use for debugging.
>  
> +config ARM_ERRATA_814220
> +       bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
> +       depends on CPU_V7
> +       help
> +         The v7 ARM states that all cache and branch predictor maintenance
> +         operations that do not specify an address execute, relative to
> +         each other, in program order.
I have a hard time parsing the above. Seems like the last part of the
sentence is maybe missing?

> +         However, because of this erratum, an L2 set/way cache maintenance
> +         operation can overtake an L1 set/way cache maintenance operation.
> +         This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
> +         r0p4, r0p5.
It would be good to say that this should be enabled if so-and-so.

also consider the cost to have it always enabled. It is a single asm
instruction but I do not know the impact on a typical boot.

	Sam

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  reply	other threads:[~2019-04-23 17:39 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-23 17:18 [PATCH 0/5] ARM: mmu: misc armv7 cache/MMU fixes Ahmad Fatoum
2019-04-23 17:18 ` [PATCH 1/5] ARM: cache-armv7: add work-around for errata 814220 Ahmad Fatoum
2019-04-23 17:39   ` Sam Ravnborg [this message]
2019-04-25 10:38     ` Ahmad Fatoum
2019-04-25 10:02   ` Lucas Stach
2019-04-23 17:18 ` [PATCH 2/5] ARM: imx: work around i.MX6UL ERR008958 (ARM errata 814220) Ahmad Fatoum
2019-04-23 17:41   ` Sam Ravnborg
2019-04-25 10:39     ` Ahmad Fatoum
2019-04-23 17:18 ` [PATCH 3/5] ARM: cache-armv7: start invalidation from outer levels Ahmad Fatoum
2019-04-23 17:21   ` Ahmad Fatoum
2019-04-25  9:57     ` Lucas Stach
2019-04-23 17:18 ` [PATCH 4/5] ARM: mmu: remove doubly defined macro Ahmad Fatoum
2019-04-23 17:18 ` [PATCH 5/5] ARM: mmu: mark uncached regions as eXecute never on v7 Ahmad Fatoum

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