From: Sascha Hauer <s.hauer@pengutronix.de>
To: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Cc: barebox@lists.infradead.org, Ahmad Fatoum <a.fatoum@pengutronix.de>
Subject: Re: [PATCH v2] ARM: imx: disable IPU QoS setup for correct SoCs
Date: Mon, 6 May 2019 08:31:30 +0200 [thread overview]
Message-ID: <20190506063130.vjfaeuexrlqtmjn7@pengutronix.de> (raw)
In-Reply-To: <20190430031524.18810-1-r.czerwinski@pengutronix.de>
On Tue, Apr 30, 2019 at 05:15:24AM +0200, Rouven Czerwinski wrote:
> The condition was introduced in 4e6e8f73e9 ("ARM: imx6: don't
> execute IPU QoS setup on MX6 SX/SL"), but instead it bails at
> the Solo, not the SX and SL.
>
> The original intent was most probably to add an exception for
> the i.MX6 Solo as well, so everything else is skipped, including
> the SX, SL and now the UL and ULL. Fix the code to reflect this.
>
> On the SX, SL, UL, ULL, this now avoids writes to memory, which
> isn't described in the datasheets. On the S, it now configures
> the QoS settings.
>
> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
> ---
> arch/arm/mach-imx/imx6.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Applied, thanks
Sascha
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prev parent reply other threads:[~2019-05-06 6:31 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-30 3:15 Rouven Czerwinski
2019-05-06 6:31 ` Sascha Hauer [this message]
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