* [PATCH 01/14] bbu: In bbu_register_std_file_update detect device before accessing it
2019-05-10 6:21 [PATCH 00/14] More Layerscape patches Sascha Hauer
@ 2019-05-10 6:21 ` Sascha Hauer
2019-05-10 6:21 ` [PATCH 02/14] esdhc-xload: invalidate icache before jumping to image Sascha Hauer
` (12 subsequent siblings)
13 siblings, 0 replies; 15+ messages in thread
From: Sascha Hauer @ 2019-05-10 6:21 UTC (permalink / raw)
To: Barebox List
The device the standard file update handler writes to may not be present
before detecting it, so as a first step detect it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
common/bbu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/common/bbu.c b/common/bbu.c
index 3271d403b7..00bec32a86 100644
--- a/common/bbu.c
+++ b/common/bbu.c
@@ -299,6 +299,8 @@ static int bbu_std_file_handler(struct bbu_handler *handler,
return -EINVAL;
}
+ device_detect_by_name(devpath_to_name(data->devicefile));
+
ret = stat(data->devicefile, &s);
if (ret) {
oflags |= O_CREAT;
--
2.20.1
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^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH 02/14] esdhc-xload: invalidate icache before jumping to image
2019-05-10 6:21 [PATCH 00/14] More Layerscape patches Sascha Hauer
2019-05-10 6:21 ` [PATCH 01/14] bbu: In bbu_register_std_file_update detect device before accessing it Sascha Hauer
@ 2019-05-10 6:21 ` Sascha Hauer
2019-05-10 6:21 ` [PATCH 03/14] ARM: Layerscape: ls1046a: Add bootsource detection support Sascha Hauer
` (11 subsequent siblings)
13 siblings, 0 replies; 15+ messages in thread
From: Sascha Hauer @ 2019-05-10 6:21 UTC (permalink / raw)
To: Barebox List
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/mci/imx-esdhc-pbl.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/mci/imx-esdhc-pbl.c b/drivers/mci/imx-esdhc-pbl.c
index 2bfe5c2f37..0251757a2a 100644
--- a/drivers/mci/imx-esdhc-pbl.c
+++ b/drivers/mci/imx-esdhc-pbl.c
@@ -16,6 +16,7 @@
#include <mci.h>
#include <linux/sizes.h>
#include <asm-generic/sections.h>
+#include <asm/cache.h>
#include <mach/xload.h>
#ifdef CONFIG_ARCH_IMX
#include <mach/atf.h>
@@ -457,6 +458,8 @@ int ls1046a_esdhc_start_image(unsigned long r0, unsigned long r1, unsigned long
return ret;
}
+ icache_invalidate();
+
printf("Starting barebox\n");
barebox(r0, r1, r2);
--
2.20.1
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^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH 03/14] ARM: Layerscape: ls1046a: Add bootsource detection support
2019-05-10 6:21 [PATCH 00/14] More Layerscape patches Sascha Hauer
2019-05-10 6:21 ` [PATCH 01/14] bbu: In bbu_register_std_file_update detect device before accessing it Sascha Hauer
2019-05-10 6:21 ` [PATCH 02/14] esdhc-xload: invalidate icache before jumping to image Sascha Hauer
@ 2019-05-10 6:21 ` Sascha Hauer
2019-05-10 6:21 ` [PATCH 04/14] ARM: Layerscape: pblimage: Drop pbl end command Sascha Hauer
` (10 subsequent siblings)
13 siblings, 0 replies; 15+ messages in thread
From: Sascha Hauer @ 2019-05-10 6:21 UTC (permalink / raw)
To: Barebox List
Not much to do, there are only a few boot sources supported.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-layerscape/Makefile | 1 +
arch/arm/mach-layerscape/boot.c | 39 +++++++++++++++++++
.../mach-layerscape/include/mach/layerscape.h | 2 +
3 files changed, 42 insertions(+)
create mode 100644 arch/arm/mach-layerscape/boot.c
diff --git a/arch/arm/mach-layerscape/Makefile b/arch/arm/mach-layerscape/Makefile
index 269839254b..ad4e2f7af3 100644
--- a/arch/arm/mach-layerscape/Makefile
+++ b/arch/arm/mach-layerscape/Makefile
@@ -2,3 +2,4 @@ obj- := __dummy__.o
lwl-y += lowlevel.o errata.o
lwl-$(CONFIG_ARCH_LS1046) += lowlevel-ls1046a.o
obj-y += icid.o
+obj-pbl-y += boot.o
diff --git a/arch/arm/mach-layerscape/boot.c b/arch/arm/mach-layerscape/boot.c
new file mode 100644
index 0000000000..c804977d22
--- /dev/null
+++ b/arch/arm/mach-layerscape/boot.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <common.h>
+#include <init.h>
+#include <bootsource.h>
+#include <mach/layerscape.h>
+#include <soc/fsl/immap_lsch2.h>
+
+enum bootsource ls1046_bootsource_get(void)
+{
+ void __iomem *dcfg = IOMEM(LSCH2_DCFG_ADDR);
+ uint32_t rcw_src;
+
+ rcw_src = in_be32(dcfg) >> 23;
+
+ if (rcw_src == 0x40)
+ return BOOTSOURCE_MMC;
+ if ((rcw_src & 0x1fe) == 0x44)
+ return BOOTSOURCE_SPI_NOR;
+ if ((rcw_src & 0x1f0) == 0x10)
+ /* 8bit NOR Flash */
+ return BOOTSOURCE_NOR;
+ if ((rcw_src & 0x1f0) == 0x20)
+ /* 16bit NOR Flash */
+ return BOOTSOURCE_NOR;
+
+ return BOOTSOURCE_UNKNOWN;
+}
+
+static int ls1046a_bootsource_init(void)
+{
+ if (!of_machine_is_compatible("fsl,ls1046a"))
+ return 0;
+
+ bootsource_set(ls1046_bootsource_get());
+
+ return 0;
+}
+coredevice_initcall(ls1046a_bootsource_init);
\ No newline at end of file
diff --git a/arch/arm/mach-layerscape/include/mach/layerscape.h b/arch/arm/mach-layerscape/include/mach/layerscape.h
index 55e0b7bc96..3366e7f258 100644
--- a/arch/arm/mach-layerscape/include/mach/layerscape.h
+++ b/arch/arm/mach-layerscape/include/mach/layerscape.h
@@ -4,4 +4,6 @@
#define LS1046A_DDR_SDRAM_BASE 0x80000000
#define LS1046A_DDR_FREQ 2100000000
+enum bootsource ls1046_bootsource_get(void);
+
#endif /* __MACH_LAYERSCAPE_H */
--
2.20.1
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^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH 04/14] ARM: Layerscape: pblimage: Drop pbl end command
2019-05-10 6:21 [PATCH 00/14] More Layerscape patches Sascha Hauer
` (2 preceding siblings ...)
2019-05-10 6:21 ` [PATCH 03/14] ARM: Layerscape: ls1046a: Add bootsource detection support Sascha Hauer
@ 2019-05-10 6:21 ` Sascha Hauer
2019-05-10 6:21 ` [PATCH 05/14] ARM: Layerscape: Add QSPI boot support Sascha Hauer
` (9 subsequent siblings)
13 siblings, 0 replies; 15+ messages in thread
From: Sascha Hauer @ 2019-05-10 6:21 UTC (permalink / raw)
To: Barebox List
The PBL image tool includes two commands into the image. These are executed
after the initial image has been uploaded but before the final CRC
check. These commands are "flush" and "wait". According to the reference
manual a "flush" command can be used to read back the the value just
written to CCSR register space in order to let the previous write
complete. This seems unnecessary as the last write was never to the CCSR
register space. The "wait" command also seems unnecessary as the time
parameter is 0. As all this end_cmd stuff goes back to the PowerPC times
and everything still seems to work on Arm let's just remove it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
scripts/pblimage.c | 19 -------------------
1 file changed, 19 deletions(-)
diff --git a/scripts/pblimage.c b/scripts/pblimage.c
index 6e83c523e5..56256260c8 100644
--- a/scripts/pblimage.c
+++ b/scripts/pblimage.c
@@ -53,7 +53,6 @@ static int in_fd;
static uint32_t pbl_cmd_initaddr;
static uint32_t pbi_crc_cmd1;
static uint32_t pbi_crc_cmd2;
-static uint32_t pbl_end_cmd[4];
enum arch {
ARCH_ARM,
@@ -210,16 +209,6 @@ static void pbl_parser(char *name)
static void add_end_cmd(void)
{
uint32_t crc32_pbl;
- int i;
- unsigned char *p = (unsigned char *)&pbl_end_cmd;
-
- for (i = 0; i < 4; i++)
- pbl_end_cmd[i] = htobe32(pbl_end_cmd[i]);
-
- for (i = 0; i < 16; i++) {
- *pmem_buf++ = *p++;
- pbl_size++;
- }
/* Add PBI CRC command. */
*pmem_buf++ = 0x08;
@@ -297,18 +286,10 @@ static int pblimage_check_params(void)
pbl_cmd_initaddr = loadaddr & PBL_ADDR_24BIT_MASK;
pbl_cmd_initaddr |= PBL_ACS_CONT_CMD;
pbl_cmd_initaddr += image_size;
- pbl_end_cmd[0] = 0x09610000;
- pbl_end_cmd[1] = 0x00000000;
- pbl_end_cmd[2] = 0x096100c0;
- pbl_end_cmd[3] = 0x00000000;
} else {
pbi_crc_cmd1 = 0x13;
pbi_crc_cmd2 = 0x80;
pbl_cmd_initaddr = 0x82000000;
- pbl_end_cmd[0] = 0x091380c0;
- pbl_end_cmd[1] = 0x00000000;
- pbl_end_cmd[2] = 0x091380c0;
- pbl_end_cmd[3] = 0x00000000;
}
next_pbl_cmd = pbl_cmd_initaddr;
--
2.20.1
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^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH 05/14] ARM: Layerscape: Add QSPI boot support
2019-05-10 6:21 [PATCH 00/14] More Layerscape patches Sascha Hauer
` (3 preceding siblings ...)
2019-05-10 6:21 ` [PATCH 04/14] ARM: Layerscape: pblimage: Drop pbl end command Sascha Hauer
@ 2019-05-10 6:21 ` Sascha Hauer
2019-05-10 6:21 ` [PATCH 06/14] ARM: Layerscape: ls1046a: Add automatic bootsource detection xload function Sascha Hauer
` (8 subsequent siblings)
13 siblings, 0 replies; 15+ messages in thread
From: Sascha Hauer @ 2019-05-10 6:21 UTC (permalink / raw)
To: Barebox List
Booting Layerscape from QSPI is a bit tricky and the approach we take is
different from the one U-Boot has taken, so it's worth writing and
reading the following explanation.
The QSPI controller can map the Flash contents into the memory space (On
LS1046a at 0x40000000). The PBL unit uses this to read the RCW from this
memory window. The Layerscape SoCs have a PowerPC history, so it seemed
appropriate for the designers to let the QSPI controller operate in
big endian mode by default. To let the SoC see the correct RCW we have
to write the RCW and PBI data with be64 endianess. Our PBL image tool
pokes the initial binary into the SoC internal SRAM using PBI data as
done with SD/MMC boot aswell. barebox then changes the QSPI controller
endianess to le64 to properly read the barebox binary (placed at an
flash offset of 128KiB, so found in memory at 0x40020000) into SDRAM and
jumps to it.
U-Boot has another approach. Here the initial binary is executed in
place directly at 0x40100000. This means the QSPI controller endianess
must be swapped inside the PBI data. This has the effect that the whole
RCW/PBI data must be 64bit endianess swapped *except* the very last word
of the PBI data which contains the CRC command and is read already with
changed endianess. As a conclusion when porting QSPI PBI files from U-Boot
to barebox skip commands changing the endianess in the QSPI controller
and make sure the image is executed in internal SRAM and not in the
Flash memory window.
Lines like this should be removed:
09550000 000f400c
This sets the binary execution address:
09570604 40100000
For barebox it should be changed to 0x10000000.
As a result the PBI files can probably be unified between SD and QSPI
boot.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-layerscape/Makefile | 1 +
arch/arm/mach-layerscape/include/mach/xload.h | 2 +
arch/arm/mach-layerscape/xload-qspi.c | 37 +++++++++++++++++++
images/Makefile.layerscape | 6 +++
scripts/pblimage.c | 17 ++++++++-
5 files changed, 62 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/mach-layerscape/xload-qspi.c
diff --git a/arch/arm/mach-layerscape/Makefile b/arch/arm/mach-layerscape/Makefile
index ad4e2f7af3..4705154fb1 100644
--- a/arch/arm/mach-layerscape/Makefile
+++ b/arch/arm/mach-layerscape/Makefile
@@ -3,3 +3,4 @@ lwl-y += lowlevel.o errata.o
lwl-$(CONFIG_ARCH_LS1046) += lowlevel-ls1046a.o
obj-y += icid.o
obj-pbl-y += boot.o
+pbl-y += xload-qspi.o
diff --git a/arch/arm/mach-layerscape/include/mach/xload.h b/arch/arm/mach-layerscape/include/mach/xload.h
index fedd36e020..94756ed13d 100644
--- a/arch/arm/mach-layerscape/include/mach/xload.h
+++ b/arch/arm/mach-layerscape/include/mach/xload.h
@@ -2,5 +2,7 @@
#define __MACH_XLOAD_H
int ls1046a_esdhc_start_image(unsigned long r0, unsigned long r1, unsigned long r2);
+int ls1046a_qspi_start_image(unsigned long r0, unsigned long r1,
+ unsigned long r2);
#endif /* __MACH_XLOAD_H */
diff --git a/arch/arm/mach-layerscape/xload-qspi.c b/arch/arm/mach-layerscape/xload-qspi.c
new file mode 100644
index 0000000000..c76780a0e8
--- /dev/null
+++ b/arch/arm/mach-layerscape/xload-qspi.c
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <common.h>
+#include <soc/fsl/immap_lsch2.h>
+#include <asm-generic/sections.h>
+#include <asm/cache.h>
+#include <mach/xload.h>
+#include <mach/layerscape.h>
+
+/*
+ * The offset of the 2nd stage image in the output file. This must match with the
+ * offset the pblimage tool puts barebox to.
+ */
+#define BAREBOX_START (128 * 1024)
+
+int ls1046a_qspi_start_image(unsigned long r0, unsigned long r1,
+ unsigned long r2)
+{
+ void *qspi_reg_base = IOMEM(LSCH2_QSPI0_BASE_ADDR);
+ void *membase = (void *)LS1046A_DDR_SDRAM_BASE;
+ void *qspi_mem_base = IOMEM(0x40000000);
+ void (*barebox)(unsigned long, unsigned long, unsigned long) = membase;
+
+ /* Switch controller into little endian mode */
+ out_be32(qspi_reg_base, 0x000f400c);
+
+ memcpy(membase, qspi_mem_base + BAREBOX_START, barebox_image_size);
+ icache_invalidate();
+
+ printf("Starting barebox\n");
+
+ barebox(r0, r1, r2);
+
+ printf("failed\n");
+
+ return -EIO;
+}
diff --git a/images/Makefile.layerscape b/images/Makefile.layerscape
index 59f672791b..38e6648729 100644
--- a/images/Makefile.layerscape
+++ b/images/Makefile.layerscape
@@ -14,6 +14,12 @@ quiet_cmd_lspbl_image = LSPBL-IMG $@
$(objtree)/scripts/pblimage -o $@ -r $(lspbl-rcw-tmp) \
-m $($(patsubst $(obj)/%.pblb,PBL_CODE_SIZE_%,$<)) -p $(lspbl-pbi-tmp) -i $<
+quiet_cmd_lspbl_spi_image = LSPBL-SPI-IMG $@
+ cmd_lspbl_spi_image = $(CPP) $(lspbl_cfg_cpp_flags) -o $(lspbl-rcw-tmp) $(word 2,$^) ; \
+ $(CPP) $(lspbl_cfg_cpp_flags) -o $(lspbl-pbi-tmp) $(word 3,$^) ; \
+ $(objtree)/scripts/pblimage -o $@ -r $(lspbl-rcw-tmp) -s \
+ -m $($(patsubst $(obj)/%.pblb,PBL_CODE_SIZE_%,$<)) -p $(lspbl-pbi-tmp) -i $<
+
pbl-$(CONFIG_MACH_LS1046ARDB) += start_ls1046ardb.pbl
$(obj)/barebox-ls1046ardb-2nd.image: $(obj)/start_ls1046ardb.pblb
$(call if_changed,shipped)
diff --git a/scripts/pblimage.c b/scripts/pblimage.c
index 56256260c8..73c0169ac1 100644
--- a/scripts/pblimage.c
+++ b/scripts/pblimage.c
@@ -13,6 +13,7 @@
#include <stdint.h>
#include <getopt.h>
#include <endian.h>
+#include <byteswap.h>
#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
#define PBL_ACS_CONT_CMD 0x81000000
@@ -49,6 +50,7 @@ static int pbl_end;
static int image_size;
static int out_fd;
static int in_fd;
+static int spiimage;
static uint32_t pbl_cmd_initaddr;
static uint32_t pbi_crc_cmd1;
@@ -229,6 +231,7 @@ static void add_end_cmd(void)
static void pbl_load_image(void)
{
int size;
+ uint64_t *buf64 = (void *)mem_buf;
/* parse the rcw.cfg file. */
pbl_parser(rcwfile);
@@ -245,6 +248,15 @@ static void pbl_load_image(void)
add_end_cmd();
+ if (spiimage) {
+ int i;
+
+ pbl_size = roundup(pbl_size, 8);
+
+ for (i = 0; i < pbl_size / 8; i++)
+ buf64[i] = bswap_64(buf64[i]);
+ }
+
size = pbl_size;
if (write(out_fd, (const void *)&mem_buf, size) != size) {
@@ -338,7 +350,7 @@ int main(int argc, char *argv[])
int opt, ret;
off_t pos;
- while ((opt = getopt(argc, argv, "i:r:p:o:m:")) != -1) {
+ while ((opt = getopt(argc, argv, "i:r:p:o:m:s")) != -1) {
switch (opt) {
case 'i':
infile = optarg;
@@ -355,6 +367,9 @@ int main(int argc, char *argv[])
case 'm':
pbl_end = atoi(optarg);
break;
+ case 's':
+ spiimage = 1;
+ break;
default:
exit(EXIT_FAILURE);
}
--
2.20.1
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^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH 06/14] ARM: Layerscape: ls1046a: Add automatic bootsource detection xload function
2019-05-10 6:21 [PATCH 00/14] More Layerscape patches Sascha Hauer
` (4 preceding siblings ...)
2019-05-10 6:21 ` [PATCH 05/14] ARM: Layerscape: Add QSPI boot support Sascha Hauer
@ 2019-05-10 6:21 ` Sascha Hauer
2019-05-10 6:21 ` [PATCH 07/14] ARM: Layerscape: ls1046a: Add bbu handlers Sascha Hauer
` (7 subsequent siblings)
13 siblings, 0 replies; 15+ messages in thread
From: Sascha Hauer @ 2019-05-10 6:21 UTC (permalink / raw)
To: Barebox List
Add a helper function which continues booting from the detected
boot source.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-layerscape/Makefile | 2 +-
arch/arm/mach-layerscape/include/mach/xload.h | 2 ++
arch/arm/mach-layerscape/xload.c | 24 +++++++++++++++++++
3 files changed, 27 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/mach-layerscape/xload.c
diff --git a/arch/arm/mach-layerscape/Makefile b/arch/arm/mach-layerscape/Makefile
index 4705154fb1..73cd61a7cf 100644
--- a/arch/arm/mach-layerscape/Makefile
+++ b/arch/arm/mach-layerscape/Makefile
@@ -3,4 +3,4 @@ lwl-y += lowlevel.o errata.o
lwl-$(CONFIG_ARCH_LS1046) += lowlevel-ls1046a.o
obj-y += icid.o
obj-pbl-y += boot.o
-pbl-y += xload-qspi.o
+pbl-y += xload-qspi.o xload.o
diff --git a/arch/arm/mach-layerscape/include/mach/xload.h b/arch/arm/mach-layerscape/include/mach/xload.h
index 94756ed13d..eb2d998865 100644
--- a/arch/arm/mach-layerscape/include/mach/xload.h
+++ b/arch/arm/mach-layerscape/include/mach/xload.h
@@ -4,5 +4,7 @@
int ls1046a_esdhc_start_image(unsigned long r0, unsigned long r1, unsigned long r2);
int ls1046a_qspi_start_image(unsigned long r0, unsigned long r1,
unsigned long r2);
+int ls1046a_xload_start_image(unsigned long r0, unsigned long r1,
+ unsigned long r2);
#endif /* __MACH_XLOAD_H */
diff --git a/arch/arm/mach-layerscape/xload.c b/arch/arm/mach-layerscape/xload.c
new file mode 100644
index 0000000000..54495d7f97
--- /dev/null
+++ b/arch/arm/mach-layerscape/xload.c
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <common.h>
+#include <bootsource.h>
+#include <mach/layerscape.h>
+#include <mach/xload.h>
+
+int ls1046a_xload_start_image(unsigned long r0, unsigned long r1,
+ unsigned long r2)
+{
+ enum bootsource src;
+
+ src = ls1046_bootsource_get();
+
+ switch (src) {
+ case BOOTSOURCE_SPI_NOR:
+ return ls1046a_qspi_start_image(r0, r1, r2);
+ case BOOTSOURCE_MMC:
+ return ls1046a_esdhc_start_image(r0, r1, r2);
+ default:
+ pr_err("Unknown bootsource\n");
+ return -EINVAL;
+ }
+}
--
2.20.1
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^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH 07/14] ARM: Layerscape: ls1046a: Add bbu handlers
2019-05-10 6:21 [PATCH 00/14] More Layerscape patches Sascha Hauer
` (5 preceding siblings ...)
2019-05-10 6:21 ` [PATCH 06/14] ARM: Layerscape: ls1046a: Add automatic bootsource detection xload function Sascha Hauer
@ 2019-05-10 6:21 ` Sascha Hauer
2019-05-10 6:21 ` [PATCH 08/14] ARM: Layerscape: TQMLS1046a: configure qspi divider Sascha Hauer
` (6 subsequent siblings)
13 siblings, 0 replies; 15+ messages in thread
From: Sascha Hauer @ 2019-05-10 6:21 UTC (permalink / raw)
To: Barebox List
The barebox images can simply be written to the partitions, so we can
use bbu_register_std_file_update() for updating to MMC and QSPI.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-layerscape/include/mach/bbu.h | 22 +++++++++++++++++++++
1 file changed, 22 insertions(+)
create mode 100644 arch/arm/mach-layerscape/include/mach/bbu.h
diff --git a/arch/arm/mach-layerscape/include/mach/bbu.h b/arch/arm/mach-layerscape/include/mach/bbu.h
new file mode 100644
index 0000000000..1ea0cbb11f
--- /dev/null
+++ b/arch/arm/mach-layerscape/include/mach/bbu.h
@@ -0,0 +1,22 @@
+#ifndef __MACH_LAYERSCAPE_BBU_H
+#define __MACH_LAYERSCAPE_BBU_H
+
+#include <bbu.h>
+
+static inline int ls1046a_bbu_mmc_register_handler(const char *name,
+ const char *devicefile,
+ unsigned long flags)
+{
+ return bbu_register_std_file_update(name, flags, devicefile,
+ filetype_layerscape_image);
+}
+
+static inline int ls1046a_bbu_qspi_register_handler(const char *name,
+ const char *devicefile,
+ unsigned long flags)
+{
+ return bbu_register_std_file_update(name, flags, devicefile,
+ filetype_layerscape_qspi_image);
+}
+
+#endif /* __MACH_LAYERSCAPE_BBU_H */
\ No newline at end of file
--
2.20.1
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^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH 08/14] ARM: Layerscape: TQMLS1046a: configure qspi divider
2019-05-10 6:21 [PATCH 00/14] More Layerscape patches Sascha Hauer
` (6 preceding siblings ...)
2019-05-10 6:21 ` [PATCH 07/14] ARM: Layerscape: ls1046a: Add bbu handlers Sascha Hauer
@ 2019-05-10 6:21 ` Sascha Hauer
2019-05-10 6:21 ` [PATCH 09/14] ARM: Layerscape: TQMLS1046a: Sync qspi RCW from TQ U-Boot Sascha Hauer
` (5 subsequent siblings)
13 siblings, 0 replies; 15+ messages in thread
From: Sascha Hauer @ 2019-05-10 6:21 UTC (permalink / raw)
To: Barebox List
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/tqmls1046a/board.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boards/tqmls1046a/board.c b/arch/arm/boards/tqmls1046a/board.c
index 4fc8e76d65..caf0f7ce38 100644
--- a/arch/arm/boards/tqmls1046a/board.c
+++ b/arch/arm/boards/tqmls1046a/board.c
@@ -32,6 +32,9 @@ static int tqmls1046a_postcore_init(void)
/* Configure iomux for i2c4 */
out_be32(&scfg->rcwpmuxcr0, 0x3300);
+ /* divide CGA1/CGA2 PLL by 24 to get QSPI interface clock */
+ out_be32(&scfg->qspi_cfg, 0x30100000);
+
return 0;
}
--
2.20.1
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^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH 09/14] ARM: Layerscape: TQMLS1046a: Sync qspi RCW from TQ U-Boot
2019-05-10 6:21 [PATCH 00/14] More Layerscape patches Sascha Hauer
` (7 preceding siblings ...)
2019-05-10 6:21 ` [PATCH 08/14] ARM: Layerscape: TQMLS1046a: configure qspi divider Sascha Hauer
@ 2019-05-10 6:21 ` Sascha Hauer
2019-05-10 6:21 ` [PATCH 10/14] ARM: Layerscape: TQMLS1046a: print life signs when debugging Sascha Hauer
` (4 subsequent siblings)
13 siblings, 0 replies; 15+ messages in thread
From: Sascha Hauer @ 2019-05-10 6:21 UTC (permalink / raw)
To: Barebox List
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
.../boards/tqmls1046a/tqmls1046a_rcw_qspi_3333_5559.cfg | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_qspi_3333_5559.cfg b/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_qspi_3333_5559.cfg
index 395c75c7d0..2df229c56c 100644
--- a/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_qspi_3333_5559.cfg
+++ b/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_qspi_3333_5559.cfg
@@ -8,7 +8,7 @@
# 32: 33 - CGA_PLL2_CFG : 0 [0x0 / 0b00]
# 34: 39 - CGA_PLL2_RAT : 14 [0xe / 0b001110]
# 96: 99 - C1_PLL_SEL : 0 [0x0 / 0b0000]
-# 128:143 - SRDS_PRTCL_S1 : 13107 [0x3333 / 0b0011001100110011]
+# 128:143 - SRDS_PRTCL_S1 : 4403 [0x1133 / 0b0001000100110011]
# 144:159 - SRDS_PRTCL_S2 : 21849 [0x5559 / 0b0101010101011001]
# 160:161 - SRDS_PLL_REF_CLK_SEL_S1 : 3 [0x3 / 0b11]
# 162:163 - SRDS_PLL_REF_CLK_SEL_S2 : 3 [0x3 / 0b11]
@@ -39,7 +39,7 @@
# 357:359 - IRQ_EXT : 0 [0x0 / 0b000]
# 360:362 - SPI_EXT : 0 [0x0 / 0b000]
# 363:365 - SDHC_EXT : 0 [0x0 / 0b000]
-# 366:368 - UART_BASE : 5 [0x5 / 0b101]
+# 366:368 - UART_BASE : 6 [0x6 / 0b110]
# 369:369 - ASLEEP : 0 [0x0 / 0b0]
# 370:370 - RTC : 0 [0x0 / 0b0]
# 371:371 - SDHC_BASE : 0 [0x0 / 0b0]
@@ -79,6 +79,6 @@
aa55aa55 01ee0100
# RCW
0c140010 0e000000 00000000 00000000
-33335559 f0005002 40025000 c1000000
-00000000 00000000 00000000 00028800
+11335559 f0005002 40025000 c1000000
+00000000 00000000 00000000 00030800
20004000 01103202 00000096 00000001
--
2.20.1
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^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH 10/14] ARM: Layerscape: TQMLS1046a: print life signs when debugging
2019-05-10 6:21 [PATCH 00/14] More Layerscape patches Sascha Hauer
` (8 preceding siblings ...)
2019-05-10 6:21 ` [PATCH 09/14] ARM: Layerscape: TQMLS1046a: Sync qspi RCW from TQ U-Boot Sascha Hauer
@ 2019-05-10 6:21 ` Sascha Hauer
2019-05-10 6:21 ` [PATCH 11/14] ARM: Layerscape: TQMLS1046a: unify pbi files Sascha Hauer
` (3 subsequent siblings)
13 siblings, 0 replies; 15+ messages in thread
From: Sascha Hauer @ 2019-05-10 6:21 UTC (permalink / raw)
To: Barebox List
Do the UART initialization after the SoC specific lowlevel setup and
print the usual '>' when early debuging is enabled. To let this go out
properly it seems we have to wait a small amount of time beforehand.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/tqmls1046a/lowlevel.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boards/tqmls1046a/lowlevel.c b/arch/arm/boards/tqmls1046a/lowlevel.c
index 88744a8f9b..9815925599 100644
--- a/arch/arm/boards/tqmls1046a/lowlevel.c
+++ b/arch/arm/boards/tqmls1046a/lowlevel.c
@@ -246,9 +246,13 @@ static noinline __noreturn void tqmls1046a_r_entry(void)
__dtb_fsl_tqmls1046a_mbls10xxa_start);
arm_cpu_lowlevel_init();
- debug_ll_init();
ls1046a_init_lowlevel();
+ debug_ll_init();
+
+ udelay(500);
+ putc_ll('>');
+
fsl_ddr_set_memctl_regs(&ddrc[0], 0);
ls1046a_errata_post_ddr();
--
2.20.1
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^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH 11/14] ARM: Layerscape: TQMLS1046a: unify pbi files
2019-05-10 6:21 [PATCH 00/14] More Layerscape patches Sascha Hauer
` (9 preceding siblings ...)
2019-05-10 6:21 ` [PATCH 10/14] ARM: Layerscape: TQMLS1046a: print life signs when debugging Sascha Hauer
@ 2019-05-10 6:21 ` Sascha Hauer
2019-05-10 6:21 ` [PATCH 12/14] ARM: Layerscape: TQMLS1046a: Support booting from QSPI Sascha Hauer
` (2 subsequent siblings)
13 siblings, 0 replies; 15+ messages in thread
From: Sascha Hauer @ 2019-05-10 6:21 UTC (permalink / raw)
To: Barebox List
This unifies the two different pbi files. With our approach for QSPI
booting differences in the pbi files are not necessary:
- We do not do execute in place for QSPI, so we do not need different
image execution addresses
- Setting up the QSPI clock doesn't hurt even for SD boot
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
...mls1046a_pbi_sd.cfg => tqmls1046a_pbi.cfg} | 2 ++
.../boards/tqmls1046a/tqmls1046a_pbi_qspi.cfg | 33 -------------------
images/Makefile.layerscape | 4 +--
3 files changed, 4 insertions(+), 35 deletions(-)
rename arch/arm/boards/tqmls1046a/{tqmls1046a_pbi_sd.cfg => tqmls1046a_pbi.cfg} (94%)
delete mode 100644 arch/arm/boards/tqmls1046a/tqmls1046a_pbi_qspi.cfg
diff --git a/arch/arm/boards/tqmls1046a/tqmls1046a_pbi_sd.cfg b/arch/arm/boards/tqmls1046a/tqmls1046a_pbi.cfg
similarity index 94%
rename from arch/arm/boards/tqmls1046a/tqmls1046a_pbi_sd.cfg
rename to arch/arm/boards/tqmls1046a/tqmls1046a_pbi.cfg
index 7ac1398123..0a04afa770 100644
--- a/arch/arm/boards/tqmls1046a/tqmls1046a_pbi_sd.cfg
+++ b/arch/arm/boards/tqmls1046a/tqmls1046a_pbi.cfg
@@ -1,3 +1,5 @@
+#Configure QSPI clock
+0957015c 40100000
#Configure Scratch register
09570600 00000000
09570604 10000000
diff --git a/arch/arm/boards/tqmls1046a/tqmls1046a_pbi_qspi.cfg b/arch/arm/boards/tqmls1046a/tqmls1046a_pbi_qspi.cfg
deleted file mode 100644
index 32865ca2d0..0000000000
--- a/arch/arm/boards/tqmls1046a/tqmls1046a_pbi_qspi.cfg
+++ /dev/null
@@ -1,33 +0,0 @@
-#Configure QSPI clock
-0957015c 40100000
-#Configure Scratch register
-09570600 00000000
-09570604 40010000
-#Disable CCI barrier tranaction
-09570178 0000e010
-09180000 00000008
-#USB PHY frequency sel
-09570418 0000009c
-0957041c 0000009c
-09570420 0000009c
-#Serdes SATA
-09eb1300 80104e20
-09eb08dc 00502880
-#PEX gen3 link (errata A-010477)
-09570158 00000300
-89400890 01048000
-89500890 01048000
-89600890 01048000
-#PEX gen3 equalization preset values (errata A-008851)
-894008bc 01000000
-89400154 47474747
-89400158 47474747
-894008bc 00000000
-895008bc 01000000
-89500154 47474747
-89500158 47474747
-895008bc 00000000
-896008bc 01000000
-89600154 47474747
-89600158 47474747
-896008bc 00000000
diff --git a/images/Makefile.layerscape b/images/Makefile.layerscape
index 38e6648729..0f892aeb62 100644
--- a/images/Makefile.layerscape
+++ b/images/Makefile.layerscape
@@ -48,12 +48,12 @@ $(obj)/barebox-tqmls1046a-2nd.image: $(obj)/start_tqmls1046a.pblb
$(obj)/barebox-tqmls1046a-sd.image: $(obj)/start_tqmls1046a.pblb \
$(board)/tqmls1046a/tqmls1046a_rcw_sd_3333_5559.cfg \
- $(board)/tqmls1046a/tqmls1046a_pbi_sd.cfg
+ $(board)/tqmls1046a/tqmls1046a_pbi.cfg
$(call if_changed,lspbl_image)
$(obj)/barebox-tqmls1046a-qspi.image: $(obj)/start_tqmls1046a.pblb \
$(board)/tqmls1046a/tqmls1046a_rcw_qspi_3333_5559.cfg \
- $(board)/tqmls1046a/tqmls1046a_pbi_qspi.cfg
+ $(board)/tqmls1046a/tqmls1046a_pbi.cfg
$(call if_changed,lspbl_image)
image-$(CONFIG_MACH_TQMLS1046A) += barebox-tqmls1046a-sd.image \
--
2.20.1
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^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH 12/14] ARM: Layerscape: TQMLS1046a: Support booting from QSPI
2019-05-10 6:21 [PATCH 00/14] More Layerscape patches Sascha Hauer
` (10 preceding siblings ...)
2019-05-10 6:21 ` [PATCH 11/14] ARM: Layerscape: TQMLS1046a: unify pbi files Sascha Hauer
@ 2019-05-10 6:21 ` Sascha Hauer
2019-05-10 6:21 ` [PATCH 13/14] ARM: Layerscape: TQMLS1046a: Add environment and update handlers Sascha Hauer
2019-05-10 6:21 ` [PATCH 14/14] ARM: Layerscape: Add device tree compatible to image metadata Sascha Hauer
13 siblings, 0 replies; 15+ messages in thread
From: Sascha Hauer @ 2019-05-10 6:21 UTC (permalink / raw)
To: Barebox List
We have to build correct images suitable for QSPI, thus have to call
lspbl_spi_image instead of lspbl_image. In lowlevel code call the
xload function which detects the bootsource rather than hardcoding
SD/MMC.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/tqmls1046a/lowlevel.c | 2 +-
images/Makefile.layerscape | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boards/tqmls1046a/lowlevel.c b/arch/arm/boards/tqmls1046a/lowlevel.c
index 9815925599..2d0223ce89 100644
--- a/arch/arm/boards/tqmls1046a/lowlevel.c
+++ b/arch/arm/boards/tqmls1046a/lowlevel.c
@@ -257,7 +257,7 @@ static noinline __noreturn void tqmls1046a_r_entry(void)
ls1046a_errata_post_ddr();
- ls1046a_esdhc_start_image(0, 0, 0);
+ ls1046a_xload_start_image(0, 0, 0);
pr_err("Booting failed\n");
diff --git a/images/Makefile.layerscape b/images/Makefile.layerscape
index 0f892aeb62..d20cc6a37e 100644
--- a/images/Makefile.layerscape
+++ b/images/Makefile.layerscape
@@ -37,7 +37,7 @@ $(obj)/barebox-ls1046ardb-emmc.image: $(obj)/start_ls1046ardb.pblb \
$(obj)/barebox-ls1046ardb-qspi.image: $(obj)/start_ls1046ardb.pblb \
$(board)/ls1046ardb/ls1046ardb_rcw_qspi.cfg \
$(board)/ls1046ardb/ls1046ardb_pbi.cfg
- $(call if_changed,lspbl_image)
+ $(call if_changed,lspbl_spi_image)
image-$(CONFIG_MACH_LS1046ARDB) += barebox-ls1046ardb-sd.image barebox-ls1046ardb-qspi.image \
barebox-ls1046ardb-emmc.image barebox-ls1046ardb-2nd.image
@@ -54,7 +54,7 @@ $(obj)/barebox-tqmls1046a-sd.image: $(obj)/start_tqmls1046a.pblb \
$(obj)/barebox-tqmls1046a-qspi.image: $(obj)/start_tqmls1046a.pblb \
$(board)/tqmls1046a/tqmls1046a_rcw_qspi_3333_5559.cfg \
$(board)/tqmls1046a/tqmls1046a_pbi.cfg
- $(call if_changed,lspbl_image)
+ $(call if_changed,lspbl_spi_image)
image-$(CONFIG_MACH_TQMLS1046A) += barebox-tqmls1046a-sd.image \
barebox-tqmls1046a-qspi.image barebox-tqmls1046a-2nd.image
--
2.20.1
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^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH 13/14] ARM: Layerscape: TQMLS1046a: Add environment and update handlers
2019-05-10 6:21 [PATCH 00/14] More Layerscape patches Sascha Hauer
` (11 preceding siblings ...)
2019-05-10 6:21 ` [PATCH 12/14] ARM: Layerscape: TQMLS1046a: Support booting from QSPI Sascha Hauer
@ 2019-05-10 6:21 ` Sascha Hauer
2019-05-10 6:21 ` [PATCH 14/14] ARM: Layerscape: Add device tree compatible to image metadata Sascha Hauer
13 siblings, 0 replies; 15+ messages in thread
From: Sascha Hauer @ 2019-05-10 6:21 UTC (permalink / raw)
To: Barebox List
The TQMLS1046a can boot from QSPI and SD/MMC. Add partitioning for these
devices and barebox environment / barebox update handlers on them.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/tqmls1046a/board.c | 24 ++++++++++
arch/arm/dts/fsl-tqmls1046a-mbls10xxa.dts | 56 +++++++++++++++++++++++
2 files changed, 80 insertions(+)
diff --git a/arch/arm/boards/tqmls1046a/board.c b/arch/arm/boards/tqmls1046a/board.c
index caf0f7ce38..8cc4d73de5 100644
--- a/arch/arm/boards/tqmls1046a/board.c
+++ b/arch/arm/boards/tqmls1046a/board.c
@@ -3,11 +3,15 @@
#include <common.h>
#include <init.h>
#include <envfs.h>
+#include <bbu.h>
+#include <bootsource.h>
#include <asm/memory.h>
#include <linux/sizes.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <soc/fsl/immap_lsch2.h>
+#include <mach/bbu.h>
+#include <mach/layerscape.h>
static int tqmls1046a_mem_init(void)
{
@@ -23,6 +27,8 @@ mem_initcall(tqmls1046a_mem_init);
static int tqmls1046a_postcore_init(void)
{
struct ccsr_scfg *scfg = IOMEM(LSCH2_SCFG_ADDR);
+ enum bootsource bootsource;
+ unsigned long sd_bbu_flags = 0, qspi_bbu_flags = 0;
if (!of_machine_is_compatible("tqc,tqmls1046a"))
return 0;
@@ -35,6 +41,24 @@ static int tqmls1046a_postcore_init(void)
/* divide CGA1/CGA2 PLL by 24 to get QSPI interface clock */
out_be32(&scfg->qspi_cfg, 0x30100000);
+ bootsource = ls1046_bootsource_get();
+
+ switch (bootsource) {
+ case BOOTSOURCE_MMC:
+ of_device_enable_path("/chosen/environment-sd");
+ sd_bbu_flags = BBU_HANDLER_FLAG_DEFAULT;
+ break;
+ case BOOTSOURCE_SPI_NOR:
+ of_device_enable_path("/chosen/environment-qspi");
+ qspi_bbu_flags = BBU_HANDLER_FLAG_DEFAULT;
+ break;
+ default:
+ break;
+ }
+
+ ls1046a_bbu_mmc_register_handler("sd", "/dev/mmc0.barebox", sd_bbu_flags);
+ ls1046a_bbu_qspi_register_handler("qspi", "/dev/qspiflash0.barebox", qspi_bbu_flags);
+
return 0;
}
diff --git a/arch/arm/dts/fsl-tqmls1046a-mbls10xxa.dts b/arch/arm/dts/fsl-tqmls1046a-mbls10xxa.dts
index d783d50baf..f0332e3999 100644
--- a/arch/arm/dts/fsl-tqmls1046a-mbls10xxa.dts
+++ b/arch/arm/dts/fsl-tqmls1046a-mbls10xxa.dts
@@ -20,6 +20,8 @@
serial0 = &duart0;
serial1 = &duart1;
mmc0 = &esdhc;
+ qspiflash0 = &qflash0;
+ qspiflash1 = &qflash1;
qsgmii_s1_p1 = &qsgmii1_phy1;
qsgmii_s1_p2 = &qsgmii1_phy2;
qsgmii_s2_p1 = &qsgmii2_phy1;
@@ -30,6 +32,18 @@
chosen {
stdout-path = "serial1:115200n8";
+
+ environment-sd {
+ compatible = "barebox,environment";
+ device-path = &environment_sd;
+ status = "disabled";
+ };
+
+ environment-qspi {
+ compatible = "barebox,environment";
+ device-path = &environment_qspi;
+ status = "disabled";
+ };
};
gpio-keys-polled {
@@ -63,6 +77,24 @@
};
+&esdhc {
+ partitions {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ compatible = "fixed-partitions";
+
+ partition@0 {
+ label = "barebox";
+ reg = <0x1000 0xdf000>;
+ };
+
+ environment_sd: partition@e0000 {
+ label = "barebox-environment";
+ reg = <0xe0000 0x20000>;
+ };
+ };
+};
&duart0 {
status = "okay";
@@ -259,3 +291,27 @@
status = "disabled";
};
};
+
+&qflash0 {
+ partitions {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ compatible = "fixed-partitions";
+
+ partition@0 {
+ label = "barebox";
+ reg = <0x0 0x200000>;
+ };
+
+ environment_qspi: partition@200000 {
+ label = "barebox-environment";
+ reg = <0x200000 0x80000>;
+ };
+
+ partition@280000 {
+ label = "data";
+ reg = <0x280000 0x0>;
+ };
+ };
+};
--
2.20.1
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^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH 14/14] ARM: Layerscape: Add device tree compatible to image metadata
2019-05-10 6:21 [PATCH 00/14] More Layerscape patches Sascha Hauer
` (12 preceding siblings ...)
2019-05-10 6:21 ` [PATCH 13/14] ARM: Layerscape: TQMLS1046a: Add environment and update handlers Sascha Hauer
@ 2019-05-10 6:21 ` Sascha Hauer
13 siblings, 0 replies; 15+ messages in thread
From: Sascha Hauer @ 2019-05-10 6:21 UTC (permalink / raw)
To: Barebox List
Enrich the image metadata with the device tree compatible string
the image supports.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/ls1046ardb/lowlevel.c | 3 +++
arch/arm/boards/tqmls1046a/lowlevel.c | 3 +++
2 files changed, 6 insertions(+)
diff --git a/arch/arm/boards/ls1046ardb/lowlevel.c b/arch/arm/boards/ls1046ardb/lowlevel.c
index 6de16063a7..0c95fbb035 100644
--- a/arch/arm/boards/ls1046ardb/lowlevel.c
+++ b/arch/arm/boards/ls1046ardb/lowlevel.c
@@ -3,6 +3,7 @@
#include <common.h>
#include <debug_ll.h>
#include <ddr_spd.h>
+#include <image-metadata.h>
#include <platform_data/mmc-esdhc-imx.h>
#include <i2c/i2c-early.h>
#include <soc/fsl/fsl_ddr_sdram.h>
@@ -201,6 +202,8 @@ static noinline __noreturn void ls1046ardb_r_entry(unsigned long memsize)
debug_ll_init();
ls1046a_init_lowlevel();
+ IMD_USED_OF(fsl_ls1046a_rdb);
+
i2c = ls1046_i2c_init(IOMEM(LSCH2_I2C1_BASE_ADDR));
ret = spd_read_eeprom(i2c, i2c_fsl_xfer, 0x51, &spd_eeprom);
if (ret) {
diff --git a/arch/arm/boards/tqmls1046a/lowlevel.c b/arch/arm/boards/tqmls1046a/lowlevel.c
index 2d0223ce89..dc0e179694 100644
--- a/arch/arm/boards/tqmls1046a/lowlevel.c
+++ b/arch/arm/boards/tqmls1046a/lowlevel.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
#include <common.h>
#include <debug_ll.h>
+#include <image-metadata.h>
#include <platform_data/mmc-esdhc-imx.h>
#include <soc/fsl/fsl_ddr_sdram.h>
#include <soc/fsl/immap_lsch2.h>
@@ -253,6 +254,8 @@ static noinline __noreturn void tqmls1046a_r_entry(void)
udelay(500);
putc_ll('>');
+ IMD_USED_OF(fsl_tqmls1046a_mbls10xxa);
+
fsl_ddr_set_memctl_regs(&ddrc[0], 0);
ls1046a_errata_post_ddr();
--
2.20.1
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