[PATCH 1/2] ARM: dts: imx6qdl: phycore: Set phy-reset-duration for fec

[PATCH 1/2] ARM: dts: imx6qdl: phycore: Set phy-reset-duration for fec

[Stefan Riedmueller]

The voltage of the ethernet phy needs to be stable before de-asserting
the reset pin. Thus set the phy-reset-duration to 10 ms.

Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
 arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
index 8fde27bd0c17..1d39368165db 100644
--- a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
+++ b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
@@ -110,6 +110,7 @@
 	phy-handle = <&ethphy>;
 	phy-mode = "rgmii";
 	phy-reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+	phy-reset-duration = <10>; /* in msecs */
 	status = "disabled";
 
 	mdio {
-- 
2.7.4


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[PATCH 2/2] ARM: dts: imx6ul: phycore: Reduce eth drive strength

[Stefan Riedmueller]

Reduce the drive strength for the MDC, MDIO and TX pins of fec1 to improve
signal quality and EMC. Also disable internal pull ups on the MDC and
MDIO pins.

Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
 arch/arm/dts/imx6ul-phytec-phycore-som.dtsi | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
index 0ec7eae1eff0..c7c657bcd409 100644
--- a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
+++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
@@ -159,16 +159,16 @@
 
 		pinctrl_enet1: enet1grp {
 			fsl,pins = <
-				MX6UL_PAD_GPIO1_IO07__ENET1_MDC		0x1b0b0
-				MX6UL_PAD_GPIO1_IO06__ENET1_MDIO	0x1b0b0
+				MX6UL_PAD_GPIO1_IO07__ENET1_MDC		0x10010
+				MX6UL_PAD_GPIO1_IO06__ENET1_MDIO	0x10010
 				MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
 				MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
 				MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
 				MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
-				MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
-				MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
-				MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
-				MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
+				MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b010
+				MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b010
+				MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b010
+				MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b010
 			>;
 		};
 
-- 
2.7.4


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Re: [PATCH 1/2] ARM: dts: imx6qdl: phycore: Set phy-reset-duration for fec

[Sascha Hauer]

On Tue, Jul 02, 2019 at 03:03:49PM +0200, Stefan Riedmueller wrote:
> The voltage of the ethernet phy needs to be stable before de-asserting
> the reset pin. Thus set the phy-reset-duration to 10 ms.
> 
> Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
> ---
>  arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi | 1 +
>  1 file changed, 1 insertion(+)

Applied, thanks

Sascha


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