[PATCH v1 00/12] ARM: stm32mp: add drivers for GPIO, pinctrl

[PATCH v1 00/12] ARM: stm32mp: add drivers for GPIO, pinctrl

[Ahmad Fatoum]

Feedback welcome.

I still have a patch that ports designware_qos from U-Boot to barebox
sitting on my branch. It works fine, but it needs refactoring, so it
can reuse existing functionality in the generic designware MAC driver
that's already in barebox. That will take a while, but if there's interest
in it, I can push the current state somwhere till then.

Cheers,
Ahmad Fatoum (12):
  ARM: dts: stm32mp157a-dk1.dts: include upstream dts before barebox'
  ARM: dts: stm32mp: factor out common DK nodes into dtsi
  gpiolib: add gpio_get_chip helper
  driver: add stubs for hardware spinlocks
  pinctrl: add driver for STM32 GPIO and pin multiplexer
  ARM: dts: stm32mp157a-dk1: enable heartbeat and error LEDs
  ARM: stm32mp: turn on GPIO related options
  ARM: stm32mp157c-dk2: add board-specific sysconf fixups
  ARM: psci: fix erroneous call of ->system_reset on system_off
  ARM: sm: move get_gicd_base_address to header for reuse
  ARM: stm32mp: implement PSCI support
  ARM: stm32mp157c-dk2: boot kernel in nonsecure mode

 arch/arm/Kconfig                              |   1 +
 arch/arm/boards/stm32mp157c-dk2/Makefile      |   1 +
 arch/arm/boards/stm32mp157c-dk2/board.c       | 106 +++++
 .../defaultenv-dk2/nv/bootm.secure_state      |   1 +
 arch/arm/configs/stm32mp_defconfig            |   8 +-
 arch/arm/cpu/psci.c                           |   6 +-
 arch/arm/cpu/sm.c                             |  29 +-
 arch/arm/dts/stm32mp157a-dk1.dts              |  58 +--
 arch/arm/dts/stm32mp157a-dk1.dtsi             |  36 ++
 arch/arm/dts/stm32mp157c-dk2.dts              |  10 +-
 arch/arm/dts/stm32mp157c.dtsi                 |  15 +
 arch/arm/include/asm/gic.h                    |  29 ++
 arch/arm/mach-stm32mp/Kconfig                 |   2 +
 arch/arm/mach-stm32mp/Makefile                |   2 +-
 arch/arm/mach-stm32mp/include/mach/stm32.h    |  16 +
 arch/arm/mach-stm32mp/psci.c                  | 166 +++++++
 drivers/gpio/gpiolib.c                        |   7 +
 drivers/pinctrl/Kconfig                       |   6 +
 drivers/pinctrl/Makefile                      |   1 +
 drivers/pinctrl/pinctrl-stm32.c               | 425 ++++++++++++++++++
 include/gpio.h                                |   1 +
 include/hwspinlock.h                          |  31 ++
 include/soc/stm32/gpio.h                      | 120 +++++
 23 files changed, 980 insertions(+), 97 deletions(-)
 create mode 100644 arch/arm/boards/stm32mp157c-dk2/defaultenv-dk2/nv/bootm.secure_state
 create mode 100644 arch/arm/dts/stm32mp157a-dk1.dtsi
 create mode 100644 arch/arm/mach-stm32mp/psci.c
 create mode 100644 drivers/pinctrl/pinctrl-stm32.c
 create mode 100644 include/hwspinlock.h
 create mode 100644 include/soc/stm32/gpio.h

-- 
2.20.1


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[PATCH v1 01/12] ARM: dts: stm32mp157a-dk1.dts: include upstream dts before barebox'

[Ahmad Fatoum]

To allow "stm32mp157c.dtsi" to extend nodes in <arm/stm32mp157c.dtsi>,
it should be included after it. Do this.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/arm/dts/stm32mp157a-dk1.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts
index 741284a44472..62c28d396f00 100644
--- a/arch/arm/dts/stm32mp157a-dk1.dts
+++ b/arch/arm/dts/stm32mp157a-dk1.dts
@@ -6,9 +6,9 @@
 
 /dts-v1/;
 
-#include "stm32mp157c.dtsi"
 #include <arm/stm32mp157c.dtsi>
 #include <arm/stm32mp157-pinctrl.dtsi>
+#include "stm32mp157c.dtsi"
 
 / {
 	model = "STMicroelectronics STM32MP157A-DK1 Discovery Board";
-- 
2.20.1


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[PATCH v1 02/12] ARM: dts: stm32mp: factor out common DK nodes into dtsi

[Ahmad Fatoum]

The DK2 appears to be just the DK1 with a display, thus factor out the
barebox-specifics into a new stm32mp157a-dk1.dtsi, which we can include
in both device trees after including the upstream device tree.

As the updated device tree introduced new nodes, the now duplicates
(&ethernet0, &uart4, /chosen and /aliases) are dropped from the barebox
device as part of this commit as well.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/arm/dts/stm32mp157a-dk1.dts  | 58 ++-----------------------------
 arch/arm/dts/stm32mp157a-dk1.dtsi | 23 ++++++++++++
 arch/arm/dts/stm32mp157c-dk2.dts  | 10 ++----
 3 files changed, 27 insertions(+), 64 deletions(-)
 create mode 100644 arch/arm/dts/stm32mp157a-dk1.dtsi

diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts
index 62c28d396f00..f2cafae66b9b 100644
--- a/arch/arm/dts/stm32mp157a-dk1.dts
+++ b/arch/arm/dts/stm32mp157a-dk1.dts
@@ -4,59 +4,5 @@
  * Author: Alexandre Torgue <alexandre.torgue@st.com>.
  */
 
-/dts-v1/;
-
-#include <arm/stm32mp157c.dtsi>
-#include <arm/stm32mp157-pinctrl.dtsi>
-#include "stm32mp157c.dtsi"
-
-/ {
-	model = "STMicroelectronics STM32MP157A-DK1 Discovery Board";
-	compatible = "st,stm32mp157a-dk1", "st,stm32mp157";
-
-	aliases {
-		ethernet0 = &ethernet0;
-		serial0 = &uart4;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	sram: sram@10050000 {
-		compatible = "mmio-sram";
-		reg = <0x10050000 0x10000>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0x10050000 0x10000>;
-
-		dma_pool: dma_pool@0 {
-			reg = <0x0 0x10000>;
-			pool;
-		};
-	};
-};
-
-&ethernet0 {
-	status = "okay";
-	pinctrl-0 = <&ethernet0_rgmii_pins_a>;
-	pinctrl-names = "default", "sleep";
-	phy-mode = "rgmii";
-	max-speed = <1000>;
-	phy-handle = <&phy0>;
-
-	mdio0 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "snps,dwmac-mdio";
-		phy0: ethernet-phy@0 {
-			reg = <0>;
-		};
-	};
-};
-
-&uart4 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart4_pins_a>;
-	status = "okay";
-};
+#include <arm/stm32mp157a-dk1.dts>
+#include "stm32mp157a-dk1.dtsi"
diff --git a/arch/arm/dts/stm32mp157a-dk1.dtsi b/arch/arm/dts/stm32mp157a-dk1.dtsi
new file mode 100644
index 000000000000..8cc70129b215
--- /dev/null
+++ b/arch/arm/dts/stm32mp157a-dk1.dtsi
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com>.
+ */
+
+#include "stm32mp157c.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	sram: sram@10050000 {
+		compatible = "mmio-sram";
+		reg = <0x10050000 0x10000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x10050000 0x10000>;
+
+		dma_pool: dma_pool@0 {
+			reg = <0x0 0x10000>;
+			pool;
+		};
+	};
+};
diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts
index 7565cabc3d92..6e73162ea4bd 100644
--- a/arch/arm/dts/stm32mp157c-dk2.dts
+++ b/arch/arm/dts/stm32mp157c-dk2.dts
@@ -4,11 +4,5 @@
  * Author: Alexandre Torgue <alexandre.torgue@st.com>.
  */
 
-/dts-v1/;
-
-#include "stm32mp157a-dk1.dts"
-
-/ {
-	model = "STMicroelectronics STM32MP157C-DK2 Discovery Board";
-	compatible = "st,stm32mp157c-dk2", "st,stm32mp157";
-};
+#include <arm/stm32mp157c-dk2.dts>
+#include "stm32mp157a-dk1.dtsi"
-- 
2.20.1


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[PATCH v1 03/12] gpiolib: add gpio_get_chip helper

[Ahmad Fatoum]

Pinctrl nodes adhering to the generic pinctrl bindings may contain
properties like input-low/input-high, which require pinctrl_ops.set_state
to have a handle on the relevant gpio chip.

Currently this would lead to code duplication: Both the pinctrl driver
and gpiolib will need to store a list of registered gpiochips.

Avoid this by providing a helper to query the registered gpio_chip
given a gpio's number.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 drivers/gpio/gpiolib.c | 7 +++++++
 include/gpio.h         | 1 +
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index 4c7aee4a0b19..f96009896a41 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -475,6 +475,13 @@ int gpio_get_num(struct device_d *dev, int gpio)
 	return -EPROBE_DEFER;
 }
 
+struct gpio_chip *gpio_get_chip(int gpio)
+{
+	struct gpio_info *gi = gpio_to_desc(gpio);
+
+	return gi ? gi->chip : NULL;
+}
+
 #ifdef CONFIG_CMD_GPIO
 static int do_gpiolib(int argc, char *argv[])
 {
diff --git a/include/gpio.h b/include/gpio.h
index 38d6ba2df913..e822fd53475d 100644
--- a/include/gpio.h
+++ b/include/gpio.h
@@ -153,5 +153,6 @@ int gpiochip_add(struct gpio_chip *chip);
 void gpiochip_remove(struct gpio_chip *chip);
 
 int gpio_get_num(struct device_d *dev, int gpio);
+struct gpio_chip *gpio_get_chip(int gpio);
 
 #endif /* __GPIO_H */
-- 
2.20.1


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[PATCH v1 04/12] driver: add stubs for hardware spinlocks

[Ahmad Fatoum]

Some STM32MP Linux drivers, which could be ported to barebox as part of
improved second stage barebox support, are using hardware spinlocks to
coordinate access between the three processors. While barebox only
uses one of the two Cortex-A cores, spin locks may still be necessary
because of firmware loaded unto the Cortex-M.

To ease porting these drivers, without having to import the hw spinlock
driver now, add stubs for the functions.

The stubs will we be reused when CONFIG_HWSPINLOCK is introduced,
but is disabled in config. The API is oriented after the implementation
in U-Boot.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 include/hwspinlock.h | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)
 create mode 100644 include/hwspinlock.h

diff --git a/include/hwspinlock.h b/include/hwspinlock.h
new file mode 100644
index 000000000000..ba21c6d29695
--- /dev/null
+++ b/include/hwspinlock.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ */
+
+#ifndef __HWSPINLOCK_H
+#define __HWSPINLOCK_H
+
+struct hwspinlock { /* TODO to be implemented */ };
+
+static inline int hwspinlock_get_by_index(struct device_d *dev,
+					  int index,
+					  struct hwspinlock *hws)
+{
+	return -ENOSYS;
+}
+
+static inline int hwspinlock_lock_timeout(struct hwspinlock *hws,
+					  int timeout_ms)
+{
+	return -ENOSYS;
+}
+
+static inline int hwspinlock_unlock(struct hwspinlock *hws)
+{
+	return -ENOSYS;
+}
+
+struct hwspinlock_ops { /* TODO to be implemented */ };
+
+#endif /* __HWSPINLOCK_H */
-- 
2.20.1


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[PATCH v1 05/12] pinctrl: add driver for STM32 GPIO and pin multiplexer

[Ahmad Fatoum]

This adds driver support for the 12 GPIO banks on the STM32MP157.
As they are accessible to both the Cortex-A cores as well as the Cortex-M
core, modifications to these are protected by a hardware spinlock
and clocks are enabled/disabled as required.

All register fiddling done by the driver is collected in <soc/stm32/gpio.h>,
so future PBL code may make use of it as well to chainload barebox proper.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/arm/Kconfig                |   1 +
 arch/arm/dts/stm32mp157c.dtsi   |  15 ++
 drivers/pinctrl/Kconfig         |   6 +
 drivers/pinctrl/Makefile        |   1 +
 drivers/pinctrl/pinctrl-stm32.c | 425 ++++++++++++++++++++++++++++++++
 include/soc/stm32/gpio.h        | 120 +++++++++
 6 files changed, 568 insertions(+)
 create mode 100644 drivers/pinctrl/pinctrl-stm32.c
 create mode 100644 include/soc/stm32/gpio.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1d4b6e09ce79..0f5190b417ff 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -216,6 +216,7 @@ config ARCH_STM32MP
 	select COMMON_CLK_OF_PROVIDER
 	select HAS_DEBUG_LL
 	select HAVE_CLK
+	select GPIOLIB
 
 config ARCH_VERSATILE
 	bool "ARM Versatile boards (ARM926EJ-S)"
diff --git a/arch/arm/dts/stm32mp157c.dtsi b/arch/arm/dts/stm32mp157c.dtsi
index fa0d00ff02fe..b97622c8d4cb 100644
--- a/arch/arm/dts/stm32mp157c.dtsi
+++ b/arch/arm/dts/stm32mp157c.dtsi
@@ -4,4 +4,19 @@
 		/* Needed to let barebox find the clock nodes */
 		compatible = "simple-bus";
 	};
+
+	aliases {
+		gpio0 = &gpioa;
+		gpio1 = &gpiob;
+		gpio2 = &gpioc;
+		gpio3 = &gpiod;
+		gpio4 = &gpioe;
+		gpio5 = &gpiof;
+		gpio6 = &gpiog;
+		gpio7 = &gpioh;
+		gpio8 = &gpioi;
+		gpio9 = &gpioj;
+		gpio10 = &gpiok;
+		gpio11 = &gpioz;
+	};
 };
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 46badeee0693..e2fb0af7562a 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -90,6 +90,12 @@ config PINCTRL_VF610
 	default y if ARCH_VF610
 	help
 	  Pinmux controller found on Vybrid VF610 family of SoCs
+
+config PINCTRL_STM32
+	bool
+	default y if ARCH_STM32MP
+	help
+	  Pinmux and GPIO controller found on STM32 family
 endif
 
 endmenu
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 35b2d4707c39..9cb5e994777a 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -11,5 +11,6 @@ obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o
 obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o
 obj-$(CONFIG_PINCTRL_TEGRA_XUSB) += pinctrl-tegra-xusb.o
 obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
+obj-$(CONFIG_PINCTRL_STM32) += pinctrl-stm32.o
 
 obj-$(CONFIG_ARCH_MVEBU) += mvebu/
diff --git a/drivers/pinctrl/pinctrl-stm32.c b/drivers/pinctrl/pinctrl-stm32.c
new file mode 100644
index 000000000000..8e392eac5099
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-stm32.c
@@ -0,0 +1,425 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2015 Maxime Coquelin
+ * Copyright (C) 2017 STMicroelectronics
+ * Copyright (C) 2019 Ahmad Fatoum, Pengutronix
+ */
+
+#include <common.h>
+#include <init.h>
+#include <io.h>
+#include <of.h>
+#include <of_address.h>
+#include <pinctrl.h>
+#include <gpio.h>
+#include <hwspinlock.h>
+#include <malloc.h>
+#include <linux/clk.h>
+#include <soc/stm32/gpio.h>
+
+#define STM32_PIN_NO(x) ((x) << 8)
+#define STM32_GET_PIN_NO(x) ((x) >> 8)
+#define STM32_GET_PIN_FUNC(x) ((x) & 0xff)
+
+struct stm32_gpio_bank {
+	void __iomem *base;
+	struct gpio_chip chip;
+	struct clk *clk;
+	const char *name;
+};
+
+struct stm32_pinctrl {
+	struct pinctrl_device pdev;
+	struct hwspinlock hws;
+	struct stm32_gpio_bank gpio_banks[];
+};
+
+static inline struct stm32_pinctrl *to_stm32_pinctrl(struct pinctrl_device *pdev)
+{
+	return container_of(pdev, struct stm32_pinctrl, pdev);
+}
+
+static inline struct stm32_gpio_bank *to_stm32_gpio_bank(struct gpio_chip *chip)
+{
+	return container_of(chip, struct stm32_gpio_bank, chip);
+}
+
+static inline int stm32_gpio_pin(int gpio, struct stm32_gpio_bank **bank)
+{
+	if (bank) {
+		struct gpio_chip *chip;
+
+		chip = gpio_get_chip(gpio);
+		if (!chip)
+			return PTR_ERR(chip);
+
+		*bank = to_stm32_gpio_bank(chip);
+	}
+
+	return gpio % STM32_GPIO_PINS_PER_BANK;
+}
+
+static inline u32 stm32_gpio_get_mode(u32 function)
+{
+	switch (function) {
+	case STM32_PIN_GPIO:
+		return 0;
+	case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
+		return 2;
+	case STM32_PIN_ANALOG:
+		return 3;
+	}
+
+	return 0;
+}
+
+static inline u32 stm32_gpio_get_alt(u32 function)
+{
+	switch (function) {
+	case STM32_PIN_GPIO:
+		return 0;
+	case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
+		return function - 1;
+	case STM32_PIN_ANALOG:
+		return 0;
+	}
+
+	return 0;
+}
+
+static int stm32_pinctrl_set_state(struct pinctrl_device *pdev, struct device_node *group)
+{
+	struct stm32_pinctrl *pinctrl = to_stm32_pinctrl(pdev);
+	struct device_node *pins;
+	int ret;
+
+	ret = hwspinlock_lock_timeout(&pinctrl->hws, 10);
+	if (ret == -ETIMEDOUT) {
+		dev_err(pdev->dev, "hw spinlock timeout\n");
+		return ret;
+	}
+
+	for_each_child_of_node(group, pins) {
+		int num_pins = 0, i;
+		u32 slew_rate;
+		bool adjust_slew_rate = false;
+		enum stm32_pin_bias bias = -1;
+		enum stm32_pin_out_type out_type = -1;
+		enum { PIN_INPUT, PIN_OUTPUT_LOW, PIN_OUTPUT_HIGH } dir = -1;
+
+		of_get_property(pins, "pinmux", &num_pins);
+		num_pins /= sizeof(__be32);
+		if (!num_pins) {
+			dev_err(pdev->dev, "Invalid pinmux property in %s\n",
+				pins->full_name);
+			return -EINVAL;
+		}
+
+		ret = of_property_read_u32(pins, "slew-rate", &slew_rate);
+		if (!ret)
+			adjust_slew_rate = true;
+
+		if (of_get_property(pins, "bias-disable", NULL))
+			bias = STM32_PIN_NO_BIAS;
+		else if (of_get_property(pins, "bias-pull-up", NULL))
+			bias = STM32_PIN_PULL_UP;
+		else if (of_get_property(pins, "bias-pull-down", NULL))
+			bias = STM32_PIN_PULL_DOWN;
+
+		if (of_get_property(pins, "drive-push-pull", NULL))
+			out_type = STM32_PIN_OUT_PUSHPULL;
+		else if (of_get_property(pins, "drive-open-drain", NULL))
+			out_type = STM32_PIN_OUT_OPENDRAIN;
+
+		if (of_get_property(pins, "input-enable", NULL))
+			dir = PIN_INPUT;
+		else if (of_get_property(pins, "output-low", NULL))
+			dir = PIN_OUTPUT_LOW;
+		else if (of_get_property(pins, "output-high", NULL))
+			dir = PIN_OUTPUT_HIGH;
+
+		for (i = 0; i < num_pins; i++) {
+			struct stm32_gpio_bank *bank = NULL;
+			u32 pinfunc, mode, alt;
+			unsigned offset, func;
+
+			ret = of_property_read_u32_index(pins, "pinmux",
+					i, &pinfunc);
+			if (ret)
+				return ret;
+
+			func = STM32_GET_PIN_FUNC(pinfunc);
+			offset = stm32_gpio_pin(STM32_GET_PIN_NO(pinfunc), &bank);
+			if (offset < 0)
+				return -ENODEV;
+
+			dev_dbg(pdev->dev, "configuring port %s pin %u with:\n\t"
+				"fn %u, mode %u, alt %u\n",
+				bank->name, offset, func, mode, alt);
+
+			mode = stm32_gpio_get_mode(func);
+			alt = stm32_gpio_get_alt(func);
+
+			clk_enable(bank->clk);
+
+			__stm32_pmx_set_mode(bank->base, offset, mode, alt);
+
+			if (adjust_slew_rate)
+				__stm32_pmx_set_speed(bank->base, offset, slew_rate);
+
+			if (bias != -1)
+				__stm32_pmx_set_bias(bank->base, offset, bias);
+
+			if (out_type != -1)
+				__stm32_pmx_set_output_type(bank->base, offset, out_type);
+
+			if (dir == PIN_INPUT)
+				__stm32_pmx_gpio_input(bank->base, offset);
+			else if (dir == PIN_OUTPUT_LOW)
+				__stm32_pmx_gpio_output(bank->base, offset, 0);
+			else if (dir == PIN_OUTPUT_HIGH)
+				__stm32_pmx_gpio_output(bank->base, offset, 1);
+
+			clk_disable(bank->clk);
+		}
+	}
+
+	hwspinlock_unlock(&pinctrl->hws);
+
+	return 0;
+}
+
+/* GPIO functions */
+
+static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
+{
+	struct stm32_gpio_bank *bank = to_stm32_gpio_bank(chip);
+	int ret;
+	u32 mode, alt;
+
+	clk_enable(bank->clk);
+
+	__stm32_pmx_get_mode(bank->base, stm32_gpio_pin(gpio, NULL), &mode, &alt);
+	if ((alt == 0) && (mode == 0))
+		ret = 1;
+	else if ((alt == 0) && (mode == 1))
+		ret = 0;
+	else
+		ret = -EINVAL;
+
+	clk_disable(bank->clk);
+
+	return ret;
+}
+
+static void stm32_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
+{
+	struct stm32_gpio_bank *bank = to_stm32_gpio_bank(chip);
+
+	clk_enable(bank->clk);
+
+	__stm32_pmx_gpio_set(bank->base, stm32_gpio_pin(gpio, NULL), value);
+
+	clk_disable(bank->clk);
+}
+
+static int stm32_gpio_get(struct gpio_chip *chip, unsigned gpio)
+{
+	struct stm32_gpio_bank *bank = to_stm32_gpio_bank(chip);
+	int ret;
+
+	clk_enable(bank->clk);
+
+	ret = __stm32_pmx_gpio_get(bank->base, stm32_gpio_pin(gpio, NULL));
+
+	clk_disable(bank->clk);
+
+	return ret;
+}
+
+static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
+{
+	struct stm32_gpio_bank *bank = to_stm32_gpio_bank(chip);
+
+	clk_enable(bank->clk);
+
+	__stm32_pmx_gpio_input(bank->base, stm32_gpio_pin(gpio, NULL));
+
+	clk_disable(bank->clk);
+
+	return 0;
+}
+
+static int stm32_gpio_direction_output(struct gpio_chip *chip,
+				       unsigned gpio, int value)
+{
+	struct stm32_gpio_bank *bank = to_stm32_gpio_bank(chip);
+
+	clk_enable(bank->clk);
+
+	__stm32_pmx_gpio_output(bank->base, stm32_gpio_pin(gpio, NULL), value);
+
+	clk_disable(bank->clk);
+
+	return 0;
+}
+
+static struct gpio_ops stm32_gpio_ops = {
+	.direction_input = stm32_gpio_direction_input,
+	.direction_output = stm32_gpio_direction_output,
+	.get_direction = stm32_gpio_get_direction,
+	.get = stm32_gpio_get,
+	.set = stm32_gpio_set,
+};
+
+static int stm32_gpiochip_add(struct stm32_gpio_bank *bank,
+			      struct device_node *np,
+			      struct device_d *parent)
+{
+	struct device_d *dev;
+	struct resource *iores;
+	enum { PINCTRL_PHANDLE, GPIOCTRL_OFFSET, PINCTRL_OFFSET, PINCOUNT, GPIO_RANGE_NCELLS };
+	const __be32 *gpio_ranges;
+	u32 ngpios;
+	int id, ret, size;
+
+	dev = of_platform_device_create(np, parent);
+	if (!dev)
+		return -ENODEV;
+
+	gpio_ranges = of_get_property(np, "gpio-ranges", &size);
+	size /= sizeof(__be32);
+	if (!gpio_ranges || size < GPIO_RANGE_NCELLS) {
+		dev_err(dev, "Couldn't read 'gpio-ranges' property in %s\n",
+			np->full_name);
+		return -EINVAL;
+	}
+
+	ret = of_property_read_u32(np, "ngpios", &ngpios);
+	if (ret)
+		ngpios = be32_to_cpu(gpio_ranges[PINCOUNT]);
+
+	bank->chip.ngpio = ngpios;
+
+	if (size > GPIO_RANGE_NCELLS) {
+		dev_err(dev, "Unsupported disjunct 'gpio-ranges' in %s\n",
+			np->full_name);
+		return -EINVAL;
+	}
+
+	if (ngpios > STM32_GPIO_PINS_PER_BANK) {
+		dev_err(dev, "ngpios property expected to be %u at most in %s\n",
+			ngpios, np->full_name);
+		return -EINVAL;
+	}
+
+	ret = of_property_read_string(np, "st,bank-name", &bank->name);
+	if (ret)
+		bank->name = np->name;
+
+	iores = dev_request_mem_resource(dev, 0);
+	if (IS_ERR(iores)) {
+		dev_err(dev, "Failed to request GPIO memory resource\n");
+		return PTR_ERR(iores);
+	}
+
+	bank->base = IOMEM(iores->start);
+
+	if (dev->id >= 0) {
+		id = dev->id;
+	} else {
+		id = of_alias_get_id(np, "gpio");
+		if (id < 0) {
+			dev_err(dev, "Failed to get GPIO alias\n");
+			return id;
+		}
+	}
+
+	bank->chip.base = id * STM32_GPIO_PINS_PER_BANK;
+	bank->chip.ops  = &stm32_gpio_ops;
+	bank->chip.dev  = dev;
+	bank->clk = clk_get(dev, NULL);
+	if (IS_ERR(bank->clk)) {
+		dev_err(dev, "failed to get clk (%ld)\n", PTR_ERR(bank->clk));
+		return PTR_ERR(bank->clk);
+	}
+
+	return gpiochip_add(&bank->chip);
+}
+
+static struct pinctrl_ops stm32_pinctrl_ops = {
+	.set_state = stm32_pinctrl_set_state,
+};
+
+static int stm32_pinctrl_probe(struct device_d *dev)
+{
+	struct stm32_pinctrl *pinctrl;
+	unsigned nbanks = 0;
+	struct stm32_gpio_bank *gpio_bank;
+	struct device_node *np = dev->device_node, *child;
+	int ret;
+
+	if (!of_find_property(np, "pins-are-numbered", NULL)) {
+		dev_err(dev, "only pins-are-numbered format supported\n");
+		return -EINVAL;
+	}
+
+	for_each_available_child_of_node(np, child)
+		if (of_property_read_bool(child, "gpio-controller"))
+			nbanks++;
+
+	pinctrl = xzalloc(sizeof(*pinctrl) + nbanks * sizeof(struct stm32_gpio_bank));
+
+	pinctrl->pdev.dev = dev;
+	pinctrl->pdev.ops = &stm32_pinctrl_ops;
+
+	/* hwspinlock property is optional, just log the error */
+	ret = hwspinlock_get_by_index(dev, 0, &pinctrl->hws);
+	if (ret)
+		dev_dbg(dev, "proceeding without hw spinlock support: (%d)\n",
+			ret);
+
+	ret = pinctrl_register(&pinctrl->pdev);
+	if (ret) {
+		dev_dbg(dev, "pinctrl_register failed: (%d)\n", ret);
+		return ret;
+	}
+
+	gpio_bank = pinctrl->gpio_banks;
+	for_each_available_child_of_node(np, child) {
+		if (!of_property_read_bool(child, "gpio-controller"))
+			continue;
+
+		ret = stm32_gpiochip_add(gpio_bank++, child, dev);
+		if (ret) {
+			dev_err(dev, "couldn't add gpiochip %s, ret = %d\n", child->name, ret);
+			return ret;
+		}
+	}
+
+	dev_info(dev, "pinctrl/gpio driver registered\n");
+
+	return 0;
+}
+
+static __maybe_unused struct of_device_id stm32_pinctrl_dt_ids[] = {
+	{ .compatible = "st,stm32f429-pinctrl" },
+	{ .compatible = "st,stm32f469-pinctrl" },
+	{ .compatible = "st,stm32f746-pinctrl" },
+	{ .compatible = "st,stm32h743-pinctrl" },
+	{ .compatible = "st,stm32mp157-pinctrl" },
+	{ .compatible = "st,stm32mp157-z-pinctrl" },
+	{ /* sentinel */ }
+};
+
+static struct driver_d stm32_pinctrl_driver = {
+	.name		= "stm32-pinctrl",
+	.probe		= stm32_pinctrl_probe,
+	.of_compatible	= DRV_OF_COMPAT(stm32_pinctrl_dt_ids),
+};
+
+static int stm32_pinctrl_init(void)
+{
+	return platform_driver_register(&stm32_pinctrl_driver);
+}
+core_initcall(stm32_pinctrl_init);
diff --git a/include/soc/stm32/gpio.h b/include/soc/stm32/gpio.h
new file mode 100644
index 000000000000..13b492a6937c
--- /dev/null
+++ b/include/soc/stm32/gpio.h
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2015 Maxime Coquelin
+ * Copyright (C) 2017 STMicroelectronics
+ * Copyright (C) 2019 Ahmad Fatoum, Pengutronix
+ */
+
+#ifndef __STM32_GPIO_H__
+#define __STM32_GPIO_H__
+
+#include <io.h>
+
+#define STM32_GPIO_MODER	0x00
+#define STM32_GPIO_TYPER	0x04
+#define STM32_GPIO_SPEEDR	0x08
+#define STM32_GPIO_PUPDR	0x0c
+#define STM32_GPIO_IDR		0x10
+#define STM32_GPIO_ODR		0x14
+#define STM32_GPIO_BSRR		0x18
+#define STM32_GPIO_LCKR		0x1c
+#define STM32_GPIO_AFRL		0x20
+#define STM32_GPIO_AFRH		0x24
+
+#define STM32_PIN_GPIO		0
+#define STM32_PIN_AF(x)		((x) + 1)
+#define STM32_PIN_ANALOG	(STM32_PIN_AF(15) + 1)
+
+#define STM32_GPIO_PINS_PER_BANK	16
+
+enum stm32_pin_bias { STM32_PIN_NO_BIAS, STM32_PIN_PULL_UP, STM32_PIN_PULL_DOWN };
+enum stm32_pin_out_type { STM32_PIN_OUT_PUSHPULL, STM32_PIN_OUT_OPENDRAIN };
+
+static inline void __stm32_pmx_set_speed(void __iomem  *base,
+					 unsigned offset, u32 speed)
+{
+	u32 val = readl(base + STM32_GPIO_SPEEDR);
+	val &= ~GENMASK(offset * 2 + 1, offset * 2);
+	val |= speed << (offset * 2);
+	writel(val, base + STM32_GPIO_SPEEDR);
+}
+
+static inline void __stm32_pmx_set_bias(void __iomem *base, unsigned offset,
+					enum stm32_pin_bias bias)
+{
+	u32 val = readl(base + STM32_GPIO_PUPDR);
+	val &= ~GENMASK(offset * 2 + 1, offset * 2);
+	val |= bias << (offset * 2);
+	writel(val, base + STM32_GPIO_PUPDR);
+}
+
+static inline void __stm32_pmx_set_mode(void __iomem *base,
+					int pin, u32 mode, u32 alt)
+{
+	u32 val;
+	int alt_shift = (pin % 8) * 4;
+	int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
+
+	val = readl(base + alt_offset);
+	val &= ~GENMASK(alt_shift + 3, alt_shift);
+	val |= (alt << alt_shift);
+	writel(val, base + alt_offset);
+
+	val = readl(base + STM32_GPIO_MODER);
+	val &= ~GENMASK(pin * 2 + 1, pin * 2);
+	val |= mode << (pin * 2);
+	writel(val, base + STM32_GPIO_MODER);
+}
+
+static inline void __stm32_pmx_get_mode(void __iomem *base, int pin,
+					u32 *mode, u32 *alt)
+{
+	u32 val;
+	int alt_shift = (pin % 8) * 4;
+	int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
+
+	val = readl(base + alt_offset);
+	val &= GENMASK(alt_shift + 3, alt_shift);
+	*alt = val >> alt_shift;
+
+	val = readl(base + STM32_GPIO_MODER);
+	val &= GENMASK(pin * 2 + 1, pin * 2);
+	*mode = val >> (pin * 2);
+}
+
+static inline int __stm32_pmx_gpio_get(void __iomem *base, unsigned offset)
+{
+	return !!(readl(base + STM32_GPIO_IDR) & BIT(offset));
+}
+
+static inline void __stm32_pmx_gpio_set(void __iomem *base, unsigned offset,
+					unsigned value)
+{
+	if (!value)
+		offset += STM32_GPIO_PINS_PER_BANK;
+
+	writel(BIT(offset), base + STM32_GPIO_BSRR);
+}
+
+static inline void __stm32_pmx_gpio_input(void __iomem *base, unsigned offset)
+{
+	__stm32_pmx_set_mode(base, offset, 0, 0);
+}
+
+static inline void __stm32_pmx_gpio_output(void __iomem *base, unsigned offset,
+					   unsigned value)
+{
+	__stm32_pmx_gpio_set(base, offset, value);
+	__stm32_pmx_set_mode(base, offset, 1, 0);
+}
+
+static inline void __stm32_pmx_set_output_type(void __iomem *base, unsigned offset,
+					       enum stm32_pin_out_type type)
+{
+	u32 val = readl(base + STM32_GPIO_TYPER);
+	val &= ~BIT(offset);
+	val |= type << offset;
+	writel(val, base + STM32_GPIO_TYPER);
+}
+
+#endif /* __STM32_GPIO_H__ */
-- 
2.20.1


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[PATCH v1 06/12] ARM: dts: stm32mp157a-dk1: enable heartbeat and error LEDs

[Ahmad Fatoum]

Now that we have GPIO support, add the red LED to the barebox
device tree and override the blue one's default state.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/arm/dts/stm32mp157a-dk1.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/dts/stm32mp157a-dk1.dtsi b/arch/arm/dts/stm32mp157a-dk1.dtsi
index 8cc70129b215..cd3d614d4623 100644
--- a/arch/arm/dts/stm32mp157a-dk1.dtsi
+++ b/arch/arm/dts/stm32mp157a-dk1.dtsi
@@ -8,6 +8,19 @@
 #include <dt-bindings/gpio/gpio.h>
 
 / {
+	led {
+		red {
+			label = "error";
+			gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+			status = "okay";
+		};
+
+		blue {
+			default-state = "on";
+		};
+	};
+
 	sram: sram@10050000 {
 		compatible = "mmio-sram";
 		reg = <0x10050000 0x10000>;
-- 
2.20.1


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[PATCH v1 07/12] ARM: stm32mp: turn on GPIO related options

[Ahmad Fatoum]

Now with pinctrl/GPIO support, enable some useful GPIO-related
drivers and commands.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/arm/configs/stm32mp_defconfig | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/arm/configs/stm32mp_defconfig b/arch/arm/configs/stm32mp_defconfig
index 3c248079ac7e..26859597710b 100644
--- a/arch/arm/configs/stm32mp_defconfig
+++ b/arch/arm/configs/stm32mp_defconfig
@@ -70,6 +70,8 @@ CONFIG_CMD_MM=y
 CONFIG_CMD_CLK=y
 CONFIG_CMD_DETECT=y
 CONFIG_CMD_FLASH=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_LED=y
 CONFIG_CMD_WD=y
 CONFIG_CMD_BAREBOX_UPDATE=y
 CONFIG_CMD_OF_NODE=y
@@ -86,10 +88,14 @@ CONFIG_DRIVER_NET_DESIGNWARE_GENERIC=y
 CONFIG_AT803X_PHY=y
 CONFIG_MICREL_PHY=y
 # CONFIG_SPI is not set
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_LED_GPIO_OF=y
 CONFIG_WATCHDOG=y
 CONFIG_WATCHDOG_POLLER=y
 CONFIG_STM32_IWDG_WATCHDOG=y
-# CONFIG_PINCTRL is not set
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED=y
 CONFIG_FS_EXT4=y
 CONFIG_FS_TFTP=y
 CONFIG_FS_NFS=y
-- 
2.20.1


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[PATCH v1 08/12] ARM: stm32mp157c-dk2: add board-specific sysconf fixups

[Ahmad Fatoum]

This imports the syscfg configuration done in the vendor U-Boot's
board_init into barebox. Only part missing is the CONFIG_DM_REGULATOR
protected clause that adjusts SYSCFG_IOCTRLSETR for operation above
~50MHz. These adjustments are only undertaken if VDD < 2.7V as they're
unsafe otherwise. As the barebox port doesn't yet support querying the
regulator, skip these adjustments for now.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/arm/boards/stm32mp157c-dk2/board.c | 94 +++++++++++++++++++++++++
 1 file changed, 94 insertions(+)

diff --git a/arch/arm/boards/stm32mp157c-dk2/board.c b/arch/arm/boards/stm32mp157c-dk2/board.c
index cbfe21db6a8c..5572231d525c 100644
--- a/arch/arm/boards/stm32mp157c-dk2/board.c
+++ b/arch/arm/boards/stm32mp157c-dk2/board.c
@@ -4,6 +4,55 @@
 #include <init.h>
 #include <asm/memory.h>
 #include <mach/stm32.h>
+#include <mfd/syscon.h>
+
+#define SYSCFG_BOOTR		0x00
+#define SYSCFG_PMCSETR		0x04
+#define SYSCFG_IOCTRLSETR	0x18
+#define SYSCFG_ICNR		0x1C
+#define SYSCFG_CMPCR		0x20
+#define SYSCFG_CMPENSETR	0x24
+#define SYSCFG_PMCCLRR		0x44
+
+#define SYSCFG_BOOTR_BOOT_MASK		GENMASK(2, 0)
+#define SYSCFG_BOOTR_BOOTPD_SHIFT	4
+
+#define SYSCFG_IOCTRLSETR_HSLVEN_TRACE		BIT(0)
+#define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI	BIT(1)
+#define SYSCFG_IOCTRLSETR_HSLVEN_ETH		BIT(2)
+#define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC		BIT(3)
+#define SYSCFG_IOCTRLSETR_HSLVEN_SPI		BIT(4)
+
+#define SYSCFG_CMPCR_SW_CTRL		BIT(1)
+#define SYSCFG_CMPCR_READY		BIT(8)
+
+#define SYSCFG_CMPENSETR_MPU_EN		BIT(0)
+
+#define SYSCFG_PMCSETR_ETH_CLK_SEL	BIT(16)
+#define SYSCFG_PMCSETR_ETH_REF_CLK_SEL	BIT(17)
+
+#define SYSCFG_PMCSETR_ETH_SELMII	BIT(20)
+
+#define SYSCFG_PMCSETR_ETH_SEL_MASK	GENMASK(23, 16)
+#define SYSCFG_PMCSETR_ETH_SEL_GMII_MII	(0 << 21)
+#define SYSCFG_PMCSETR_ETH_SEL_RGMII	(1 << 21)
+#define SYSCFG_PMCSETR_ETH_SEL_RMII	(4 << 21)
+
+#define pr_debug_syscfg(syscfg, reg) do {			\
+	int ret;						\
+	u32 val;						\
+								\
+	if (MSG_DEBUG > LOGLEVEL)				\
+		break;						\
+								\
+	ret = regmap_read(syscfg, reg, &val);			\
+								\
+	if (ret == 0)						\
+		pr_debug(#reg "= 0x%08x\n", val);		\
+	else							\
+		pr_debug(#reg "= ERROR (%d)\n", ret);		\
+} while (0)
+
 
 static int dk2_postcore_init(void)
 {
@@ -15,3 +64,48 @@ static int dk2_postcore_init(void)
 	return 0;
 }
 mem_initcall(dk2_postcore_init);
+
+static int dk2_sysconf_init(void)
+{
+	struct regmap *syscfg;
+	u32 reg;
+
+	if (!of_machine_is_compatible("st,stm32mp157c-dk2"))
+		return 0;
+
+	// TODO this function should be skipped if TF-A is used as first stage.
+	// Any way to determine this at runtime?
+
+	syscfg = syscon_regmap_lookup_by_compatible("st,stm32mp157-syscfg");
+
+	/* interconnect update : select master using the port 1 */
+	/* LTDC = AXI_M9 */
+	/* GPU  = AXI_M8 */
+	/* for now information is hardcoded */
+	regmap_write(syscfg, SYSCFG_ICNR, BIT(9));
+	pr_debug_syscfg(syscfg, SYSCFG_ICNR);
+
+	/* disable Pull-Down for boot pin connected to VDD */
+	regmap_read(syscfg, SYSCFG_BOOTR, &reg);
+	reg &= ~(SYSCFG_BOOTR_BOOT_MASK << SYSCFG_BOOTR_BOOTPD_SHIFT);
+	reg |= (reg & SYSCFG_BOOTR_BOOT_MASK) << SYSCFG_BOOTR_BOOTPD_SHIFT;
+	regmap_write(syscfg, SYSCFG_BOOTR, reg);
+	pr_debug_syscfg(syscfg, SYSCFG_BOOTR);
+
+	// TODO: Port High Speed Low Voltage Pad mode Enable from U-Boot
+
+	/* activate automatic I/O compensation
+	 * warning: need to ensure CSI enabled and ready in clock driver
+	 */
+	regmap_write(syscfg, SYSCFG_CMPENSETR, SYSCFG_CMPENSETR_MPU_EN);
+
+	do {
+		regmap_read(syscfg, SYSCFG_CMPCR, &reg);
+	} while (!(reg & SYSCFG_CMPCR_READY));
+
+	regmap_update_bits(syscfg, SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL, 0);
+	pr_debug_syscfg(syscfg, SYSCFG_CMPCR);
+
+	return 0;
+}
+coredevice_initcall(dk2_sysconf_init);
-- 
2.20.1


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[PATCH v1 09/12] ARM: psci: fix erroneous call of ->system_reset on system_off

[Ahmad Fatoum]

Both psci_system_reset and psci_system_off call psci_ops->system_reset,
which seems like a copy-paste error as there is an unused ->system_off
as well.

Adjust psci_system_off to use ->system_off instead. This won't matter
for the existing i.MX7 PSCI implementation because it defines neither
callback, but it will for the upcoming STM32MP PSCI support.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/arm/cpu/psci.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/psci.c b/arch/arm/cpu/psci.c
index 5c662cd0b992..a976ddbb5c65 100644
--- a/arch/arm/cpu/psci.c
+++ b/arch/arm/cpu/psci.c
@@ -138,8 +138,8 @@ static unsigned long psci_system_off(void)
 {
 	psci_printf("%s\n", __func__);
 
-	if (psci_ops->system_reset)
-		psci_ops->system_reset();
+	if (psci_ops->system_off)
+		psci_ops->system_off();
 
 	while(1);
 
@@ -293,4 +293,4 @@ BAREBOX_CMD_START(smc)
 	BAREBOX_CMD_DESC("secure monitor test command")
 	BAREBOX_CMD_GROUP(CMD_GRP_MISC)
 BAREBOX_CMD_END
-#endif
\ No newline at end of file
+#endif
-- 
2.20.1


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[PATCH v1 10/12] ARM: sm: move get_gicd_base_address to header for reuse

[Ahmad Fatoum]

Incoming PSCI implementation for the STM32MP1 needs
to get_gicd_base_address as well, so move it to gic.h to
avoid code duplication.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/arm/cpu/sm.c          | 29 +----------------------------
 arch/arm/include/asm/gic.h | 29 +++++++++++++++++++++++++++++
 2 files changed, 30 insertions(+), 28 deletions(-)

diff --git a/arch/arm/cpu/sm.c b/arch/arm/cpu/sm.c
index d9d62fbd9db0..b7a9eae89b1a 100644
--- a/arch/arm/cpu/sm.c
+++ b/arch/arm/cpu/sm.c
@@ -22,9 +22,6 @@
 
 #include "mmu.h"
 
-/* valid bits in CBAR register / PERIPHBASE value */
-#define CBAR_MASK			0xFFFF8000
-
 static unsigned int read_id_pfr1(void)
 {
 	unsigned int reg;
@@ -51,30 +48,6 @@ static void write_mvbar(u32 val)
 	asm("mcr p15, 0, %0, c12, c0, 1" : : "r"(val));
 }
 
-static unsigned long get_cbar(void)
-{
-	unsigned periphbase;
-
-	/* get the GIC base address from the CBAR register */
-	asm("mrc p15, 4, %0, c15, c0, 0\n" : "=r" (periphbase));
-
-	/* the PERIPHBASE can be mapped above 4 GB (lower 8 bits used to
-	 * encode this). Bail out here since we cannot access this without
-	 * enabling paging.
-	 */
-	if ((periphbase & 0xff) != 0) {
-		pr_err("PERIPHBASE is above 4 GB, no access.\n");
-		return -1;
-	}
-
-	return periphbase & CBAR_MASK;
-}
-
-static unsigned long get_gicd_base_address(void)
-{
-	return get_cbar() + GIC_DIST_OFFSET;
-}
-
 static int cpu_is_virt_capable(void)
 {
 	return read_id_pfr1() & (1 << 12);
@@ -267,4 +240,4 @@ static int sm_init(void)
 
 	return 0;
 }
-device_initcall(sm_init);
\ No newline at end of file
+device_initcall(sm_init);
diff --git a/arch/arm/include/asm/gic.h b/arch/arm/include/asm/gic.h
index bd3a80cdf70a..f83f52814107 100644
--- a/arch/arm/include/asm/gic.h
+++ b/arch/arm/include/asm/gic.h
@@ -107,4 +107,33 @@
 #define ICC_SGI1R_EL1		S3_0_C12_C11_5
 #define ICC_ASGI1R_EL1		S3_0_C12_C11_6
 
+#ifndef __ASSEMBLY__
+/* valid bits in CBAR register / PERIPHBASE value */
+#define CBAR_MASK			0xFFFF8000
+
+static inline unsigned long get_cbar(void)
+{
+	unsigned periphbase;
+
+	/* get the GIC base address from the CBAR register */
+	asm("mrc p15, 4, %0, c15, c0, 0\n" : "=r" (periphbase));
+
+	/* the PERIPHBASE can be mapped above 4 GB (lower 8 bits used to
+	 * encode this). Bail out here since we cannot access this without
+	 * enabling paging.
+	 */
+	if ((periphbase & 0xff) != 0) {
+		pr_err("PERIPHBASE is above 4 GB, no access.\n");
+		return -1;
+	}
+
+	return periphbase & CBAR_MASK;
+}
+
+static inline unsigned long get_gicd_base_address(void)
+{
+	return get_cbar() + GIC_DIST_OFFSET;
+}
+#endif
+
 #endif /* __GIC_H__ */
-- 
2.20.1


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[PATCH v1 11/12] ARM: stm32mp: implement PSCI support

[Ahmad Fatoum]

A mainline kernel will expect the firmware to have installed a secure
boot monitor for PSCI. Therefore have the firmware install a secure
boot monitor for PSCI.

The implemented functions are ported from the vendor U-Boot and not all
of them are currently exposed by barebox via secure calls.
In particular the implementation of .affinity_info and .migrate_info_type
are not yet used anywhere.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/arm/mach-stm32mp/Kconfig              |   1 +
 arch/arm/mach-stm32mp/Makefile             |   2 +-
 arch/arm/mach-stm32mp/include/mach/stm32.h |  16 ++
 arch/arm/mach-stm32mp/psci.c               | 166 +++++++++++++++++++++
 4 files changed, 184 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-stm32mp/psci.c

diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
index be16294f5ad7..94205aaf5508 100644
--- a/arch/arm/mach-stm32mp/Kconfig
+++ b/arch/arm/mach-stm32mp/Kconfig
@@ -1,6 +1,7 @@
 if ARCH_STM32MP
 
 config ARCH_STM32MP1157
+	select ARM_SECURE_MONITOR
 	bool
 
 config MACH_STM32MP157C_DK2
diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile
index 16a218658ade..132efe76c09c 100644
--- a/arch/arm/mach-stm32mp/Makefile
+++ b/arch/arm/mach-stm32mp/Makefile
@@ -1 +1 @@
-obj- := __dummy__.o
+obj-$(CONFIG_ARM_PSCI) += psci.o
diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h
index f9bdb788b98a..50f561c1e66f 100644
--- a/arch/arm/mach-stm32mp/include/mach/stm32.h
+++ b/arch/arm/mach-stm32mp/include/mach/stm32.h
@@ -32,4 +32,20 @@
 #define STM32_DDR_BASE			0xC0000000
 #define STM32_DDR_SIZE			SZ_1G
 
+/* TAMP registers */
+#define TAMP_BACKUP_REGISTER(x)         (STM32_TAMP_BASE + 0x100 + 4 * x)
+/* secure access */
+#define TAMP_BACKUP_MAGIC_NUMBER        TAMP_BACKUP_REGISTER(4)
+#define TAMP_BACKUP_BRANCH_ADDRESS      TAMP_BACKUP_REGISTER(5)
+/* non secure access */
+#define TAMP_BOOT_CONTEXT               TAMP_BACKUP_REGISTER(20)
+#define TAMP_BOOTCOUNT                  TAMP_BACKUP_REGISTER(21)
+
+#define TAMP_BOOT_MODE_MASK             GENMASK(15, 8)
+#define TAMP_BOOT_MODE_SHIFT            8
+#define TAMP_BOOT_DEVICE_MASK           GENMASK(7, 4)
+#define TAMP_BOOT_INSTANCE_MASK         GENMASK(3, 0)
+#define TAMP_BOOT_FORCED_MASK           GENMASK(7, 0)
+#define TAMP_BOOT_DEBUG_ON              BIT(16)
+
 #endif /* _MACH_STM32_H_ */
diff --git a/arch/arm/mach-stm32mp/psci.c b/arch/arm/mach-stm32mp/psci.c
new file mode 100644
index 000000000000..e5b447f85cc8
--- /dev/null
+++ b/arch/arm/mach-stm32mp/psci.c
@@ -0,0 +1,166 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2019 Ahmad Fatoum, Pengutronix <a.fatoum@pengutronix.de>
+ */
+
+#include <init.h>
+#include <common.h>
+#include <io.h>
+#include <linux/sizes.h>
+#include <asm/psci.h>
+#include <asm/gic.h>
+#include <asm/system.h>
+#include <mach/stm32.h>
+#include <asm/secure.h>
+
+#define BOOT_API_A7_CORE0_MAGIC_NUMBER	0xCA7FACE0
+#define BOOT_API_A7_CORE1_MAGIC_NUMBER	0xCA7FACE1
+
+#define MPIDR_AFF0			GENMASK(7, 0)
+
+#define RCC_MP_GRSTCSETR		(STM32_RCC_BASE + 0x0404)
+#define RCC_MP_GRSTCSETR_MPUP1RST	BIT(5)
+#define RCC_MP_GRSTCSETR_MPUP0RST	BIT(4)
+#define RCC_MP_GRSTCSETR_MPSYSRST	BIT(0)
+
+#define STM32MP1_PSCI_NR_CPUS		2
+#if STM32MP1_PSCI_NR_CPUS > ARM_SECURE_MAX_CPU
+#error "invalid value for ARM_SECURE_MAX_CPU"
+#endif
+
+static u8 psci_state[STM32MP1_PSCI_NR_CPUS] = {
+	 PSCI_AFFINITY_LEVEL_ON,
+	 PSCI_AFFINITY_LEVEL_OFF
+};
+
+static void psci_set_state(int cpu, u8 state)
+{
+	psci_state[cpu] = state;
+}
+
+static void stm32mp_smp_kick_all_cpus(void)
+{
+	u32 gic_dist_addr;
+
+	gic_dist_addr = get_gicd_base_address();
+
+	/* kick all CPUs (except this one) by writing to GICD_SGIR */
+	writel(1 << 24, gic_dist_addr + GICD_SGIR);
+}
+
+static int stm32mp_affinity_info(u32 target_affinity,
+				 u32 lowest_affinity_level)
+{
+	u32 cpu = target_affinity & MPIDR_AFF0;
+
+	if (lowest_affinity_level > 0)
+		return ARM_PSCI_RET_INVAL;
+
+	if (target_affinity & ~MPIDR_AFF0)
+		return ARM_PSCI_RET_INVAL;
+
+	if (cpu >= STM32MP1_PSCI_NR_CPUS)
+		return ARM_PSCI_RET_INVAL;
+
+	return psci_state[cpu];
+}
+
+static int stm32mp_migrate_info_type(void)
+{
+	/*
+	 * in Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
+	 * return 2 = Trusted OS is either not present or does not require
+	 * migration, system of this type does not require the caller
+	 * to use the MIGRATE function.
+	 * MIGRATE function calls return NOT_SUPPORTED.
+	 */
+	return 2;
+}
+
+static int stm32mp_cpu_on(u32 target_cpu)
+{
+	u32 cpu = target_cpu & MPIDR_AFF0;
+
+	if (target_cpu & ~MPIDR_AFF0)
+		return ARM_PSCI_RET_INVAL;
+
+	if (cpu >= STM32MP1_PSCI_NR_CPUS)
+		return ARM_PSCI_RET_INVAL;
+
+	if (psci_state[cpu] == PSCI_AFFINITY_LEVEL_ON)
+		return ARM_PSCI_RET_ALREADY_ON;
+
+	/* write entrypoint in backup RAM register */
+	writel(psci_cpu_entry, TAMP_BACKUP_BRANCH_ADDRESS);
+	psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON_PENDING);
+
+	/* write magic number in backup register */
+	if (cpu == 0x01)
+		writel(BOOT_API_A7_CORE1_MAGIC_NUMBER, TAMP_BACKUP_MAGIC_NUMBER);
+	else
+		writel(BOOT_API_A7_CORE0_MAGIC_NUMBER, TAMP_BACKUP_MAGIC_NUMBER);
+
+	stm32mp_smp_kick_all_cpus();
+
+	return ARM_PSCI_RET_SUCCESS;
+}
+
+static int stm32mp_cpu_off(void)
+{
+	u32 cpu;
+
+	cpu = psci_get_cpu_id();
+
+	psci_set_state(cpu, PSCI_AFFINITY_LEVEL_OFF);
+
+	dsb();
+	isb();
+
+	/* reset core: wfi is managed by BootRom */
+	if (cpu == 0x01)
+		writel(RCC_MP_GRSTCSETR_MPUP1RST, RCC_MP_GRSTCSETR);
+	else
+		writel(RCC_MP_GRSTCSETR_MPUP0RST, RCC_MP_GRSTCSETR);
+
+	/* just awaiting reset */
+	while (1)
+		asm("wfi");
+
+	return 0;
+}
+
+static void stm32mp_system_reset(void)
+{
+	/* System reset */
+	writel(RCC_MP_GRSTCSETR_MPSYSRST, RCC_MP_GRSTCSETR);
+	/* just awaiting reset */
+	while (1)
+		asm("wfi");
+}
+
+static void stm32mp_system_off(void)
+{
+	/* System Off is not managed, waiting user power off
+	 * TODO: handle I2C write in PMIC Main Control register bit 0 = SWOFF
+	 */
+	while (1)
+		asm("wfi");
+}
+
+static struct psci_ops stm32mp_psci_ops = {
+	.cpu_on = stm32mp_cpu_on,
+	.cpu_off = stm32mp_cpu_off,
+	.affinity_info = stm32mp_affinity_info,
+	.migrate_info_type = stm32mp_migrate_info_type,
+	.system_off = stm32mp_system_off,
+	.system_reset = stm32mp_system_reset,
+};
+
+static int stm32mp_init(void)
+{
+	psci_set_ops(&stm32mp_psci_ops);
+
+	return 0;
+}
+postcore_initcall(stm32mp_init);
-- 
2.20.1


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[PATCH v1 12/12] ARM: stm32mp157c-dk2: boot kernel in nonsecure mode

[Ahmad Fatoum]

The mainline kernel expects the firmware to have installed a secure boot
monitor for PSCI. The only means to do this is via the environment,
thus do the necessary changes.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/arm/boards/stm32mp157c-dk2/Makefile             |  1 +
 arch/arm/boards/stm32mp157c-dk2/board.c              | 12 ++++++++++++
 .../defaultenv-dk2/nv/bootm.secure_state             |  1 +
 arch/arm/mach-stm32mp/Kconfig                        |  1 +
 4 files changed, 15 insertions(+)
 create mode 100644 arch/arm/boards/stm32mp157c-dk2/defaultenv-dk2/nv/bootm.secure_state

diff --git a/arch/arm/boards/stm32mp157c-dk2/Makefile b/arch/arm/boards/stm32mp157c-dk2/Makefile
index 092c31d6b28d..03f46111206c 100644
--- a/arch/arm/boards/stm32mp157c-dk2/Makefile
+++ b/arch/arm/boards/stm32mp157c-dk2/Makefile
@@ -1,2 +1,3 @@
 lwl-y += lowlevel.o
 obj-y += board.o
+bbenv-y += defaultenv-dk2
diff --git a/arch/arm/boards/stm32mp157c-dk2/board.c b/arch/arm/boards/stm32mp157c-dk2/board.c
index 5572231d525c..6c4f874d6bd8 100644
--- a/arch/arm/boards/stm32mp157c-dk2/board.c
+++ b/arch/arm/boards/stm32mp157c-dk2/board.c
@@ -5,6 +5,7 @@
 #include <asm/memory.h>
 #include <mach/stm32.h>
 #include <mfd/syscon.h>
+#include <envfs.h>
 
 #define SYSCFG_BOOTR		0x00
 #define SYSCFG_PMCSETR		0x04
@@ -65,6 +66,17 @@ static int dk2_postcore_init(void)
 }
 mem_initcall(dk2_postcore_init);
 
+static int dk2_devices_init(void)
+{
+	if (!of_machine_is_compatible("st,stm32mp157c-dk2"))
+		return 0;
+
+	defaultenv_append_directory(defaultenv_dk2);
+
+	return 0;
+}
+device_initcall(dk2_devices_init);
+
 static int dk2_sysconf_init(void)
 {
 	struct regmap *syscfg;
diff --git a/arch/arm/boards/stm32mp157c-dk2/defaultenv-dk2/nv/bootm.secure_state b/arch/arm/boards/stm32mp157c-dk2/defaultenv-dk2/nv/bootm.secure_state
new file mode 100644
index 000000000000..83bc509e8d95
--- /dev/null
+++ b/arch/arm/boards/stm32mp157c-dk2/defaultenv-dk2/nv/bootm.secure_state
@@ -0,0 +1 @@
+nonsecure
diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
index 94205aaf5508..c0a1c202f7ce 100644
--- a/arch/arm/mach-stm32mp/Kconfig
+++ b/arch/arm/mach-stm32mp/Kconfig
@@ -7,6 +7,7 @@ config ARCH_STM32MP1157
 config MACH_STM32MP157C_DK2
 	select ARCH_STM32MP1157
 	select ARM_USE_COMPRESSED_DTB
+	select ENVIRONMENT_VARIABLES
 	bool "STM32MP157C-DK2 board"
 
 endif
-- 
2.20.1


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Re: [PATCH v1 08/12] ARM: stm32mp157c-dk2: add board-specific sysconf fixups

[Ahmad Fatoum]

On 17/6/19 17:07, Ahmad Fatoum wrote:
> This imports the syscfg configuration done in the vendor U-Boot's
> board_init into barebox. Only part missing is the CONFIG_DM_REGULATOR
> protected clause that adjusts SYSCFG_IOCTRLSETR for operation above
> ~50MHz. These adjustments are only undertaken if VDD < 2.7V as they're
> unsafe otherwise. As the barebox port doesn't yet support querying the
> regulator, skip these adjustments for now.
> 
> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
>  arch/arm/boards/stm32mp157c-dk2/board.c | 94 +++++++++++++++++++++++++
>  1 file changed, 94 insertions(+)
> 
> diff --git a/arch/arm/boards/stm32mp157c-dk2/board.c b/arch/arm/boards/stm32mp157c-dk2/board.c
> index cbfe21db6a8c..5572231d525c 100644
> --- a/arch/arm/boards/stm32mp157c-dk2/board.c
> +++ b/arch/arm/boards/stm32mp157c-dk2/board.c
> @@ -4,6 +4,55 @@
>  #include <init.h>
>  #include <asm/memory.h>
>  #include <mach/stm32.h>
> +#include <mfd/syscon.h>
> +
> +#define SYSCFG_BOOTR		0x00
> +#define SYSCFG_PMCSETR		0x04
> +#define SYSCFG_IOCTRLSETR	0x18
> +#define SYSCFG_ICNR		0x1C
> +#define SYSCFG_CMPCR		0x20
> +#define SYSCFG_CMPENSETR	0x24
> +#define SYSCFG_PMCCLRR		0x44
> +
> +#define SYSCFG_BOOTR_BOOT_MASK		GENMASK(2, 0)
> +#define SYSCFG_BOOTR_BOOTPD_SHIFT	4
> +
> +#define SYSCFG_IOCTRLSETR_HSLVEN_TRACE		BIT(0)
> +#define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI	BIT(1)
> +#define SYSCFG_IOCTRLSETR_HSLVEN_ETH		BIT(2)
> +#define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC		BIT(3)
> +#define SYSCFG_IOCTRLSETR_HSLVEN_SPI		BIT(4)
> +
> +#define SYSCFG_CMPCR_SW_CTRL		BIT(1)
> +#define SYSCFG_CMPCR_READY		BIT(8)
> +
> +#define SYSCFG_CMPENSETR_MPU_EN		BIT(0)
> +
> +#define SYSCFG_PMCSETR_ETH_CLK_SEL	BIT(16)
> +#define SYSCFG_PMCSETR_ETH_REF_CLK_SEL	BIT(17)
> +
> +#define SYSCFG_PMCSETR_ETH_SELMII	BIT(20)
> +
> +#define SYSCFG_PMCSETR_ETH_SEL_MASK	GENMASK(23, 16)
> +#define SYSCFG_PMCSETR_ETH_SEL_GMII_MII	(0 << 21)
> +#define SYSCFG_PMCSETR_ETH_SEL_RGMII	(1 << 21)
> +#define SYSCFG_PMCSETR_ETH_SEL_RMII	(4 << 21)
> +
> +#define pr_debug_syscfg(syscfg, reg) do {			\
> +	int ret;						\
> +	u32 val;						\
> +								\
> +	if (MSG_DEBUG > LOGLEVEL)				\
> +		break;						\
> +								\
> +	ret = regmap_read(syscfg, reg, &val);			\
> +								\
> +	if (ret == 0)						\
> +		pr_debug(#reg "= 0x%08x\n", val);		\
> +	else							\
> +		pr_debug(#reg "= ERROR (%d)\n", ret);		\
> +} while (0)
> +
>  
>  static int dk2_postcore_init(void)
>  {
> @@ -15,3 +64,48 @@ static int dk2_postcore_init(void)
>  	return 0;
>  }
>  mem_initcall(dk2_postcore_init);
> +
> +static int dk2_sysconf_init(void)
> +{
> +	struct regmap *syscfg;
> +	u32 reg;
> +
> +	if (!of_machine_is_compatible("st,stm32mp157c-dk2"))
> +		return 0;
> +
> +	// TODO this function should be skipped if TF-A is used as first stage.
> +	// Any way to determine this at runtime?

Skipping this if TF-A was loaded beforehand seems to be just an optimization
that shouldn't affect correctness. But the PSCI stuff installed by barebox
and TF-A if used may be another matter.

Rouven, any idea how to check if TF-A was first stage? Would checking if barebox
is in non-secure mode work?

> +
> +	syscfg = syscon_regmap_lookup_by_compatible("st,stm32mp157-syscfg");
> +
> +	/* interconnect update : select master using the port 1 */
> +	/* LTDC = AXI_M9 */
> +	/* GPU  = AXI_M8 */
> +	/* for now information is hardcoded */
> +	regmap_write(syscfg, SYSCFG_ICNR, BIT(9));
> +	pr_debug_syscfg(syscfg, SYSCFG_ICNR);
> +
> +	/* disable Pull-Down for boot pin connected to VDD */
> +	regmap_read(syscfg, SYSCFG_BOOTR, &reg);
> +	reg &= ~(SYSCFG_BOOTR_BOOT_MASK << SYSCFG_BOOTR_BOOTPD_SHIFT);
> +	reg |= (reg & SYSCFG_BOOTR_BOOT_MASK) << SYSCFG_BOOTR_BOOTPD_SHIFT;
> +	regmap_write(syscfg, SYSCFG_BOOTR, reg);
> +	pr_debug_syscfg(syscfg, SYSCFG_BOOTR);
> +
> +	// TODO: Port High Speed Low Voltage Pad mode Enable from U-Boot
> +
> +	/* activate automatic I/O compensation
> +	 * warning: need to ensure CSI enabled and ready in clock driver
> +	 */
> +	regmap_write(syscfg, SYSCFG_CMPENSETR, SYSCFG_CMPENSETR_MPU_EN);
> +
> +	do {
> +		regmap_read(syscfg, SYSCFG_CMPCR, &reg);
> +	} while (!(reg & SYSCFG_CMPCR_READY));
> +
> +	regmap_update_bits(syscfg, SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL, 0);
> +	pr_debug_syscfg(syscfg, SYSCFG_CMPCR);
> +
> +	return 0;
> +}
> +coredevice_initcall(dk2_sysconf_init);
> 

-- 
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Re: [PATCH v1 08/12] ARM: stm32mp157c-dk2: add board-specific sysconf fixups

[Rouven Czerwinski]

> Skipping this if TF-A was loaded beforehand seems to be just an
> optimization
> that shouldn't affect correctness. But the PSCI stuff installed by
> barebox
> and TF-A if used may be another matter.
> 
> Rouven, any idea how to check if TF-A was first stage? Would checking
> if barebox
> is in non-secure mode work?

Unfortunately, no. ARMv7a does not provide any means to check whether
the processor is in secure state (which would indicate that no secure
monitor has been installed). Accesses to the secure configuration
register which contain the NS bit will result in an abort, however I
currently don't remember whether this abort is taken in secure or non-
secure mode.

Regards,
Rouven Czerwinski
-- 
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Re: [PATCH v1 00/12] ARM: stm32mp: add drivers for GPIO, pinctrl

[Sascha Hauer]

On Mon, Jun 17, 2019 at 05:07:39PM +0200, Ahmad Fatoum wrote:
> Feedback welcome.
> 
> I still have a patch that ports designware_qos from U-Boot to barebox
> sitting on my branch. It works fine, but it needs refactoring, so it
> can reuse existing functionality in the generic designware MAC driver
> that's already in barebox. That will take a while, but if there's interest
> in it, I can push the current state somwhere till then.
> 
> Cheers,
> Ahmad Fatoum (12):
>   ARM: dts: stm32mp157a-dk1.dts: include upstream dts before barebox'
>   ARM: dts: stm32mp: factor out common DK nodes into dtsi
>   gpiolib: add gpio_get_chip helper
>   driver: add stubs for hardware spinlocks
>   pinctrl: add driver for STM32 GPIO and pin multiplexer
>   ARM: dts: stm32mp157a-dk1: enable heartbeat and error LEDs
>   ARM: stm32mp: turn on GPIO related options
>   ARM: stm32mp157c-dk2: add board-specific sysconf fixups
>   ARM: psci: fix erroneous call of ->system_reset on system_off
>   ARM: sm: move get_gicd_base_address to header for reuse
>   ARM: stm32mp: implement PSCI support
>   ARM: stm32mp157c-dk2: boot kernel in nonsecure mode

Applied, thanks

Sascha


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Re: [PATCH v1 00/12] ARM: stm32mp: add drivers for GPIO, pinctrl

[Ahmad Fatoum]

Hello Sascha,

On 20/6/19 16:32, Sascha Hauer wrote:
> On Mon, Jun 17, 2019 at 05:07:39PM +0200, Ahmad Fatoum wrote:

>> Ahmad Fatoum (12):
>>   ARM: stm32mp157c-dk2: add board-specific sysconf fixups

Please drop this patch from next.

>>   ARM: psci: fix erroneous call of ->system_reset on system_off
>>   ARM: stm32mp: implement PSCI support
>>   ARM: stm32mp157c-dk2: boot kernel in nonsecure mode

as well as these three. These patches duplicate functionality already
existing in the upstream ARM Trusted Firmware-A repository.

STMicro provides two boot chains for the STM32MP. A trusted boot chain,
with the TF-A as the first stage boot loader doing the SDRAM init
and U-Boot as the second stage as well as a simplified one where
U-Boot SPL acts as a first stage.

After talking this over with Lucas, I now see that barebox should
probably not go down this road and instead settle for support of
one of these boot chains.

STMicro's docs[1] state that

> authentication is optional with this boot chain, so it can run on any STM32MP
> security variant (that is, with or without the Secure boot).
> The trusted boot chain is the default solution delivered by STMicroelectronics,
> with a complete feature set (for example, all Flash devices are supported).

Which makes me lean towards settling for TF-A as first stage and have
barebox focus on the second stage instead. Should it turn out, we should
be doing first stage as well, these can always be reinstated in a way that doesn't
break use of TF-A. Dropping them now allows a boot chain with
mainline TF-A -> barebox with my network patches -> mainline Kernel
to function.

>>   ARM: sm: move get_gicd_base_address to header for reuse

Could be removed as well, but it doesn't hurt to leave it in.
Future code for other subarches may need this as well.

[1]: https://wiki.st.com/stm32mpu/wiki/Boot_chains_overview ¶2.2.1

Cheers
Ahmad

> 
> Applied, thanks
> 
> Sascha
> 
> 

-- 
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Re: [PATCH v1 00/12] ARM: stm32mp: add drivers for GPIO, pinctrl

[Ahmad Fatoum]

Sorry,

On 3/7/19 18:51, Ahmad Fatoum wrote:
>   ARM: psci: fix erroneous call of ->system_reset on system_off

this one is a generic fix and should stay. To sum up, please drop:

75624841ec85 ARM: stm32mp157c-dk2: boot kernel in nonsecure mode
cc392cc3b5df ARM: stm32mp: implement PSCI support
e7561dba5791 ARM: stm32mp157c-dk2: add board-specific sysconf fixups

Thanks,
Ahmad

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Re: [PATCH v1 00/12] ARM: stm32mp: add drivers for GPIO, pinctrl

[Sascha Hauer]

On Thu, Jul 04, 2019 at 07:39:40AM +0200, Ahmad Fatoum wrote:
> Sorry,
> 
> On 3/7/19 18:51, Ahmad Fatoum wrote:
> >   ARM: psci: fix erroneous call of ->system_reset on system_off
> 
> this one is a generic fix and should stay. To sum up, please drop:
> 
> 75624841ec85 ARM: stm32mp157c-dk2: boot kernel in nonsecure mode
> cc392cc3b5df ARM: stm32mp: implement PSCI support
> e7561dba5791 ARM: stm32mp157c-dk2: add board-specific sysconf fixups

Ok, did that.

Sascha

-- 
Pengutronix e.K.                           |                             |
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