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From: Steffen Trumtrar <s.trumtrar@pengutronix.de>
To: Barebox List <barebox@lists.infradead.org>
Subject: [PATCH 2/3] ARM: socfpga: cyclone5-system-manager.h: remove defines
Date: Thu, 17 Oct 2019 12:40:40 +0200	[thread overview]
Message-ID: <20191017104041.31923-2-s.trumtrar@pengutronix.de> (raw)
In-Reply-To: <20191017104041.31923-1-s.trumtrar@pengutronix.de>

These defines are common for arria10 and cyclone5.
Instead of having them here, they are moved to drivers/net/designware_socfpga.c.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
 .../include/mach/cyclone5-system-manager.h            | 11 -----------
 1 file changed, 11 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/cyclone5-system-manager.h b/arch/arm/mach-socfpga/include/mach/cyclone5-system-manager.h
index 24f52effd886..7cec60937b84 100644
--- a/arch/arm/mach-socfpga/include/mach/cyclone5-system-manager.h
+++ b/arch/arm/mach-socfpga/include/mach/cyclone5-system-manager.h
@@ -57,15 +57,4 @@ void socfpga_sysmgr_pinmux_init(unsigned long *sys_mgr_init_table, int num);
 #define SYSMGR_FPGAINTF_NAND		(1<<4)
 #define SYSMGR_FPGAINTF_SDMMC		(1<<5)
 
-/* Enumeration: sysmgr::emacgrp::ctrl::physel::enum                        */
-#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
-#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
-#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
-#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0
-#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2
-#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003
-
-#define SYSMGR_FPGAGRP_MODULE  0x00000028
-#define SYSMGR_FPGAGRP_MODULE_EMAC 0x00000004
-
 #endif /* _SYSTEM_MANAGER_H_ */
-- 
2.23.0


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  reply	other threads:[~2019-10-17 10:40 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-17 10:40 [PATCH 1/3] net: designware: socfpga: fix phy setup for Arria10 Steffen Trumtrar
2019-10-17 10:40 ` Steffen Trumtrar [this message]
2019-10-17 10:40 ` [PATCH 3/3] ARM: socfpga: defconfig: enable state_drv Steffen Trumtrar
2019-10-18 10:51 ` [PATCH 1/3] net: designware: socfpga: fix phy setup for Arria10 Sascha Hauer

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