From: Sascha Hauer <s.hauer@pengutronix.de>
To: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Cc: Barebox List <barebox@lists.infradead.org>
Subject: Re: [PATCH 1/3] net: designware: socfpga: fix phy setup for Arria10
Date: Fri, 18 Oct 2019 12:51:59 +0200 [thread overview]
Message-ID: <20191018105159.dwapuqnagow2q3xx@pengutronix.de> (raw)
In-Reply-To: <20191017104041.31923-1-s.trumtrar@pengutronix.de>
On Thu, Oct 17, 2019 at 12:40:39PM +0200, Steffen Trumtrar wrote:
> Barebox-version of the Linux v5.2 patch:
>
> 40ae25505fe834648ce4aa70b073ee934942bfdb
> net: stmmac: socfpga: fix phy and ptp_ref setup for Arria10/Stratix10
>
> On the Arria10, Agilex, and Stratix10 SoC, there are a few differences from
> the Cyclone5 and Arria5:
> - The emac PHY setup bits are in separate registers.
> - The PTP reference clock select mask is different.
> - The register to enable the emac signal from FPGA is different.
>
> Thus, this patch creates a separate function for setting the phy modes on
> Arria10/Agilex/Stratix10. The separation is based a new DTS binding:
> "altr,socfpga-stmmac-a10-s10".
>
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> Signed-off-by: David S. Miller <davem@davemloft.net>
>
> The new DTS binding is already part of v2019.10.0 and the driver doesn't
> probe on Arria10 without the new binding introduced in this patch.
>
> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
> ---
> drivers/net/designware.h | 1 +
> drivers/net/designware_socfpga.c | 133 +++++++++++++++++++++++++++----
> 2 files changed, 118 insertions(+), 16 deletions(-)
Applied, thanks
Sascha
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prev parent reply other threads:[~2019-10-18 10:52 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-17 10:40 Steffen Trumtrar
2019-10-17 10:40 ` [PATCH 2/3] ARM: socfpga: cyclone5-system-manager.h: remove defines Steffen Trumtrar
2019-10-17 10:40 ` [PATCH 3/3] ARM: socfpga: defconfig: enable state_drv Steffen Trumtrar
2019-10-18 10:51 ` Sascha Hauer [this message]
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