From: Du Huanpeng <duhuanpeng@loongson.cn>
To: barebox@lists.infradead.org
Subject: macro about loongson's CPU & SoC
Date: Tue, 26 Nov 2019 19:57:50 +0800 [thread overview]
Message-ID: <20191126115119.GA20169@brew> (raw)
Hello, I find there are some macros about loongson's CPU and SoC,
$ vim barebox/arch/mips/Kconfig
174 config CPU_LOONGSON1B
175 bool "Loongson 1B"
176 depends on SYS_HAS_CPU_LOONGSON1B
177 select CPU_LOONGSON1
178 help
179 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
180 release 2 instruction set.
Here I want to list some Chips from this page:
http://www.loongson.cn/product/
NAME CPU Core(s)
The loongson 3, for series/server & desktop
3A3000/3B3000 GS464E 64bit x4
3A2000/3B2000 GS464E 64bit x4
3B1500 GS464 64bit x8
3A1000 GS464 64bit x4
The loongson 2, for series/low power
2K1000 GS264 64bit x2
2F GS464 64bit x1
2H GS464 64bit x1
The loongson 1, for series/embeded
1C101 GS132R 32bit ?
1D GS132 32bit ?
1C GS232 32bit x1
1B GS232 32bit x1 <-- loongson 1b
1A GS232 32bit x1
the CPU name of LOONGSON1B is socalled GS232, shall we
change CPU_LOONGSON1 to CPU_GS232?
here is a introduce for GS232 in Chinese:
- - - -
龙芯 232 核是一款实现 MIPS32 兼容且支持 EJTAG 调试的双发射处理器,通过采用转移
预测、寄存器重命名、乱序发射、路预测的指令 CACHE、非阻塞的数据 CACHE、写合并收集
等技术来提高流水线的效率。
- - - -
base on this description, is it compact with MIPS32.
for loongson's other cores, shall we define some macro:
CONFIG_CPU_GS232
CONFIG_CPU_GS264
CONFIG_CPU_GS464
Regards,
duhuanpeng
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next reply other threads:[~2019-11-26 11:58 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-26 11:57 Du Huanpeng [this message]
2019-11-26 12:11 ` Antony Pavlov
2019-11-26 13:03 ` Du Huanpeng
2019-11-27 14:01 ` Sascha Hauer
2019-12-02 9:03 ` Du Huanpeng
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