From: Sascha Hauer <s.hauer@pengutronix.de>
To: Giorgio Dal Molin <giorgio.nicole@arcor.de>
Cc: barebox@lists.infradead.org, Ahmad Fatoum <a.fatoum@pengutronix.de>
Subject: Re: barebox image for an spi flash (like m25p0) on an imx7 soc
Date: Thu, 5 Mar 2020 14:24:15 +0100 [thread overview]
Message-ID: <20200305132415.GT3335@pengutronix.de> (raw)
In-Reply-To: <1062353935.2358.1583401816499@mail.vodafone.de>
On Thu, Mar 05, 2020 at 10:50:15AM +0100, Giorgio Dal Molin wrote:
> Hi,
>
> thank you for the quick reply.
>
> here is how I register the bbu for the spi flash:
>
> imx7_bbu_internal_spi_i2c_register_handler("SPI", "/dev/m25p0", BBU_HANDLER_FLAG_DEFAULT);
>
> and here is a hex dump of the spi flash after bb-updating (I hacked the 'cat' command a bit):
>
> imx7d: / cat -h -b 0x450 /dev/m25p0
There's the 'md' command for this purpose ;)
> 0000: 0xfe 0x03 0x00 0xea 0xfe 0xff 0xff 0xea 0xfe 0xff 0xff 0xea 0xfe 0xff 0xff 0xea
> 0010: 0xfe 0xff 0xff 0xea 0xfe 0xff 0xff 0xea 0xfe 0xff 0xff 0xea 0xfe 0xff 0xff 0xea
> 0020: 0x62 0x61 0x72 0x65 0x62 0x6f 0x78 0x00 0x00 0x00 0x00 0x00 0x00 0xf0 0x06 0x00
> 0030: 0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55
> 0040: 0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55
> 0050: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
> ... < zeros > ...
> 03f0: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
> 0400: 0xd1 0x00 0x20 0x40 0x00 0x10 0x00 0x80 0x00 0x00 0x00 0x00 0x2c 0x04 0x00 0x80
> 0410: 0x20 0x04 0x00 0x80 0x00 0x04 0x00 0x80 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
> 0420: 0x00 0x00 0x00 0x80 0x00 0xf0 0x06 0x00 0x00 0x00 0x00 0x00 0xd2 0x01 0xbc 0x40
> 0430: 0xcc 0x01 0x6c 0x04 0x30 0x34 0x00 0x04 0x0f 0x40 0x00 0x05 0x30 0x39 0x10 0x00
> 0440: 0x00 0x00 0x00 0x02 0x30 0x7a 0x00 0x00 0x01 0x04 0x00 0x01 0x30 0x7a 0x01 0xa0
>
> It seems 'reasonable': there's a 0x400 bytes flash header and then the actual image
> starts, but it does not boot.
...
> 03f0: 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
> 0400: 0xd1 0x00 0x20 0x40 0x00 0x10 0x91 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
> 0410: 0x20 0x04 0x91 0x00 0x00 0x04 0x91 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
> 0420: 0x00 0x00 0x91 0x00 0x00 0xa0 0x00 0x00 0x00 0x00 0x00 0x00 0xd2 0x00 0x04 0x40
> 0430: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
> 0440: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
>
>
> The first 4 bites at offset 0x400 are the same but then the u-boot working image is
> different.
Where do you have the SDRAM setup? The U-Boot snippet loads into
internal SRAM which looks like the SDRAM setup is done in code. The
barebox image above loads into SDRAM which of course requires that you
have setup the SDRAM in the DCD table.
Sascha
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next prev parent reply other threads:[~2020-03-05 13:24 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-05 8:26 Giorgio Dal Molin
2020-03-05 9:05 ` Ahmad Fatoum
2020-03-05 9:50 ` Giorgio Dal Molin
2020-03-05 13:24 ` Sascha Hauer [this message]
2020-03-05 13:54 ` Giorgio Dal Molin
2020-03-05 14:20 ` Rouven Czerwinski
2020-03-05 17:11 ` Giorgio
2020-03-06 8:41 ` Giorgio Dal Molin
2020-03-06 13:01 ` Sascha Hauer
2020-03-06 13:46 ` Giorgio Dal Molin
2020-03-06 17:22 ` Giorgio Dal Molin
2020-03-06 10:11 ` Giorgio Dal Molin
2020-03-06 12:59 ` Sascha Hauer
2020-03-06 14:08 ` Giorgio Dal Molin
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