[PATCH 1/3] ARM64: Setup vectors in all lower execption levels

[PATCH 1/3] ARM64: Setup vectors in all lower execption levels

[Sascha Hauer]

barebox on ARM64 often changes the exception level when loading a TF-A
or other secure monitor firmware. Make sure we have setup the vector
table in the exception level we then end up in.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/cpu/interrupts_64.c | 25 ++++++++++++++++---------
 1 file changed, 16 insertions(+), 9 deletions(-)

diff --git a/arch/arm/cpu/interrupts_64.c b/arch/arm/cpu/interrupts_64.c
index e8475d2e47..baccf47808 100644
--- a/arch/arm/cpu/interrupts_64.c
+++ b/arch/arm/cpu/interrupts_64.c
@@ -194,15 +194,22 @@ extern unsigned long vectors;
 
 static int aarch64_init_vectors(void)
 {
-        unsigned int el;
-
-        el = current_el();
-        if (el == 1)
-                asm volatile("msr vbar_el1, %0" : : "r" (&vectors) : "cc");
-        else if (el == 2)
-                asm volatile("msr vbar_el2, %0" : : "r" (&vectors) : "cc");
-        else
-                asm volatile("msr vbar_el3, %0" : : "r" (&vectors) : "cc");
+	unsigned int el;
+
+	el = current_el();
+	switch (el) {
+	case 3:
+		asm volatile("msr vbar_el3, %0" : : "r" (&vectors) : "cc");
+		/* Fall through */
+	case 2:
+		asm volatile("msr vbar_el2, %0" : : "r" (&vectors) : "cc");
+		/* Fall through */
+	case 1:
+		asm volatile("msr vbar_el1, %0" : : "r" (&vectors) : "cc");
+		/* Fall through */
+	default:
+		break;
+	}
 
 	return 0;
 }
-- 
2.26.0.rc2


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[PATCH 2/3] ARM64: attribute argument to create_sections() is 64bit

[Sascha Hauer]

The attribute argument to create_sections() is 64bit, so pass in a
64bit variable. This is done in preparation for using some of the upper
bits in the (UN)CACHED_MEM defines.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/cpu/mmu_64.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/mmu_64.c b/arch/arm/cpu/mmu_64.c
index 98cd4c754e..8181658952 100644
--- a/arch/arm/cpu/mmu_64.c
+++ b/arch/arm/cpu/mmu_64.c
@@ -158,19 +158,21 @@ static void create_sections(uint64_t virt, uint64_t phys, uint64_t size,
 
 int arch_remap_range(void *_start, size_t size, unsigned flags)
 {
+	unsigned long attrs;
+
 	switch (flags) {
 	case MAP_CACHED:
-		flags = CACHED_MEM;
+		attrs = CACHED_MEM;
 		break;
 	case MAP_UNCACHED:
-		flags = UNCACHED_MEM;
+		attrs = UNCACHED_MEM;
 		break;
 	default:
 		return -EINVAL;
 	}
 
 	create_sections((uint64_t)_start, (uint64_t)_start, (uint64_t)size,
-			flags);
+			attrs);
 	return 0;
 }
 
-- 
2.26.0.rc2


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[PATCH 3/3] arm64: Set PXN/UXN attributes for uncached mem

[Sascha Hauer]

The attributes should be set to avoid speculative access to memory-mapped
peripherals.

The patch has been tested with:

noinline unsigned long nox(void)
{
	return get_pc();
}

static void xn_test(void)
{
	void *adr = (void *)SOME_SRAM_ADDRESS;
	unsigned long ret;
	unsigned long (*fn)(void) = adr;

	memcpy(adr, nox, 0x1000);

	sync_caches_for_execution();

	ret = fn();
	printf("pc: 0x%08lx\n", ret);
}

Without this patch nox() gets executed in SRAM, with it runs into a
abort as expected.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/cpu/mmu_64.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/mmu_64.h b/arch/arm/cpu/mmu_64.h
index a2a5477569..f5b7624037 100644
--- a/arch/arm/cpu/mmu_64.h
+++ b/arch/arm/cpu/mmu_64.h
@@ -6,7 +6,8 @@
 			 PTE_BLOCK_AF)
 #define UNCACHED_MEM    (PTE_BLOCK_MEMTYPE(MT_DEVICE_nGnRnE) | \
 			 PTE_BLOCK_OUTER_SHARE | \
-			 PTE_BLOCK_AF)
+			 PTE_BLOCK_AF | \
+			 PTE_BLOCK_UXN)
 
 /*
  * Do it the simple way for now and invalidate the entire tlb
-- 
2.26.0.rc2


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Re: [PATCH 3/3] arm64: Set PXN/UXN attributes for uncached mem

[Ahmad Fatoum]

On 3/31/20 10:01 AM, Sascha Hauer wrote:
> The attributes should be set to avoid speculative access to memory-mapped
> peripherals.
> 
> The patch has been tested with:
> 
> noinline unsigned long nox(void)
> {
> 	return get_pc();
> }
> 
> static void xn_test(void)
> {
> 	void *adr = (void *)SOME_SRAM_ADDRESS;
> 	unsigned long ret;
> 	unsigned long (*fn)(void) = adr;
> 
> 	memcpy(adr, nox, 0x1000);
> 
> 	sync_caches_for_execution();
> 
> 	ret = fn();
> 	printf("pc: 0x%08lx\n", ret);
> }
> 
> Without this patch nox() gets executed in SRAM, with it runs into a
> abort as expected.
> 
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
>  arch/arm/cpu/mmu_64.h | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/cpu/mmu_64.h b/arch/arm/cpu/mmu_64.h
> index a2a5477569..f5b7624037 100644
> --- a/arch/arm/cpu/mmu_64.h
> +++ b/arch/arm/cpu/mmu_64.h
> @@ -6,7 +6,8 @@
>  			 PTE_BLOCK_AF)
>  #define UNCACHED_MEM    (PTE_BLOCK_MEMTYPE(MT_DEVICE_nGnRnE) | \
>  			 PTE_BLOCK_OUTER_SHARE | \
> -			 PTE_BLOCK_AF)
> +			 PTE_BLOCK_AF | \
> +			 PTE_BLOCK_UXN)

Don't we need PXN in EL1?
The commit message also speaks of PXN.

Cheers
Ahmad

>  
>  /*
>   * Do it the simple way for now and invalidate the entire tlb
> 

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Re: [PATCH 3/3] arm64: Set PXN/UXN attributes for uncached mem

[Sascha Hauer]

On Tue, Mar 31, 2020 at 10:33:54AM +0200, Ahmad Fatoum wrote:
> 
> 
> On 3/31/20 10:01 AM, Sascha Hauer wrote:
> > The attributes should be set to avoid speculative access to memory-mapped
> > peripherals.
> > 
> > The patch has been tested with:
> > 
> > noinline unsigned long nox(void)
> > {
> > 	return get_pc();
> > }
> > 
> > static void xn_test(void)
> > {
> > 	void *adr = (void *)SOME_SRAM_ADDRESS;
> > 	unsigned long ret;
> > 	unsigned long (*fn)(void) = adr;
> > 
> > 	memcpy(adr, nox, 0x1000);
> > 
> > 	sync_caches_for_execution();
> > 
> > 	ret = fn();
> > 	printf("pc: 0x%08lx\n", ret);
> > }
> > 
> > Without this patch nox() gets executed in SRAM, with it runs into a
> > abort as expected.
> > 
> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > ---
> >  arch/arm/cpu/mmu_64.h | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> > 
> > diff --git a/arch/arm/cpu/mmu_64.h b/arch/arm/cpu/mmu_64.h
> > index a2a5477569..f5b7624037 100644
> > --- a/arch/arm/cpu/mmu_64.h
> > +++ b/arch/arm/cpu/mmu_64.h
> > @@ -6,7 +6,8 @@
> >  			 PTE_BLOCK_AF)
> >  #define UNCACHED_MEM    (PTE_BLOCK_MEMTYPE(MT_DEVICE_nGnRnE) | \
> >  			 PTE_BLOCK_OUTER_SHARE | \
> > -			 PTE_BLOCK_AF)
> > +			 PTE_BLOCK_AF | \
> > +			 PTE_BLOCK_UXN)
> 
> Don't we need PXN in EL1?

We are not in EL1 currently. What happens if we change the exception
level after the MMU setup? In that case we would have to adjust the
attributes of the existing page tables when doing so. We are currently
not prepared for that so I am not sure how much sense it makes to test
for the EL here.

> The commit message also speaks of PXN.

Yeah, I'll fix that.

Sascha

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
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Re: [PATCH 3/3] arm64: Set PXN/UXN attributes for uncached mem

[Sascha Hauer]

On Tue, Mar 31, 2020 at 11:01:35AM +0200, Sascha Hauer wrote:
> On Tue, Mar 31, 2020 at 10:33:54AM +0200, Ahmad Fatoum wrote:
> > 
> > 
> > On 3/31/20 10:01 AM, Sascha Hauer wrote:
> > > The attributes should be set to avoid speculative access to memory-mapped
> > > peripherals.
> > > 
> > > The patch has been tested with:
> > > 
> > > noinline unsigned long nox(void)
> > > {
> > > 	return get_pc();
> > > }
> > > 
> > > static void xn_test(void)
> > > {
> > > 	void *adr = (void *)SOME_SRAM_ADDRESS;
> > > 	unsigned long ret;
> > > 	unsigned long (*fn)(void) = adr;
> > > 
> > > 	memcpy(adr, nox, 0x1000);
> > > 
> > > 	sync_caches_for_execution();
> > > 
> > > 	ret = fn();
> > > 	printf("pc: 0x%08lx\n", ret);
> > > }
> > > 
> > > Without this patch nox() gets executed in SRAM, with it runs into a
> > > abort as expected.
> > > 
> > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > > ---
> > >  arch/arm/cpu/mmu_64.h | 3 ++-
> > >  1 file changed, 2 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/arch/arm/cpu/mmu_64.h b/arch/arm/cpu/mmu_64.h
> > > index a2a5477569..f5b7624037 100644
> > > --- a/arch/arm/cpu/mmu_64.h
> > > +++ b/arch/arm/cpu/mmu_64.h
> > > @@ -6,7 +6,8 @@
> > >  			 PTE_BLOCK_AF)
> > >  #define UNCACHED_MEM    (PTE_BLOCK_MEMTYPE(MT_DEVICE_nGnRnE) | \
> > >  			 PTE_BLOCK_OUTER_SHARE | \
> > > -			 PTE_BLOCK_AF)
> > > +			 PTE_BLOCK_AF | \
> > > +			 PTE_BLOCK_UXN)
> > 
> > Don't we need PXN in EL1?
> 
> We are not in EL1 currently. What happens if we change the exception
> level after the MMU setup? In that case we would have to adjust the
> attributes of the existing page tables when doing so. We are currently
> not prepared for that so I am not sure how much sense it makes to test
> for the EL here.

Hm, this is no reason for not honoring the current EL in the first
place, I'll update the patch accordingly.

Sascha


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Pengutronix e.K.                           |                             |
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31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
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Re: [PATCH 3/3] arm64: Set PXN/UXN attributes for uncached mem

[Ahmad Fatoum]

Hi,

On 3/31/20 11:20 AM, Sascha Hauer wrote:
> On Tue, Mar 31, 2020 at 11:01:35AM +0200, Sascha Hauer wrote:
>> On Tue, Mar 31, 2020 at 10:33:54AM +0200, Ahmad Fatoum wrote:
>>>
>>>
>>> On 3/31/20 10:01 AM, Sascha Hauer wrote:
>>>> The attributes should be set to avoid speculative access to memory-mapped
>>>> peripherals.
>>>>
>>>> The patch has been tested with:
>>>>
>>>> noinline unsigned long nox(void)
>>>> {
>>>> 	return get_pc();
>>>> }
>>>>
>>>> static void xn_test(void)
>>>> {
>>>> 	void *adr = (void *)SOME_SRAM_ADDRESS;
>>>> 	unsigned long ret;
>>>> 	unsigned long (*fn)(void) = adr;
>>>>
>>>> 	memcpy(adr, nox, 0x1000);
>>>>
>>>> 	sync_caches_for_execution();
>>>>
>>>> 	ret = fn();
>>>> 	printf("pc: 0x%08lx\n", ret);
>>>> }
>>>>
>>>> Without this patch nox() gets executed in SRAM, with it runs into a
>>>> abort as expected.
>>>>
>>>> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
>>>> ---
>>>>  arch/arm/cpu/mmu_64.h | 3 ++-
>>>>  1 file changed, 2 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/arch/arm/cpu/mmu_64.h b/arch/arm/cpu/mmu_64.h
>>>> index a2a5477569..f5b7624037 100644
>>>> --- a/arch/arm/cpu/mmu_64.h
>>>> +++ b/arch/arm/cpu/mmu_64.h
>>>> @@ -6,7 +6,8 @@
>>>>  			 PTE_BLOCK_AF)
>>>>  #define UNCACHED_MEM    (PTE_BLOCK_MEMTYPE(MT_DEVICE_nGnRnE) | \
>>>>  			 PTE_BLOCK_OUTER_SHARE | \
>>>> -			 PTE_BLOCK_AF)
>>>> +			 PTE_BLOCK_AF | \
>>>> +			 PTE_BLOCK_UXN)
>>>
>>> Don't we need PXN in EL1?
>>
>> We are not in EL1 currently. What happens if we change the exception
>> level after the MMU setup? In that case we would have to adjust the
>> attributes of the existing page tables when doing so. We are currently
>> not prepared for that so I am not sure how much sense it makes to test
>> for the EL here.
> 
> Hm, this is no reason for not honoring the current EL in the first
> place, I'll update the patch accordingly.

Not understanding what you mean here, but I'll see in v2. :-)

Cheers,
Ahmad

> 
> Sascha
> 
> 

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Pengutronix e.K.                           |                             |
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[PATCH v2] arm64: Set PXN/UXN attributes for uncached mem

[Sascha Hauer]

The attributes should be set to avoid speculative access to memory-mapped
peripherals.

The patch has been tested with:

noinline unsigned long nox(void)
{
	return get_pc();
}

static void xn_test(void)
{
	void *adr = (void *)SOME_SRAM_ADDRESS;
	unsigned long ret;
	unsigned long (*fn)(void) = adr;

	memcpy(adr, nox, 0x1000);

	sync_caches_for_execution();

	ret = fn();
	printf("pc: 0x%08lx\n", ret);
}

Without this patch nox() gets executed in SRAM, with it runs into a
abort as expected.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
Changes since v1:
- Select correct PXN/UXN bits based on current exception level

 arch/arm/cpu/mmu_64.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/mmu_64.h b/arch/arm/cpu/mmu_64.h
index a2a5477569..f5b7624037 100644
--- a/arch/arm/cpu/mmu_64.h
+++ b/arch/arm/cpu/mmu_64.h
@@ -6,7 +6,8 @@
 			 PTE_BLOCK_AF)
 #define UNCACHED_MEM    (PTE_BLOCK_MEMTYPE(MT_DEVICE_nGnRnE) | \
 			 PTE_BLOCK_OUTER_SHARE | \
-			 PTE_BLOCK_AF)
+			 PTE_BLOCK_AF | \
+			 PTE_BLOCK_UXN)
 
 /*
  * Do it the simple way for now and invalidate the entire tlb
-- 
2.26.0.rc2


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Re: [PATCH v2] arm64: Set PXN/UXN attributes for uncached mem

[Sascha Hauer]

On Tue, Mar 31, 2020 at 12:12:58PM +0200, Sascha Hauer wrote:
> The attributes should be set to avoid speculative access to memory-mapped
> peripherals.
> 
> The patch has been tested with:
> 
> noinline unsigned long nox(void)
> {
> 	return get_pc();
> }
> 
> static void xn_test(void)
> {
> 	void *adr = (void *)SOME_SRAM_ADDRESS;
> 	unsigned long ret;
> 	unsigned long (*fn)(void) = adr;
> 
> 	memcpy(adr, nox, 0x1000);
> 
> 	sync_caches_for_execution();
> 
> 	ret = fn();
> 	printf("pc: 0x%08lx\n", ret);
> }
> 
> Without this patch nox() gets executed in SRAM, with it runs into a
> abort as expected.
> 
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> Changes since v1:
> - Select correct PXN/UXN bits based on current exception level
> 
>  arch/arm/cpu/mmu_64.h | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/cpu/mmu_64.h b/arch/arm/cpu/mmu_64.h
> index a2a5477569..f5b7624037 100644
> --- a/arch/arm/cpu/mmu_64.h
> +++ b/arch/arm/cpu/mmu_64.h
> @@ -6,7 +6,8 @@
>  			 PTE_BLOCK_AF)
>  #define UNCACHED_MEM    (PTE_BLOCK_MEMTYPE(MT_DEVICE_nGnRnE) | \
>  			 PTE_BLOCK_OUTER_SHARE | \
> -			 PTE_BLOCK_AF)
> +			 PTE_BLOCK_AF | \
> +			 PTE_BLOCK_UXN)

Wrong patch, please ignore.

Sascha

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[PATCH v2] arm64: Set PXN/UXN attributes for uncached mem

[Sascha Hauer]

The attributes should be set to avoid speculative access to memory-mapped
peripherals.

The patch has been tested with:

noinline unsigned long nox(void)
{
	return get_pc();
}

static void xn_test(void)
{
	void *adr = (void *)SOME_SRAM_ADDRESS;
	unsigned long ret;
	unsigned long (*fn)(void) = adr;

	memcpy(adr, nox, 0x1000);

	sync_caches_for_execution();

	ret = fn();
	printf("pc: 0x%08lx\n", ret);
}

Without this patch nox() gets executed in SRAM, with it runs into a
abort as expected.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
Changes since v1:
- Select correct PXN/UXN bits based on current exception level

 arch/arm/cpu/mmu-early_64.c |  3 ++-
 arch/arm/cpu/mmu_64.c       |  4 ++--
 arch/arm/cpu/mmu_64.h       | 17 +++++++++++++++++
 3 files changed, 21 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/mmu-early_64.c b/arch/arm/cpu/mmu-early_64.c
index 94e372637a..a7598f28aa 100644
--- a/arch/arm/cpu/mmu-early_64.c
+++ b/arch/arm/cpu/mmu-early_64.c
@@ -67,7 +67,8 @@ void mmu_early_enable(unsigned long membase, unsigned long memsize,
 
 	el = current_el();
 	set_ttbr_tcr_mair(el, ttb, calc_tcr(el, EARLY_BITS_PER_VA), MEMORY_ATTRIBUTES);
-	create_sections((void *)ttb, 0, 0, 1UL << (EARLY_BITS_PER_VA - 1), UNCACHED_MEM);
+	create_sections((void *)ttb, 0, 0, 1UL << (EARLY_BITS_PER_VA - 1),
+			attrs_uncached_mem());
 	create_sections((void *)ttb, membase, membase, memsize, CACHED_MEM);
 	tlb_invalidate();
 	isb();
diff --git a/arch/arm/cpu/mmu_64.c b/arch/arm/cpu/mmu_64.c
index 8181658952..14d955cd96 100644
--- a/arch/arm/cpu/mmu_64.c
+++ b/arch/arm/cpu/mmu_64.c
@@ -165,7 +165,7 @@ int arch_remap_range(void *_start, size_t size, unsigned flags)
 		attrs = CACHED_MEM;
 		break;
 	case MAP_UNCACHED:
-		attrs = UNCACHED_MEM;
+		attrs = attrs_uncached_mem();
 		break;
 	default:
 		return -EINVAL;
@@ -201,7 +201,7 @@ void __mmu_init(bool mmu_on)
 	pr_debug("ttb: 0x%p\n", ttb);
 
 	/* create a flat mapping */
-	create_sections(0, 0, 1UL << (BITS_PER_VA - 1), UNCACHED_MEM);
+	create_sections(0, 0, 1UL << (BITS_PER_VA - 1), attrs_uncached_mem());
 
 	/* Map sdram cached. */
 	for_each_memory_bank(bank)
diff --git a/arch/arm/cpu/mmu_64.h b/arch/arm/cpu/mmu_64.h
index a2a5477569..9bbb62fc6b 100644
--- a/arch/arm/cpu/mmu_64.h
+++ b/arch/arm/cpu/mmu_64.h
@@ -8,6 +8,23 @@
 			 PTE_BLOCK_OUTER_SHARE | \
 			 PTE_BLOCK_AF)
 
+static inline unsigned long attrs_uncached_mem(void)
+{
+	unsigned long attrs = UNCACHED_MEM;
+
+	switch (current_el()) {
+	case 3:
+	case 2:
+		attrs |= PTE_BLOCK_UXN;
+		break;
+	default:
+		attrs |= PTE_BLOCK_UXN | PTE_BLOCK_PXN;
+		break;
+	}
+
+	return attrs;
+}
+
 /*
  * Do it the simple way for now and invalidate the entire tlb
  */
-- 
2.26.0.rc2


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Re: [PATCH v2] arm64: Set PXN/UXN attributes for uncached mem

[Ahmad Fatoum]

Hi,

On 3/31/20 12:17 PM, Sascha Hauer wrote:
> The attributes should be set to avoid speculative access to memory-mapped
> peripherals.
> 
> The patch has been tested with:
> 
> noinline unsigned long nox(void)
> {
> 	return get_pc();
> }
> 
> static void xn_test(void)
> {
> 	void *adr = (void *)SOME_SRAM_ADDRESS;
> 	unsigned long ret;
> 	unsigned long (*fn)(void) = adr;
> 
> 	memcpy(adr, nox, 0x1000);
> 
> 	sync_caches_for_execution();
> 
> 	ret = fn();
> 	printf("pc: 0x%08lx\n", ret);
> }
> 
> Without this patch nox() gets executed in SRAM, with it runs into a
> abort as expected.

Looks good to me.
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>

> 
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> Changes since v1:
> - Select correct PXN/UXN bits based on current exception level
> 
>  arch/arm/cpu/mmu-early_64.c |  3 ++-
>  arch/arm/cpu/mmu_64.c       |  4 ++--
>  arch/arm/cpu/mmu_64.h       | 17 +++++++++++++++++
>  3 files changed, 21 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/cpu/mmu-early_64.c b/arch/arm/cpu/mmu-early_64.c
> index 94e372637a..a7598f28aa 100644
> --- a/arch/arm/cpu/mmu-early_64.c
> +++ b/arch/arm/cpu/mmu-early_64.c
> @@ -67,7 +67,8 @@ void mmu_early_enable(unsigned long membase, unsigned long memsize,
>  
>  	el = current_el();
>  	set_ttbr_tcr_mair(el, ttb, calc_tcr(el, EARLY_BITS_PER_VA), MEMORY_ATTRIBUTES);
> -	create_sections((void *)ttb, 0, 0, 1UL << (EARLY_BITS_PER_VA - 1), UNCACHED_MEM);
> +	create_sections((void *)ttb, 0, 0, 1UL << (EARLY_BITS_PER_VA - 1),
> +			attrs_uncached_mem());
>  	create_sections((void *)ttb, membase, membase, memsize, CACHED_MEM);
>  	tlb_invalidate();
>  	isb();
> diff --git a/arch/arm/cpu/mmu_64.c b/arch/arm/cpu/mmu_64.c
> index 8181658952..14d955cd96 100644
> --- a/arch/arm/cpu/mmu_64.c
> +++ b/arch/arm/cpu/mmu_64.c
> @@ -165,7 +165,7 @@ int arch_remap_range(void *_start, size_t size, unsigned flags)
>  		attrs = CACHED_MEM;
>  		break;
>  	case MAP_UNCACHED:
> -		attrs = UNCACHED_MEM;
> +		attrs = attrs_uncached_mem();
>  		break;
>  	default:
>  		return -EINVAL;
> @@ -201,7 +201,7 @@ void __mmu_init(bool mmu_on)
>  	pr_debug("ttb: 0x%p\n", ttb);
>  
>  	/* create a flat mapping */
> -	create_sections(0, 0, 1UL << (BITS_PER_VA - 1), UNCACHED_MEM);
> +	create_sections(0, 0, 1UL << (BITS_PER_VA - 1), attrs_uncached_mem());
>  
>  	/* Map sdram cached. */
>  	for_each_memory_bank(bank)
> diff --git a/arch/arm/cpu/mmu_64.h b/arch/arm/cpu/mmu_64.h
> index a2a5477569..9bbb62fc6b 100644
> --- a/arch/arm/cpu/mmu_64.h
> +++ b/arch/arm/cpu/mmu_64.h
> @@ -8,6 +8,23 @@
>  			 PTE_BLOCK_OUTER_SHARE | \
>  			 PTE_BLOCK_AF)
>  
> +static inline unsigned long attrs_uncached_mem(void)
> +{
> +	unsigned long attrs = UNCACHED_MEM;
> +
> +	switch (current_el()) {
> +	case 3:
> +	case 2:
> +		attrs |= PTE_BLOCK_UXN;
> +		break;
> +	default:
> +		attrs |= PTE_BLOCK_UXN | PTE_BLOCK_PXN;
> +		break;
> +	}
> +
> +	return attrs;
> +}
> +
>  /*
>   * Do it the simple way for now and invalidate the entire tlb
>   */
> 

-- 
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