From: Lucas Stach <l.stach@pengutronix.de>
To: barebox@lists.infradead.org
Subject: [PATCH] net: designware: eqos: attach PHY earlier
Date: Mon, 11 May 2020 18:50:38 +0200 [thread overview]
Message-ID: <20200511165038.22358-1-l.stach@pengutronix.de> (raw)
If the PHY isn't driving the refclock, the software reset of the
controller will time out. Some PHYs need some board specific
configuration to properly drive the reflock. Attach the PHY before
attempting the software reset, so PHY fixups have a chance to run.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
drivers/net/designware_eqos.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/net/designware_eqos.c b/drivers/net/designware_eqos.c
index cb52f3942d86..d2baaeaf6372 100644
--- a/drivers/net/designware_eqos.c
+++ b/drivers/net/designware_eqos.c
@@ -360,6 +360,11 @@ static int eqos_start(struct eth_device *edev)
int ret;
int i;
+ ret = phy_device_connect(edev, &eqos->miibus, eqos->phy_addr,
+ eqos->ops->adjust_link, 0, eqos->interface);
+ if (ret)
+ return ret;
+
setbits_le32(&eqos->dma_regs->mode, EQOS_DMA_MODE_SWR);
ret = readl_poll_timeout(&eqos->dma_regs->mode, mode_set,
@@ -379,11 +384,6 @@ static int eqos_start(struct eth_device *edev)
val = (rate / USEC_PER_SEC) - 1; /* -1 because the data sheet says so */
writel(val, &eqos->mac_regs->us_tic_counter);
- ret = phy_device_connect(edev, &eqos->miibus, eqos->phy_addr,
- eqos->ops->adjust_link, 0, eqos->interface);
- if (ret)
- return ret;
-
/* Before we reset the mac, we must insure the PHY is not powered down
* as the dw controller needs all clock domains to be running, including
* the PHY clock, to come out of a mac reset. */
--
2.20.1
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next reply other threads:[~2020-05-11 16:50 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-11 16:50 Lucas Stach [this message]
2020-05-12 5:44 ` Ahmad Fatoum
2020-05-12 7:52 ` Sascha Hauer
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