* [PATCH v1 2/2] net: phy: micrel: backport ksz9031 phy-mode support
2020-06-16 8:41 [PATCH v1 1/2] net: phy: port phy_interface_is_rgmii() from kernel Oleksij Rempel
@ 2020-06-16 8:41 ` Oleksij Rempel
2020-06-17 8:38 ` [PATCH v1 1/2] net: phy: port phy_interface_is_rgmii() from kernel Sascha Hauer
1 sibling, 0 replies; 3+ messages in thread
From: Oleksij Rempel @ 2020-06-16 8:41 UTC (permalink / raw)
To: barebox; +Cc: Oleksij Rempel
this patch will allow to use proper clock skew configuration from
devicetree instead of using board specific fixups.
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
---
drivers/net/phy/micrel.c | 103 +++++++++++++++++++++++++++++++++++++++
1 file changed, 103 insertions(+)
diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index 8f0b81d8fa..c13f80cf40 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -18,6 +18,7 @@
#include <linux/ethtool.h>
#include <linux/phy.h>
#include <linux/micrel_phy.h>
+#include <linux/bitfield.h>
/* Operation Mode Strap Override */
#define MII_KSZPHY_OMSO 0x16
@@ -155,9 +156,50 @@ static int ksz9021_config_init(struct phy_device *phydev)
/* MMD Address 0x2 */
#define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
+#define MII_KSZ9031RN_RX_CTL_M GENMASK(7, 4)
+#define MII_KSZ9031RN_TX_CTL_M GENMASK(3, 0)
+
#define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
+#define MII_KSZ9031RN_RXD3 GENMASK(15, 12)
+#define MII_KSZ9031RN_RXD2 GENMASK(11, 8)
+#define MII_KSZ9031RN_RXD1 GENMASK(7, 4)
+#define MII_KSZ9031RN_RXD0 GENMASK(3, 0)
+
#define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
+#define MII_KSZ9031RN_TXD3 GENMASK(15, 12)
+#define MII_KSZ9031RN_TXD2 GENMASK(11, 8)
+#define MII_KSZ9031RN_TXD1 GENMASK(7, 4)
+#define MII_KSZ9031RN_TXD0 GENMASK(3, 0)
+
#define MII_KSZ9031RN_CLK_PAD_SKEW 8
+#define MII_KSZ9031RN_GTX_CLK GENMASK(9, 5)
+#define MII_KSZ9031RN_RX_CLK GENMASK(4, 0)
+
+/* KSZ9031 has internal RGMII_IDRX = 1.2ns and RGMII_IDTX = 0ns. To
+ * provide different RGMII options we need to configure delay offset
+ * for each pad relative to build in delay.
+ */
+/* keep rx as "No delay adjustment" and set rx_clk to +0.60ns to get delays of
+ * 1.80ns
+ */
+#define RX_ID 0x7
+#define RX_CLK_ID 0x19
+
+/* set rx to +0.30ns and rx_clk to -0.90ns to compensate the
+ * internal 1.2ns delay.
+ */
+#define RX_ND 0xc
+#define RX_CLK_ND 0x0
+
+/* set tx to -0.42ns and tx_clk to +0.96ns to get 1.38ns delay */
+#define TX_ID 0x0
+#define TX_CLK_ID 0x1f
+
+/* set tx and tx_clk to "No delay adjustment" to keep 0ns
+ * dealy
+ */
+#define TX_ND 0x7
+#define TX_CLK_ND 0xf
static int ksz9031_of_load_skew_values(struct phy_device *phydev,
const struct device_node *of_node,
@@ -206,6 +248,61 @@ static int ksz9031_center_flp_timing(struct phy_device *phydev)
return genphy_restart_aneg(phydev);
}
+static int ksz9031_config_rgmii_delay(struct phy_device *phydev)
+{
+ u16 rx, tx, rx_clk, tx_clk;
+
+ switch (phydev->interface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ tx = TX_ND;
+ tx_clk = TX_CLK_ND;
+ rx = RX_ND;
+ rx_clk = RX_CLK_ND;
+ break;
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ tx = TX_ID;
+ tx_clk = TX_CLK_ID;
+ rx = RX_ID;
+ rx_clk = RX_CLK_ID;
+ break;
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ tx = TX_ND;
+ tx_clk = TX_CLK_ND;
+ rx = RX_ID;
+ rx_clk = RX_CLK_ID;
+ break;
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ tx = TX_ID;
+ tx_clk = TX_CLK_ID;
+ rx = RX_ND;
+ rx_clk = RX_CLK_ND;
+ break;
+ default:
+ return 0;
+ }
+
+ phy_write_mmd_indirect(phydev, MII_KSZ9031RN_CONTROL_PAD_SKEW, 2,
+ FIELD_PREP(MII_KSZ9031RN_RX_CTL_M, rx) |
+ FIELD_PREP(MII_KSZ9031RN_TX_CTL_M, tx));
+
+ phy_write_mmd_indirect(phydev, MII_KSZ9031RN_RX_DATA_PAD_SKEW, 2,
+ FIELD_PREP(MII_KSZ9031RN_RXD3, rx) |
+ FIELD_PREP(MII_KSZ9031RN_RXD2, rx) |
+ FIELD_PREP(MII_KSZ9031RN_RXD1, rx) |
+ FIELD_PREP(MII_KSZ9031RN_RXD0, rx));
+
+ phy_write_mmd_indirect(phydev, MII_KSZ9031RN_TX_DATA_PAD_SKEW, 2,
+ FIELD_PREP(MII_KSZ9031RN_TXD3, tx) |
+ FIELD_PREP(MII_KSZ9031RN_TXD2, tx) |
+ FIELD_PREP(MII_KSZ9031RN_TXD1, tx) |
+ FIELD_PREP(MII_KSZ9031RN_TXD0, tx));
+
+ phy_write_mmd_indirect(phydev, MII_KSZ9031RN_CLK_PAD_SKEW, 2,
+ FIELD_PREP(MII_KSZ9031RN_GTX_CLK, tx_clk) |
+ FIELD_PREP(MII_KSZ9031RN_RX_CLK, rx_clk));
+ return 0;
+}
+
static int ksz9031_config_init(struct phy_device *phydev)
{
const struct device_d *dev = &phydev->dev;
@@ -226,6 +323,12 @@ static int ksz9031_config_init(struct phy_device *phydev)
of_node = dev->parent->device_node;
if (of_node) {
+ if (phy_interface_is_rgmii(phydev)) {
+ ret = ksz9031_config_rgmii_delay(phydev);
+ if (ret < 0)
+ return ret;
+ }
+
ksz9031_of_load_skew_values(phydev, of_node,
MII_KSZ9031RN_CLK_PAD_SKEW, 5,
clk_skews, 2);
--
2.27.0
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^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH v1 1/2] net: phy: port phy_interface_is_rgmii() from kernel
2020-06-16 8:41 [PATCH v1 1/2] net: phy: port phy_interface_is_rgmii() from kernel Oleksij Rempel
2020-06-16 8:41 ` [PATCH v1 2/2] net: phy: micrel: backport ksz9031 phy-mode support Oleksij Rempel
@ 2020-06-17 8:38 ` Sascha Hauer
1 sibling, 0 replies; 3+ messages in thread
From: Sascha Hauer @ 2020-06-17 8:38 UTC (permalink / raw)
To: Oleksij Rempel; +Cc: barebox
On Tue, Jun 16, 2020 at 10:41:32AM +0200, Oleksij Rempel wrote:
> and remove duplicates from other drivers
>
> Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
> ---
> drivers/net/phy/dp83867.c | 6 ------
> drivers/net/phy/marvell.c | 6 ------
> include/linux/phy.h | 21 +++++++++++++++++++++
> 3 files changed, 21 insertions(+), 12 deletions(-)
Applied, thanks
Sascha
>
> diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
> index b3328b7e44..8e6f198ca2 100644
> --- a/drivers/net/phy/dp83867.c
> +++ b/drivers/net/phy/dp83867.c
> @@ -177,12 +177,6 @@ static int dp83867_of_init(struct phy_device *phydev)
> &dp83867->fifo_depth);
> }
>
> -static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
> -{
> - return phydev->interface >= PHY_INTERFACE_MODE_RGMII &&
> - phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
> -}
> -
> static inline bool phy_interface_is_sgmii(struct phy_device *phydev)
> {
> return phydev->interface == PHY_INTERFACE_MODE_SGMII ||
> diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
> index 73d6453b36..af39ed68fd 100644
> --- a/drivers/net/phy/marvell.c
> +++ b/drivers/net/phy/marvell.c
> @@ -168,12 +168,6 @@ static int marvell_read_status(struct phy_device *phydev)
>
> #define MII_88E1510_GEN_CTRL_REG_1 0x14
>
> -static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
> -{
> - return phydev->interface >= PHY_INTERFACE_MODE_RGMII &&
> - phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
> -};
> -
> /*
> * Set and/or override some configuration registers based on the
> * marvell,reg-init property stored in the of_node for the phydev.
> diff --git a/include/linux/phy.h b/include/linux/phy.h
> index a9fdf44f1a..eec1332c9d 100644
> --- a/include/linux/phy.h
> +++ b/include/linux/phy.h
> @@ -353,6 +353,27 @@ static inline int phy_clear_bits(struct phy_device *phydev, u32 regnum, u16 val)
> return phy_modify(phydev, regnum, val, 0);
> }
>
> +/**
> + * phy_interface_mode_is_rgmii - Convenience function for testing if a
> + * PHY interface mode is RGMII (all variants)
> + * @mode: the phy_interface_t enum
> + */
> +static inline bool phy_interface_mode_is_rgmii(phy_interface_t mode)
> +{
> + return mode >= PHY_INTERFACE_MODE_RGMII &&
> + mode <= PHY_INTERFACE_MODE_RGMII_TXID;
> +};
> +
> +/**
> + * phy_interface_is_rgmii - Convenience function for testing if a PHY interface
> + * is RGMII (all variants)
> + * @phydev: the phy_device struct
> + */
> +static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
> +{
> + return phy_interface_mode_is_rgmii(phydev->interface);
> +};
> +
> int phy_device_connect(struct eth_device *dev, struct mii_bus *bus, int addr,
> void (*adjust_link) (struct eth_device *edev),
> u32 flags, phy_interface_t interface);
> --
> 2.27.0
>
>
> _______________________________________________
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>
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^ permalink raw reply [flat|nested] 3+ messages in thread