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From: Marco Felsch <m.felsch@pengutronix.de>
To: barebox@lists.infradead.org
Subject: [PATCH 3/3] ARM: i.MX: setup ENET_CLK_SEL in imx6_init for every imx6q/imx6d
Date: Thu,  6 Aug 2020 11:29:19 +0200	[thread overview]
Message-ID: <20200806092919.1892-3-m.felsch@pengutronix.de> (raw)
In-Reply-To: <20200806092919.1892-1-m.felsch@pengutronix.de>

Setup the ENET TX reference clk to get it from the internal clock from
anatop. This is the default value for newer imx6 processors like: 6sx,
6ul, 6ull. So it should be safe to set it as default for imx6q/d too.

It will be output on the pad if ENET_REF_CLK is muxed which can be used
to clock a phy.

While on it replace the current 'magic' value by the new introduced
definition.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
 arch/arm/mach-imx/imx6.c | 24 ++++++++++++++++++------
 1 file changed, 18 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index 6a9ea23c71..f325e698fa 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -160,16 +160,28 @@ static void imx6_setup_ipu_qos(void)
 	}
 }
 
-static void imx6ul_enet_clk_init(void)
+static void imx6_enet_clk_init(void)
 {
-	void __iomem *gprbase = IOMEM(MX6_IOMUXC_BASE_ADDR) + 0x4000;
-	uint32_t val;
+	void __iomem *gprbase;
+	uint32_t val, bitmask;
 
-	if (!cpu_mx6_is_mx6ul() && !cpu_mx6_is_mx6ull())
+	switch (imx6_cpu_type()) {
+	case IMX6_CPUTYPE_IMX6D:
+	case IMX6_CPUTYPE_IMX6Q:
+		gprbase = IOMEM(MX6_IOMUXC_BASE_ADDR);
+		bitmask = IMX6Q_GPR1_ENET_CLK_SEL_ANATOP;
+		break;
+	case IMX6_CPUTYPE_IMX6UL:
+	case IMX6_CPUTYPE_IMX6ULL:
+		gprbase = IOMEM(MX6_IOMUXC_BASE_ADDR) + 0x4000;
+		bitmask = IMX6UL_GPR1_ENET_CLK_OUTPUT;
+		break;
+	default:
 		return;
+	}
 
 	val = readl(gprbase + IOMUXC_GPR1);
-	val |= (0x3 << 17);
+	val |= bitmask;
 	writel(val, gprbase + IOMUXC_GPR1);
 }
 
@@ -264,7 +276,7 @@ int imx6_init(void)
 	pr_info("%s unique ID: %llx\n", cputypestr, mx6_uid);
 
 	imx6_setup_ipu_qos();
-	imx6ul_enet_clk_init();
+	imx6_enet_clk_init();
 
 	pfuze_register_init_callback(imx6_register_poweroff_init);
 
-- 
2.20.1


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  parent reply	other threads:[~2020-08-06  9:29 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-06  9:29 [PATCH 1/3] ARM: i.MX6 dtsi: add enet_out clock Marco Felsch
2020-08-06  9:29 ` [PATCH 2/3] ARM: imx6ul: add fec bits to GPR syscon definition Marco Felsch
2020-08-06  9:29 ` Marco Felsch [this message]
2020-08-10  7:16   ` [PATCH 3/3] ARM: i.MX: setup ENET_CLK_SEL in imx6_init for every imx6q/imx6d Sascha Hauer
2020-08-10  8:38     ` Marco Felsch

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