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From: Sascha Hauer <s.hauer@pengutronix.de>
To: Marco Felsch <m.felsch@pengutronix.de>
Cc: barebox@lists.infradead.org
Subject: Re: [PATCH 3/3] ARM: i.MX: setup ENET_CLK_SEL in imx6_init for every imx6q/imx6d
Date: Mon, 10 Aug 2020 09:16:14 +0200	[thread overview]
Message-ID: <20200810071614.GW31536@pengutronix.de> (raw)
In-Reply-To: <20200806092919.1892-3-m.felsch@pengutronix.de>

Hi Marco,

On Thu, Aug 06, 2020 at 11:29:19AM +0200, Marco Felsch wrote:
> Setup the ENET TX reference clk to get it from the internal clock from
> anatop. This is the default value for newer imx6 processors like: 6sx,
> 6ul, 6ull. So it should be safe to set it as default for imx6q/d too.

I don't follow this reasoning. We only ever know the boards that are
unhappy with the reset default, because these are the ones that change
it. Now if we change the register default we can't know which boards
stop working because they relied on the previous reset default value.

Here is an example from U-Boot where this bit is explicitly cleared:

board/tqc/tqma6/tqma6_mba6.c:85: clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);

We support this board in barebox as well and it might break with your
change, so I don't think this patch is a good idea.

Sascha

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  reply	other threads:[~2020-08-10  7:16 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-06  9:29 [PATCH 1/3] ARM: i.MX6 dtsi: add enet_out clock Marco Felsch
2020-08-06  9:29 ` [PATCH 2/3] ARM: imx6ul: add fec bits to GPR syscon definition Marco Felsch
2020-08-06  9:29 ` [PATCH 3/3] ARM: i.MX: setup ENET_CLK_SEL in imx6_init for every imx6q/imx6d Marco Felsch
2020-08-10  7:16   ` Sascha Hauer [this message]
2020-08-10  8:38     ` Marco Felsch

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