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[193.232.173.35]) by smtp.gmail.com with ESMTPSA id m24sm750795lfq.184.2021.04.01.22.56.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 01 Apr 2021 22:56:14 -0700 (PDT) Date: Fri, 2 Apr 2021 08:56:13 +0300 From: Antony Pavlov To: Ahmad Fatoum Cc: barebox@lists.infradead.org Message-Id: <20210402085613.9a8dd5ecb960a47faa3eaa90@gmail.com> In-Reply-To: <20210324082304.30858-1-a.fatoum@pengutronix.de> References: <20210324082304.30858-1-a.fatoum@pengutronix.de> X-Mailer: Sylpheed 3.7.0 (GTK+ 2.24.32; i686-pc-linux-gnu) Mime-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210402_065618_373013_2D659DCE X-CRM114-Status: GOOD ( 23.01 ) X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "barebox" X-SA-Exim-Connect-IP: 2001:8b0:10b:1:d65d:64ff:fe57:4e05 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.ext.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-2.7 required=4.0 tests=AWL,BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, NICE_REPLY_A,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: Re: [PATCH master 1/3] RISC-V: cpu: request stack memory region X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.ext.pengutronix.de) On Wed, 24 Mar 2021 09:23:02 +0100 Ahmad Fatoum wrote: Current RISC-V erizo barebox master succesfully runs on QEMU but hangs on FPGA. git bisection shows this: barebox$ git bisect good 809e66d4ef ... barebox$ git bisect bad fef19e17f651a7f4b6063a76c506a67cabfe4a69 is the first bad commit commit fef19e17f651a7f4b6063a76c506a67cabfe4a69 Author: Ahmad Fatoum Date: Wed Mar 24 09:23:02 2021 +0100 RISC-V: cpu: request stack memory region I see that request_sdram_region("stack", ...) hangs in input_data_len(). On FPGA I load barebox image at 0x80000000 (erizo RAM start) not at 0x0 (link address). The problem is that input_data_end in input_data_len() contains link-time address, not actual run-time address. I have added this hack --- a/arch/riscv/boot/uncompress.c +++ b/arch/riscv/boot/uncompress.c @@ -46,7 +46,7 @@ void __noreturn barebox_pbl_start(unsigned long membase, = unsigned long memsize, relocate_to_adr(membase); = pg_len =3D pg_end - pg_start; - uncompressed_len =3D input_data_len(); + uncompressed_len =3D get_unaligned((const u32 *)(input_data_end - 4= + get_runtime_offset())); = barebox_base =3D riscv_mem_barebox_image(membase, endmem, uncompressed_len + MAX_BSS_S= IZE); Alas, this hack does not fix the problem completely. > Now that the stack base region is determined dynamically, > mem_malloc_resource can no longer reserve the stack space. > Do as ARM does and add a RISC-V specific initcall to reserve > the main thread's stack space. > = > Reported-by: Antony Pavlov > Signed-off-by: Ahmad Fatoum > --- > Fix for master as otherwise stack could be overwritten at runtime > --- > arch/riscv/cpu/core.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > = > diff --git a/arch/riscv/cpu/core.c b/arch/riscv/cpu/core.c > index bdcd500ed748..982d378eddec 100644 > --- a/arch/riscv/cpu/core.c > +++ b/arch/riscv/cpu/core.c > @@ -2,6 +2,9 @@ > /* > * Copyright (C) 2012 Regents of the University of California > * Copyright (C) 2017 SiFive > + * Copyright (C) 2021 Ahmad Fatoum, Pengutronix > + * > + * Common RISC-V core initcalls. > * > * All RISC-V systems have a timer attached to every hart. These timers= can > * either be read from the "time" and "timeh" CSRs, and can use the SBI = to > @@ -14,8 +17,17 @@ > #include > #include > #include > +#include > +#include > #include > = > +static int riscv_request_stack(void) > +{ > + extern unsigned long riscv_stack_top; > + return PTR_ERR_OR_ZERO(request_sdram_region("stack", riscv_stack_top - = STACK_SIZE, STACK_SIZE)); > +} > +coredevice_initcall(riscv_request_stack); > + > static struct device_d timer_dev; > = > static int riscv_probe(struct device_d *parent) > -- = > 2.29.2 > = -- = Best regards, =A0 Antony Pavlov _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox