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[193.232.173.35]) by smtp.gmail.com with ESMTPSA id o9sm608105lfi.175.2021.05.05.08.23.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 05 May 2021 08:23:47 -0700 (PDT) Date: Wed, 5 May 2021 18:23:46 +0300 From: Antony Pavlov To: Jan =?ISO-8859-1?Q?L=FCbbe?= Cc: barebox@lists.infradead.org, Ahmad Fatoum Message-Id: <20210505182346.f2fa9326b2994a3821b140a5@gmail.com> In-Reply-To: <1f4419dcaf9646155cbb8e16aab21b0fcd04a976.camel@pengutronix.de> References: <20210505100900.88141-1-antonynpavlov@gmail.com> <20210505100900.88141-8-antonynpavlov@gmail.com> <1f4419dcaf9646155cbb8e16aab21b0fcd04a976.camel@pengutronix.de> X-Mailer: Sylpheed 3.7.0 (GTK+ 2.24.32; i686-pc-linux-gnu) Mime-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210505_082350_352694_F177ADC7 X-CRM114-Status: GOOD ( 14.67 ) X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "barebox" X-SA-Exim-Connect-IP: 2001:8b0:10b:1:d65d:64ff:fe57:4e05 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.ext.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-2.7 required=4.0 tests=AWL,BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, NICE_REPLY_A,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: Re: [PATCH 7/9] RISC-V: add initial LiteX SoC support X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.ext.pengutronix.de) On Wed, 05 May 2021 12:45:23 +0200 Jan L=FCbbe wrote: > On Wed, 2021-05-05 at 13:08 +0300, Antony Pavlov wrote: > > LiteX is a Migen-based System on Chip, supporting softcore > > VexRiscv CPU, a 32-bits Linux Capable RISC-V CPU. > > = > > See https://github.com/enjoy-digital/litex and > > https://github.com/litex-hub/linux-on-litex-vexriscv > > for details. > > = > > Signed-off-by: Antony Pavlov > > --- > > = > > = > = > = > > +config MACH_LITEX > > + bool "litex family" > > + select ARCH_RV32I > > + select HAS_DEBUG_LL > > + select HAS_NMON > > + select USE_COMPRESSED_DTB > > + select RISCV_SBI > > + > = > = > Hmm, there is also https://github.com/litex-hub/linux-on-litex-rocket/ wh= ich > uses the 64-bit RocketChip CPU. How would that fit into this naming schem= e? > Would it be a different MACH? Rocket is a 64-bit core, VexRiscv is a 32-bit core. All LiteX family SoC use the same peripheral IP cores, but different CPU co= res. The situation is similar to MIPS Malta FPGA devboard, main FPGA can be burn= ed with very different CPU bitstreams: config MIPS_MALTA bool "MIPS Malta board" ... select SYS_HAS_CPU_MIPS32_R1 select SYS_HAS_CPU_MIPS32_R2 select SYS_HAS_CPU_MIPS32_R3_5 select SYS_HAS_CPU_MIPS32_R5 select SYS_HAS_CPU_MIPS32_R6 select SYS_HAS_CPU_MIPS64_R1 select SYS_HAS_CPU_MIPS64_R2 select SYS_HAS_CPU_MIPS64_R6 select SYS_HAS_CPU_NEVADA select SYS_HAS_CPU_RM7000 I'll investigate the problem more carefully. Thanks for noting! -- = Best regards, =A0 Antony Pavlov _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox