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[193.232.173.35]) by smtp.gmail.com with ESMTPSA id f3sm1834676lja.107.2021.05.07.07.25.28 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 May 2021 07:25:29 -0700 (PDT) Date: Fri, 7 May 2021 17:25:27 +0300 From: Antony Pavlov To: Ahmad Fatoum Message-Id: <20210507172527.cf80cf7cb749560d2e8200cd@gmail.com> In-Reply-To: References: <20210506220834.223350-1-antonynpavlov@gmail.com> <20210506220834.223350-3-antonynpavlov@gmail.com> X-Mailer: Sylpheed 3.7.0 (GTK+ 2.24.32; i686-pc-linux-gnu) Mime-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210507_072531_746345_744F6CC8 X-CRM114-Status: GOOD ( 29.62 ) X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: barebox@lists.infradead.org Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "barebox" X-SA-Exim-Connect-IP: 2001:8b0:10b:1:d65d:64ff:fe57:4e05 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.ext.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-2.6 required=4.0 tests=AWL,BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, NICE_REPLY_A,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: Re: [PATCH v2 02/11] RISC-V: make RISCV_SBI and RISCV_M_MODE explicitly mutually exclusive X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.ext.pengutronix.de) On Fri, 7 May 2021 13:42:00 +0200 Ahmad Fatoum wrote: Hi Ahmad! > Hello, > = > On 07.05.21 00:08, Antony Pavlov wrote: > > Signed-off-by: Antony Pavlov > > --- > > arch/riscv/Kconfig | 22 ++++++++++++---------- > > arch/riscv/Kconfig.socs | 4 +++- > > arch/riscv/configs/erizo_generic_defconfig | 1 + > > 3 files changed, 16 insertions(+), 11 deletions(-) > > = > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > > index a4aa799acf..dcff00d63f 100644 > > --- a/arch/riscv/Kconfig > > +++ b/arch/riscv/Kconfig > > @@ -38,6 +38,18 @@ config ARCH_RV64I > > = > > endchoice > > = > > +choice > > + prompt "Privilege level" > > + default RISCV_SBI > > + > > +config RISCV_SBI > > + bool "S-mode (supervisor mode), use SBI calls" > > + > > +config RISCV_M_MODE > > + bool "M-mode (machine mode)" > > + > > +endchoice > = > Hmm. I am wondering if we shouldn't just make both selectable > at the same time and fix code to call a function that determines > mode dynamically? e.g. > = > enum riscv_mode { RISCV_M_MODE =3D 1, RISCV_S_MODE =3D 2 }; > = > static inline enum riscv_mode riscv_get_mode(void) > { > if (IS_ENABLED(CONFIG_RISCV_M_MODE) && IS_ENABLED(CONFIG_RISCV_S_MODE)) { > /* somehow determine it dynamically */ > } > = > return IS_ENABLED(CONFIG_RISCV_M_MODE) ? RISCV_M_MODE : RISCV_S_MODE; > } > > = > I would really like to have a riscv{32,64}_defconfig that can just build = all boards > at once. Do you know if this could be dynamically determined? At the moment I have not answer. I'll try to investigate dynamic mode determination, it's very attractive id= ea. On the other hand compile time mode selection is not the show stopper for "one defconfig to build them all": we have to make STACK_SIZE and MALLOC_SI= ZE per-board parameters not per-defconfig parameters like now. If we could make STACK_SIZE and MALLOC_SIZE per-board compile-time paramete= rs then we can make RISC-V mode per-board compile-time parameter too. Is this solut= ion acceptable? > > + > > source "arch/riscv/Kconfig.socs" > > = > > config CPU_SUPPORTS_32BIT_KERNEL > > @@ -97,14 +109,4 @@ config NMON_HELP > > Say yes here to get the nmon commands message on > > every nmon start. > > = > > -# set if we run in machine mode, cleared if we run in supervisor mode > > -config RISCV_M_MODE > > - bool > > - > > -# set if we are running in S-mode and can use SBI calls > > -config RISCV_SBI > > - bool > > - depends on !RISCV_M_MODE > > - default y > > - > > endmenu > > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs > > index c6875738d0..f767942f34 100644 > > --- a/arch/riscv/Kconfig.socs > > +++ b/arch/riscv/Kconfig.socs > > @@ -3,10 +3,10 @@ menu "SoC selection" > > config SOC_ERIZO > > bool "Erizo SoC" > > depends on ARCH_RV32I > > + depends on RISCV_M_MODE > > select HAS_ASM_DEBUG_LL > > select HAS_NMON > > select USE_COMPRESSED_DTB > > - select RISCV_M_MODE > > select RISCV_TIMER > > = > > config BOARD_ERIZO_GENERIC > > @@ -15,6 +15,7 @@ config BOARD_ERIZO_GENERIC > > = > > config SOC_VIRT > > bool "QEMU Virt Machine" > > + depends on RISCV_SBI > > select BOARD_RISCV_GENERIC_DT > > select CLINT_TIMER > > help > > @@ -23,6 +24,7 @@ config SOC_VIRT > > = > > config SOC_SIFIVE > > bool "SiFive SoCs" > > + depends on RISCV_SBI > > select CLK_SIFIVE > > select CLK_SIFIVE_PRCI > > select RISCV_TIMER > > diff --git a/arch/riscv/configs/erizo_generic_defconfig b/arch/riscv/co= nfigs/erizo_generic_defconfig > > index 247a179130..16168eef66 100644 > > --- a/arch/riscv/configs/erizo_generic_defconfig > > +++ b/arch/riscv/configs/erizo_generic_defconfig > > @@ -1,3 +1,4 @@ > > +CONFIG_RISCV_M_MODE=3Dy > > CONFIG_SOC_ERIZO=3Dy > > # CONFIG_GLOBALVAR is not set > > CONFIG_STACK_SIZE=3D0x20000 > > = > = > -- = > Pengutronix e.K. | | > Steuerwalder Str. 21 | http://www.pengutronix.de/ | > 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | -- = Best regards, =A0 Antony Pavlov _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox