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[109.252.203.80]) by smtp.gmail.com with ESMTPSA id e20sm179795ljn.13.2021.08.17.03.04.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Aug 2021 03:04:48 -0700 (PDT) From: Antony Pavlov To: barebox@lists.infradead.org Date: Tue, 17 Aug 2021 13:04:28 +0300 Message-Id: <20210817100435.114756-2-antonynpavlov@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210817100435.114756-1-antonynpavlov@gmail.com> References: <20210817100435.114756-1-antonynpavlov@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210817_030451_711774_336C268C X-CRM114-Status: GOOD ( 14.82 ) X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ahmad Fatoum Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:e::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.ext.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-4.2 required=4.0 tests=AWL,BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: [PATCH 1/8] clocksource: timer-riscv: select CSR from device tree X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.ext.pengutronix.de) barebox timer-riscv driver supports one of user counters: * 'cycle', counter for RDCYCLE instruction (CSR 0xc00); * 'time', timer for RDTIME instruction (CSR 0xc01). At the moment in M-mode timer-riscv uses the 'cycle' counter, and in S-mode timer-riscv uses the 'time' timer. Alas picorv32 CPU core supports only the 'cycle' counter. VexRiscV CPU core in M-mode supports only the 'time' timer. This patch makes it possible to use the 'time' timer for VexRiscV CPU in M-mode. See also http://lists.infradead.org/pipermail/barebox/2021-May/036067.html Signed-off-by: Antony Pavlov --- arch/riscv/dts/erizo.dtsi | 2 ++ drivers/clocksource/timer-riscv.c | 24 ++++++++++++------------ 2 files changed, 14 insertions(+), 12 deletions(-) diff --git a/arch/riscv/dts/erizo.dtsi b/arch/riscv/dts/erizo.dtsi index 228711bd69..4eb92ae6f1 100644 --- a/arch/riscv/dts/erizo.dtsi +++ b/arch/riscv/dts/erizo.dtsi @@ -22,6 +22,8 @@ timebase-frequency = <24000000>; + barebox,csr-cycle; + cpu@0 { device_type = "cpu"; compatible = "cliffordwolf,picorv32", "riscv"; diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index 5a517fe6b4..96637f988a 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -12,9 +12,8 @@ #include #include #include -#include -static u64 notrace riscv_timer_get_count_sbi(void) +static u64 notrace riscv_timer_get_count_time(void) { __maybe_unused u32 hi, lo; @@ -29,7 +28,7 @@ static u64 notrace riscv_timer_get_count_sbi(void) return ((u64)hi << 32) | lo; } -static u64 notrace riscv_timer_get_count_rdcycle(void) +static u64 notrace riscv_timer_get_count_cycle(void) { __maybe_unused u32 hi, lo; @@ -44,24 +43,25 @@ static u64 notrace riscv_timer_get_count_rdcycle(void) return ((u64)hi << 32) | lo; } -static u64 notrace riscv_timer_get_count(void) -{ - if (riscv_mode() == RISCV_S_MODE) - return riscv_timer_get_count_sbi(); - else - return riscv_timer_get_count_rdcycle(); -} - static struct clocksource riscv_clocksource = { - .read = riscv_timer_get_count, .mask = CLOCKSOURCE_MASK(64), .priority = 100, }; static int riscv_timer_init(struct device_d* dev) { + struct device_node *cpu; + dev_dbg(dev, "running at %lu Hz\n", riscv_timebase); + cpu = of_find_node_by_path("/cpus"); + + if (of_property_read_bool(cpu, "barebox,csr-cycle")) { + riscv_clocksource.read = riscv_timer_get_count_cycle; + } else { + riscv_clocksource.read = riscv_timer_get_count_time; + } + riscv_clocksource.mult = clocksource_hz2mult(riscv_timebase, riscv_clocksource.shift); return init_clock(&riscv_clocksource); -- 2.32.0 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox