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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:e::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.ext.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-4.9 required=4.0 tests=AWL,BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: [PATCH v2 1/3] arm: zynqmp: add support for xilinx zcu106 board X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.ext.pengutronix.de) Add support for the Xilinx Zynq UltraScale+ MPSoC ZCU106 evaluation board. The changes are derived from the ZCU104 board support by applying s/104/106/g (more or less). Signed-off-by: Michael Riesch --- arch/arm/boards/Makefile | 1 + arch/arm/boards/xilinx-zcu106/Makefile | 3 +++ arch/arm/boards/xilinx-zcu106/board.c | 21 ++++++++++++++++ arch/arm/boards/xilinx-zcu106/lowlevel.c | 24 +++++++++++++++++++ arch/arm/boards/xilinx-zcu106/lowlevel_init.S | 12 ++++++++++ arch/arm/dts/Makefile | 1 + arch/arm/dts/zynqmp-zcu106-revA.dts | 21 ++++++++++++++++ arch/arm/mach-zynqmp/Kconfig | 6 +++++ images/Makefile.zynqmp | 4 ++++ 9 files changed, 93 insertions(+) create mode 100644 arch/arm/boards/xilinx-zcu106/Makefile create mode 100644 arch/arm/boards/xilinx-zcu106/board.c create mode 100644 arch/arm/boards/xilinx-zcu106/lowlevel.c create mode 100644 arch/arm/boards/xilinx-zcu106/lowlevel_init.S create mode 100644 arch/arm/dts/zynqmp-zcu106-revA.dts diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index 5aac64fce..22dc9fe3d 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -170,6 +170,7 @@ obj-$(CONFIG_MACH_WARP7) += element14-warp7/ obj-$(CONFIG_MACH_WEBASTO_CCBV2) += webasto-ccbv2/ obj-$(CONFIG_MACH_VF610_TWR) += freescale-vf610-twr/ obj-$(CONFIG_MACH_XILINX_ZCU104) += xilinx-zcu104/ +obj-$(CONFIG_MACH_XILINX_ZCU106) += xilinx-zcu106/ obj-$(CONFIG_MACH_ZII_COMMON) += zii-common/ obj-$(CONFIG_MACH_ZII_RDU1) += zii-imx51-rdu1/ obj-$(CONFIG_MACH_ZII_RDU2) += zii-imx6q-rdu2/ diff --git a/arch/arm/boards/xilinx-zcu106/Makefile b/arch/arm/boards/xilinx-zcu106/Makefile new file mode 100644 index 000000000..297f77d57 --- /dev/null +++ b/arch/arm/boards/xilinx-zcu106/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +obj-y += board.o +lwl-y += lowlevel.o lowlevel_init.o diff --git a/arch/arm/boards/xilinx-zcu106/board.c b/arch/arm/boards/xilinx-zcu106/board.c new file mode 100644 index 000000000..0cb5ce86e --- /dev/null +++ b/arch/arm/boards/xilinx-zcu106/board.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2021, WolfVision GmbH + * Author: Michael Riesch + * + * Based on the barebox ZCU104 board support code. + */ + +#include +#include +#include + +static int zcu106_register_update_handler(void) +{ + if (!of_machine_is_compatible("xlnx,zynqmp-zcu106")) + return 0; + + return zynqmp_bbu_register_handler("SD", "/boot/BOOT.BIN", + BBU_HANDLER_FLAG_DEFAULT); +} +device_initcall(zcu106_register_update_handler); diff --git a/arch/arm/boards/xilinx-zcu106/lowlevel.c b/arch/arm/boards/xilinx-zcu106/lowlevel.c new file mode 100644 index 000000000..ccc8d6141 --- /dev/null +++ b/arch/arm/boards/xilinx-zcu106/lowlevel.c @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021, WolfVision GmbH + * Author: Michael Riesch + * + * Based on the barebox ZCU104 board support code. + */ + +#include +#include +#include + +extern char __dtb_zynqmp_zcu106_revA_start[]; + +void zynqmp_zcu106_start(uint32_t, uint32_t, uint32_t); + +void noinline zynqmp_zcu106_start(uint32_t r0, uint32_t r1, uint32_t r2) +{ + /* Assume that the first stage boot loader configured the UART */ + putc_ll('>'); + + barebox_arm_entry(0, SZ_2G, + __dtb_zynqmp_zcu106_revA_start + global_variable_offset()); +} diff --git a/arch/arm/boards/xilinx-zcu106/lowlevel_init.S b/arch/arm/boards/xilinx-zcu106/lowlevel_init.S new file mode 100644 index 000000000..f3d55dcef --- /dev/null +++ b/arch/arm/boards/xilinx-zcu106/lowlevel_init.S @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#include +#include + +/* The DRAM is already setup */ +#define STACK_TOP 0x80000000 + +ENTRY_PROC(start_zynqmp_zcu106) + mov x0, #STACK_TOP + mov sp, x0 + b zynqmp_zcu106_start +ENTRY_PROC_END(start_zynqmp_zcu106) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ffa9fe88c..14ca6c38e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -170,6 +170,7 @@ lwl-$(CONFIG_MACH_SAMA5D27_SOM1) += at91-sama5d27_som1_ek.dtb.o lwl-$(CONFIG_MACH_SAMA5D27_GIANTBOARD) += at91-sama5d27_giantboard.dtb.o lwl-$(CONFIG_MACH_AT91SAM9X5EK) += at91sam9x5ek.dtb.o lwl-$(CONFIG_MACH_XILINX_ZCU104) += zynqmp-zcu104-revA.dtb.o +lwl-$(CONFIG_MACH_XILINX_ZCU106) += zynqmp-zcu106-revA.dtb.o lwl-$(CONFIG_MACH_ZII_IMX7D_DEV) += imx7d-zii-rpu2.dtb.o imx7d-zii-rmu2.dtb.o lwl-$(CONFIG_MACH_WAGO_PFC_AM35XX) += am35xx-pfc-750_820x.dtb.o diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts new file mode 100644 index 000000000..7c5058826 --- /dev/null +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP ZCU106 + * + * Copyright (C) 2021, WolfVision GmbH + * Author: Michael Riesch + * + * Based on the dts for the Xilinx ZynqMP ZCU104. + */ + +#include + +/ { + chosen { + environment { + compatible = "barebox,environment"; + device-path = &sdhci1, "partname:0"; + file-path = "barebox.env"; + }; + }; +}; diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig index c9dc71c9e..78cb90165 100644 --- a/arch/arm/mach-zynqmp/Kconfig +++ b/arch/arm/mach-zynqmp/Kconfig @@ -7,4 +7,10 @@ config MACH_XILINX_ZCU104 Say Y here if you are using the Xilinx Zynq UltraScale+ MPSoC ZCU104 evaluation board. +config MACH_XILINX_ZCU106 + bool "Xilinx Zynq UltraScale+ MPSoC ZCU106" + help + Say Y here if you are using the Xilinx Zynq UltraScale+ MPSoC ZCU106 + evaluation board. + endif diff --git a/images/Makefile.zynqmp b/images/Makefile.zynqmp index da3e90b84..872f39988 100644 --- a/images/Makefile.zynqmp +++ b/images/Makefile.zynqmp @@ -6,3 +6,7 @@ pblb-$(CONFIG_MACH_XILINX_ZCU104) += start_zynqmp_zcu104 FILE_barebox-zynqmp-zcu104.img = start_zynqmp_zcu104.pblb image-$(CONFIG_MACH_XILINX_ZCU104) += barebox-zynqmp-zcu104.img + +pblb-$(CONFIG_MACH_XILINX_ZCU106) += start_zynqmp_zcu106 +FILE_barebox-zynqmp-zcu106.img = start_zynqmp_zcu106.pblb +image-$(CONFIG_MACH_XILINX_ZCU106) += barebox-zynqmp-zcu106.img -- 2.17.1 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox