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SFV:NSPM; SKIP:0; X-MS-Exchange-CrossPremises-SCL: 1 X-MS-Exchange-CrossPremises-Processed-By-Journaling: Journal Agent X-OrganizationHeadersPreserved: HE1P192MB0058.EURP192.PROD.OUTLOOK.COM X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211101_051138_520616_D8060681 X-CRM114-Status: GOOD ( 22.18 ) X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:e::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.ext.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-5.3 required=4.0 tests=AWL,BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: [PATCH v3] Fix problem with imx_ddrc_sdram_size calc X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.ext.pengutronix.de) There was some issues with the imx_ddrc_sdram_size calculation. If we compare the imx8mn DDR4 evk against the LPDDR4 variant in code and in the datasheets, we see the following: DDR4 LPDDR4 ======================== Bus width 16 16 Rank 1 1 Ranks 1 1 Banks 4 8 Banks grps 2 1 Rows 17 15 Col 10 10 This gives us the following problems: 1. Bus width problem. Does not support 16 bit SDRAM bus mode, only 32 bit supported 2. Row size problem. Only up to 16 bit row size support. 3. Bank groups support. Only support of 1 bank group. 4. Bit count problem. The imx_ddrc_count_bits function does not do a correct count. The fact that the code only handled a 32 bit bus width, compensated the problems with rows, banks and rank. 1. Bus width problem: ===================== The imx8mn has a 16-bit SDRAM bus width access but the calculation of the memory size treat it as a 32-bit width bus which makes the memory calculation to be wrong (meminfo wrong and memtest fails). There is a difference between the imx7 and the imx8 familys. The imx8 family has a device config field in the master register of the DDRC controller which the imx7 family doesn't have (the bus width is 32-bit as default). The device config field together with the DQ configuration tells us the actual bus width of the device for a correct mem size calculaton. >>From the imx8mn reference manual: +----------------------------------------------------+ | Field | Function | |----------------------------------------------------| | 31-30 | Indicates the configuration of the | | | device used in the system. | | device_config | 00b - x4 device | | | 01b - x8 device | | | 10b - x16 device | | | 11b - x32 device | +----------------------------------------------------+ ... ... The imx8 supports a bus width of 4 bits or x4 (device_config b00). This is a problem for the calculation of the mem size when it only handle the bus width in bytes. Therefore we must treat the mem size calculation for the half bus width (width = 0) in a special way. Do the calculation with one byte width and then divide the mem size by 2 later on. 2. Row size problem: ==================== The current row calculation in imx_ddrc_sdram_size does only handle 16 bit row size, the row size of the imx8mn DDR4 need 17 bits. We need to add DDRC_ADDRMAP7_ROW_B16 and DDRC_ADDRMAP7_ROW_B17 in the row check table to support a 18 bit row size. i.e. ... #define DDRC_ADDRMAP7_ROW_B17 GENMASK(11, 8) #define DDRC_ADDRMAP7_ROW_B16 GENMASK(3, 0) ... ... const u8 row_b[] = { FIELD_GET(DDRC_ADDRMAP7_ROW_B17, addrmap[7]), FIELD_GET(DDRC_ADDRMAP7_ROW_B16, addrmap[7]), FIELD_GET(DDRC_ADDRMAP6_ROW_B15, addrmap[6]), FIELD_GET(DDRC_ADDRMAP6_ROW_B14, addrmap[6]), ... ... 3. Bank groups support: ======================= Add bank group size to handle mem chip with two or more bank groups in one chip. The imx8mn DDR4 has one mem chip with ranks set to 1 and the number of banks is 4 in 2 groups, total of 8 banks. We need two add the DDRC_ADDRMAP8 and do a check DDRC_ADDRMAP8_BG_B0 and DDRC_ADDRMAP8_BG_B1 to get the number of bank groups in the chip. i.e. ... #define DDRC_ADDRMAP8_BG_B1 GENMASK(13, 8) #define DDRC_ADDRMAP8_BG_B0 GENMASK(4, 0) ... ... if (addrmap[8]) { if (FIELD_GET(DDRC_ADDRMAP8_BG_B0, addrmap[8]) != 0b11111) banks++; if (FIELD_GET(DDRC_ADDRMAP8_BG_B1, addrmap[8]) != 0b111111) banks++; } ... ... 4. Bit count problem: ===================== Also adjusted the imx_ddrc_count_bits which currently did a wrong bit check (stopped after the first check). Tested on a IMX8MN Evk with 2GB DDR4 and on a IMX8MN custom board with 512MB LPDDR4, checked size and made memory test. Signed-off-by: Joacim Zetterling --- arch/arm/mach-imx/esdctl.c | 63 +++++++++++++++++++++++++------------- 1 file changed, 42 insertions(+), 21 deletions(-) diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c index e56da3cb76d4..39b98655668b 100644 --- a/arch/arm/mach-imx/esdctl.c +++ b/arch/arm/mach-imx/esdctl.c @@ -320,6 +320,7 @@ static int vf610_ddrmc_add_mem(void *mmdcbase, struct imx_esdctl_data *data) #define DDRC_MSTR_LPDDR4 BIT(5) #define DDRC_MSTR_DATA_BUS_WIDTH GENMASK(13, 12) #define DDRC_MSTR_ACTIVE_RANKS GENMASK(27, 24) +#define DDRC_MSTR_DEVICE_CONFIG GENMASK(31, 30) #define DDRC_ADDRMAP0_CS_BIT1 GENMASK(12, 8) @@ -346,13 +347,19 @@ static int vf610_ddrmc_add_mem(void *mmdcbase, struct imx_esdctl_data *data) #define DDRC_ADDRMAP7_ROW_B17 GENMASK(11, 8) #define DDRC_ADDRMAP7_ROW_B16 GENMASK( 3, 0) +#define DDRC_ADDRMAP8_BG_B1 GENMASK(13, 8) +#define DDRC_ADDRMAP8_BG_B0 GENMASK(4, 0) + static unsigned int imx_ddrc_count_bits(unsigned int bits, const u8 config[], unsigned int config_num) { unsigned int i; - for (i = 0; i < config_num && config[i] == 0b1111; i++) - bits--; + + for (i = 0; i < config_num; i++) { + if (config[i] == 0b1111) + bits--; + } return bits; } @@ -361,7 +368,7 @@ static resource_size_t imx_ddrc_sdram_size(void __iomem *ddrc, const u32 addrmap[], u8 col_max, const u8 col_b[], unsigned int col_b_num, u8 row_max, const u8 row_b[], unsigned int row_b_num, - bool reduced_adress_space) + bool reduced_adress_space, bool is_imx8) { const u32 mstr = readl(ddrc + DDRC_MSTR); unsigned int banks, ranks, columns, rows, active_ranks, width; @@ -384,15 +391,20 @@ imx_ddrc_sdram_size(void __iomem *ddrc, const u32 addrmap[], BUG(); } + /* Bus width in bytes, 0 means half byte or 4-bit mode */ + if (is_imx8) + width = (1 << FIELD_GET(DDRC_MSTR_DEVICE_CONFIG, mstr)) >> 1; + else + width = 4; + switch (FIELD_GET(DDRC_MSTR_DATA_BUS_WIDTH, mstr)) { case 0b00: /* Full DQ bus */ - width = 4; break; - case 0b01: /* Half DQ bus */ - width = 2; + case 0b01: /* Half DQ bus */ + width >>= 1; break; case 0b10: /* Quarter DQ bus */ - width = 1; + width >>= 2; break; default: BUG(); @@ -409,10 +421,25 @@ imx_ddrc_sdram_size(void __iomem *ddrc, const u32 addrmap[], if (FIELD_GET(DDRC_ADDRMAP1_BANK_B2, addrmap[1]) != 0b11111) banks++; + if (addrmap[8]) { + if (FIELD_GET(DDRC_ADDRMAP8_BG_B0, addrmap[8]) != 0b11111) + banks++; + if (FIELD_GET(DDRC_ADDRMAP8_BG_B1, addrmap[8]) != 0b111111) + banks++; + } + columns = imx_ddrc_count_bits(col_max, col_b, col_b_num); rows = imx_ddrc_count_bits(row_max, row_b, row_b_num); - size = memory_sdram_size(columns, rows, 1 << banks, width) << ranks; + /* + * Special case when bus width is 0 or x4 mode, + * calculate the mem size and then divide the size by 2. + */ + if (width) + size = memory_sdram_size(columns, rows, 1 << banks, width); + else + size = memory_sdram_size(columns, rows, 1 << banks, 1) >> 1; + size <<= ranks; return reduced_adress_space ? size * 3 / 4 : size; } @@ -427,7 +454,8 @@ static resource_size_t imx8m_ddrc_sdram_size(void __iomem *ddrc) readl(ddrc + DDRC_ADDRMAP(4)), readl(ddrc + DDRC_ADDRMAP(5)), readl(ddrc + DDRC_ADDRMAP(6)), - readl(ddrc + DDRC_ADDRMAP(7)) + readl(ddrc + DDRC_ADDRMAP(7)), + readl(ddrc + DDRC_ADDRMAP(8)) }; const u8 col_b[] = { /* @@ -445,15 +473,8 @@ static resource_size_t imx8m_ddrc_sdram_size(void __iomem *ddrc) FIELD_GET(DDRC_ADDRMAP2_COL_B4, addrmap[2]), }; const u8 row_b[] = { - /* - * FIXME: RM mentions the following fields as being - * present, but looking at the code generated by DDR - * tool it doesn't look like those registers are - * really implemented/used. - * - * FIELD_GET(DDRC_ADDRMAP7_ROW_B17, addrmap[7]), - * FIELD_GET(DDRC_ADDRMAP7_ROW_B16, addrmap[7]), - */ + FIELD_GET(DDRC_ADDRMAP7_ROW_B17, addrmap[7]), + FIELD_GET(DDRC_ADDRMAP7_ROW_B16, addrmap[7]), FIELD_GET(DDRC_ADDRMAP6_ROW_B15, addrmap[6]), FIELD_GET(DDRC_ADDRMAP6_ROW_B14, addrmap[6]), FIELD_GET(DDRC_ADDRMAP6_ROW_B13, addrmap[6]), @@ -465,8 +486,8 @@ static resource_size_t imx8m_ddrc_sdram_size(void __iomem *ddrc) return imx_ddrc_sdram_size(ddrc, addrmap, 12, ARRAY_AND_SIZE(col_b), - 16, ARRAY_AND_SIZE(row_b), - reduced_adress_space); + 18, ARRAY_AND_SIZE(row_b), + reduced_adress_space, true); } static int imx8m_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data) @@ -508,7 +529,7 @@ static resource_size_t imx7d_ddrc_sdram_size(void __iomem *ddrc) return imx_ddrc_sdram_size(ddrc, addrmap, 11, ARRAY_AND_SIZE(col_b), 15, ARRAY_AND_SIZE(row_b), - reduced_adress_space); + reduced_adress_space, false); } static int imx7d_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data) -- 2.25.1 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox