* [PATCH v1 1/2] serial: amba-pl011: reset controller on pl011_setbaudrate()
@ 2022-01-14 8:21 Oleksij Rempel
2022-01-14 8:21 ` [PATCH v1 2/2] ARM: rpi: set uart0-pl0110 clk to 48MHz Oleksij Rempel
0 siblings, 1 reply; 6+ messages in thread
From: Oleksij Rempel @ 2022-01-14 8:21 UTC (permalink / raw)
To: barebox; +Cc: Oleksij Rempel
Reset UART controller on baudrate update. Otherwise, at least on some
systems (for example RPi2), new baudrate setting will not be updated
and system will continue to use previous settings.
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
---
drivers/serial/amba-pl011.c | 41 ++++++++++++++++++++++---------------
1 file changed, 24 insertions(+), 17 deletions(-)
diff --git a/drivers/serial/amba-pl011.c b/drivers/serial/amba-pl011.c
index 3baadd54e7..345c58e274 100644
--- a/drivers/serial/amba-pl011.c
+++ b/drivers/serial/amba-pl011.c
@@ -54,6 +54,23 @@ to_amba_uart_port(struct console_device *uart)
return container_of(uart, struct amba_uart_port, uart);
}
+static void pl011_rlcr(struct amba_uart_port *uart, u32 lcr)
+{
+ struct vendor_data *vendor = uart->vendor;
+
+ writew(lcr, uart->base + vendor->lcrh_rx);
+ if (vendor->lcrh_tx != vendor->lcrh_rx) {
+ int i;
+ /*
+ * Wait 10 PCLKs before writing LCRH_TX register,
+ * to get this delay write read only register 10 times
+ */
+ for (i = 0; i < 10; ++i)
+ writew(0xff, uart->base + UART011_MIS);
+ writew(lcr, uart->base + vendor->lcrh_tx);
+ }
+}
+
static int pl011_setbaudrate(struct console_device *cdev, int baudrate)
{
struct amba_uart_port *uart = to_amba_uart_port(cdev);
@@ -61,6 +78,7 @@ static int pl011_setbaudrate(struct console_device *cdev, int baudrate)
unsigned int divider;
unsigned int remainder;
unsigned int fraction;
+ uint32_t cr;
/*
** Set baud rate
@@ -74,9 +92,15 @@ static int pl011_setbaudrate(struct console_device *cdev, int baudrate)
temp = (8 * remainder) / baudrate;
fraction = (temp >> 1) + (temp & 1);
+ cr = readl(uart->base + UART011_CR);
+ writel(0x0, uart->base + UART011_CR);
+
writel(divider, uart->base + UART011_IBRD);
writel(fraction, uart->base + UART011_FBRD);
+ pl011_rlcr(uart, UART01x_LCRH_WLEN_8 | UART01x_LCRH_FEN);
+ writel(cr, uart->base + UART011_CR);
+
return 0;
}
@@ -118,23 +142,6 @@ static int pl011_tstc(struct console_device *cdev)
return !(readl(uart->base + UART01x_FR) & UART01x_FR_RXFE);
}
-static void pl011_rlcr(struct amba_uart_port *uart, u32 lcr)
-{
- struct vendor_data *vendor = uart->vendor;
-
- writew(lcr, uart->base + vendor->lcrh_rx);
- if (vendor->lcrh_tx != vendor->lcrh_rx) {
- int i;
- /*
- * Wait 10 PCLKs before writing LCRH_TX register,
- * to get this delay write read only register 10 times
- */
- for (i = 0; i < 10; ++i)
- writew(0xff, uart->base + UART011_MIS);
- writew(lcr, uart->base + vendor->lcrh_tx);
- }
-}
-
static int pl011_init_port(struct console_device *cdev)
{
struct amba_uart_port *uart = to_amba_uart_port(cdev);
--
2.30.2
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^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH v1 2/2] ARM: rpi: set uart0-pl0110 clk to 48MHz
2022-01-14 8:21 [PATCH v1 1/2] serial: amba-pl011: reset controller on pl011_setbaudrate() Oleksij Rempel
@ 2022-01-14 8:21 ` Oleksij Rempel
2022-01-14 8:30 ` Sascha Hauer
0 siblings, 1 reply; 6+ messages in thread
From: Oleksij Rempel @ 2022-01-14 8:21 UTC (permalink / raw)
To: barebox; +Cc: Oleksij Rempel
At least on RPi2 this clock is 48MHz. This issue was not visible,
becouse amba-pl011 driver was not reseting UART controller after
changing baudrate. So, clk settings was not updated for some time.
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
---
arch/arm/boards/raspberry-pi/rpi-common.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boards/raspberry-pi/rpi-common.c b/arch/arm/boards/raspberry-pi/rpi-common.c
index 6c5df6fd69..2684bd5ed7 100644
--- a/arch/arm/boards/raspberry-pi/rpi-common.c
+++ b/arch/arm/boards/raspberry-pi/rpi-common.c
@@ -374,7 +374,7 @@ static int rpi_console_clock_init(void)
clk = clk_fixed("apb_pclk", 0);
clk_register_clkdev(clk, "apb_pclk", NULL);
- clk = clk_fixed("uart0-pl0110", 3 * 1000 * 1000);
+ clk = clk_fixed("uart0-pl0110", 48 * 1000 * 1000);
clk_register_clkdev(clk, NULL, "uart0-pl0110");
clkdev_add_physbase(clk, BCM2835_PL011_BASE, NULL);
clkdev_add_physbase(clk, BCM2836_PL011_BASE, NULL);
--
2.30.2
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^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH v1 2/2] ARM: rpi: set uart0-pl0110 clk to 48MHz
2022-01-14 8:21 ` [PATCH v1 2/2] ARM: rpi: set uart0-pl0110 clk to 48MHz Oleksij Rempel
@ 2022-01-14 8:30 ` Sascha Hauer
2022-01-14 10:12 ` Oleksij Rempel
0 siblings, 1 reply; 6+ messages in thread
From: Sascha Hauer @ 2022-01-14 8:30 UTC (permalink / raw)
To: Oleksij Rempel; +Cc: barebox
On Fri, Jan 14, 2022 at 09:21:41AM +0100, Oleksij Rempel wrote:
> At least on RPi2 this clock is 48MHz. This issue was not visible,
> becouse amba-pl011 driver was not reseting UART controller after
> changing baudrate. So, clk settings was not updated for some time.
We have an rpi3 and rpi4 in our lab. Could you give this a test on these
boards?
Sascha
>
> Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
> ---
> arch/arm/boards/raspberry-pi/rpi-common.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boards/raspberry-pi/rpi-common.c b/arch/arm/boards/raspberry-pi/rpi-common.c
> index 6c5df6fd69..2684bd5ed7 100644
> --- a/arch/arm/boards/raspberry-pi/rpi-common.c
> +++ b/arch/arm/boards/raspberry-pi/rpi-common.c
> @@ -374,7 +374,7 @@ static int rpi_console_clock_init(void)
> clk = clk_fixed("apb_pclk", 0);
> clk_register_clkdev(clk, "apb_pclk", NULL);
>
> - clk = clk_fixed("uart0-pl0110", 3 * 1000 * 1000);
> + clk = clk_fixed("uart0-pl0110", 48 * 1000 * 1000);
> clk_register_clkdev(clk, NULL, "uart0-pl0110");
> clkdev_add_physbase(clk, BCM2835_PL011_BASE, NULL);
> clkdev_add_physbase(clk, BCM2836_PL011_BASE, NULL);
> --
> 2.30.2
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
>
--
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Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH v1 2/2] ARM: rpi: set uart0-pl0110 clk to 48MHz
2022-01-14 8:30 ` Sascha Hauer
@ 2022-01-14 10:12 ` Oleksij Rempel
2022-01-14 10:17 ` Ahmad Fatoum
2022-01-14 10:39 ` Sascha Hauer
0 siblings, 2 replies; 6+ messages in thread
From: Oleksij Rempel @ 2022-01-14 10:12 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
On Fri, Jan 14, 2022 at 09:30:18AM +0100, Sascha Hauer wrote:
> On Fri, Jan 14, 2022 at 09:21:41AM +0100, Oleksij Rempel wrote:
> > At least on RPi2 this clock is 48MHz. This issue was not visible,
> > becouse amba-pl011 driver was not reseting UART controller after
> > changing baudrate. So, clk settings was not updated for some time.
>
> We have an rpi3 and rpi4 in our lab. Could you give this a test on these
> boards?
Yes, rpi3 is tested and rpi4 is currently not supported.
> Sascha
>
> >
> > Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
> > ---
> > arch/arm/boards/raspberry-pi/rpi-common.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/boards/raspberry-pi/rpi-common.c b/arch/arm/boards/raspberry-pi/rpi-common.c
> > index 6c5df6fd69..2684bd5ed7 100644
> > --- a/arch/arm/boards/raspberry-pi/rpi-common.c
> > +++ b/arch/arm/boards/raspberry-pi/rpi-common.c
> > @@ -374,7 +374,7 @@ static int rpi_console_clock_init(void)
> > clk = clk_fixed("apb_pclk", 0);
> > clk_register_clkdev(clk, "apb_pclk", NULL);
> >
> > - clk = clk_fixed("uart0-pl0110", 3 * 1000 * 1000);
> > + clk = clk_fixed("uart0-pl0110", 48 * 1000 * 1000);
> > clk_register_clkdev(clk, NULL, "uart0-pl0110");
> > clkdev_add_physbase(clk, BCM2835_PL011_BASE, NULL);
> > clkdev_add_physbase(clk, BCM2836_PL011_BASE, NULL);
> > --
> > 2.30.2
> >
> >
> > _______________________________________________
> > barebox mailing list
> > barebox@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/barebox
> >
>
> --
> Pengutronix e.K. | |
> Steuerwalder Str. 21 | http://www.pengutronix.de/ |
> 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH v1 2/2] ARM: rpi: set uart0-pl0110 clk to 48MHz
2022-01-14 10:12 ` Oleksij Rempel
@ 2022-01-14 10:17 ` Ahmad Fatoum
2022-01-14 10:39 ` Sascha Hauer
1 sibling, 0 replies; 6+ messages in thread
From: Ahmad Fatoum @ 2022-01-14 10:17 UTC (permalink / raw)
To: Oleksij Rempel, Sascha Hauer; +Cc: barebox, Uwe Kleine-Koenig
On 14.01.22 11:12, Oleksij Rempel wrote:
> On Fri, Jan 14, 2022 at 09:30:18AM +0100, Sascha Hauer wrote:
>> On Fri, Jan 14, 2022 at 09:21:41AM +0100, Oleksij Rempel wrote:
>>> At least on RPi2 this clock is 48MHz. This issue was not visible,
>>> becouse amba-pl011 driver was not reseting UART controller after
>>> changing baudrate. So, clk settings was not updated for some time.
>>
>> We have an rpi3 and rpi4 in our lab. Could you give this a test on these
>> boards?
>
> Yes, rpi3 is tested and rpi4 is currently not supported.
Uwe's finger is surely hovering over the send button right now ;)
>
>> Sascha
>>
>>>
>>> Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
>>> ---
>>> arch/arm/boards/raspberry-pi/rpi-common.c | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm/boards/raspberry-pi/rpi-common.c b/arch/arm/boards/raspberry-pi/rpi-common.c
>>> index 6c5df6fd69..2684bd5ed7 100644
>>> --- a/arch/arm/boards/raspberry-pi/rpi-common.c
>>> +++ b/arch/arm/boards/raspberry-pi/rpi-common.c
>>> @@ -374,7 +374,7 @@ static int rpi_console_clock_init(void)
>>> clk = clk_fixed("apb_pclk", 0);
>>> clk_register_clkdev(clk, "apb_pclk", NULL);
>>>
>>> - clk = clk_fixed("uart0-pl0110", 3 * 1000 * 1000);
>>> + clk = clk_fixed("uart0-pl0110", 48 * 1000 * 1000);
>>> clk_register_clkdev(clk, NULL, "uart0-pl0110");
>>> clkdev_add_physbase(clk, BCM2835_PL011_BASE, NULL);
>>> clkdev_add_physbase(clk, BCM2836_PL011_BASE, NULL);
>>> --
>>> 2.30.2
>>>
>>>
>>> _______________________________________________
>>> barebox mailing list
>>> barebox@lists.infradead.org
>>> http://lists.infradead.org/mailman/listinfo/barebox
>>>
>>
>> --
>> Pengutronix e.K. | |
>> Steuerwalder Str. 21 | http://www.pengutronix.de/ |
>> 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
>> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
>>
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH v1 2/2] ARM: rpi: set uart0-pl0110 clk to 48MHz
2022-01-14 10:12 ` Oleksij Rempel
2022-01-14 10:17 ` Ahmad Fatoum
@ 2022-01-14 10:39 ` Sascha Hauer
1 sibling, 0 replies; 6+ messages in thread
From: Sascha Hauer @ 2022-01-14 10:39 UTC (permalink / raw)
To: Oleksij Rempel; +Cc: barebox
On Fri, Jan 14, 2022 at 11:12:46AM +0100, Oleksij Rempel wrote:
> On Fri, Jan 14, 2022 at 09:30:18AM +0100, Sascha Hauer wrote:
> > On Fri, Jan 14, 2022 at 09:21:41AM +0100, Oleksij Rempel wrote:
> > > At least on RPi2 this clock is 48MHz. This issue was not visible,
> > > becouse amba-pl011 driver was not reseting UART controller after
> > > changing baudrate. So, clk settings was not updated for some time.
> >
> > We have an rpi3 and rpi4 in our lab. Could you give this a test on these
> > boards?
>
> Yes, rpi3 is tested and rpi4 is currently not supported.
Fine. Ok then, applied, thanks
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 6+ messages in thread
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2022-01-14 8:21 [PATCH v1 1/2] serial: amba-pl011: reset controller on pl011_setbaudrate() Oleksij Rempel
2022-01-14 8:21 ` [PATCH v1 2/2] ARM: rpi: set uart0-pl0110 clk to 48MHz Oleksij Rempel
2022-01-14 8:30 ` Sascha Hauer
2022-01-14 10:12 ` Oleksij Rempel
2022-01-14 10:17 ` Ahmad Fatoum
2022-01-14 10:39 ` Sascha Hauer
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