* [PATCH 1/2] ARM: i.MX: factor out AIPS configuration into helper function
@ 2022-03-03 14:42 Ahmad Fatoum
2022-03-03 14:42 ` [PATCH RFT 2/2] ARM: i.MX6: configure AIPS3 for i.MX6ULL/i.MX6SX Ahmad Fatoum
2022-03-04 14:29 ` [PATCH 1/2] ARM: i.MX: factor out AIPS configuration into helper function Sascha Hauer
0 siblings, 2 replies; 3+ messages in thread
From: Ahmad Fatoum @ 2022-03-03 14:42 UTC (permalink / raw)
To: barebox; +Cc: Christian Melki, Ahmad Fatoum
We have the exact same sequence twice for each AIPS and i.MX6ULL/SX add
another AIPS, so it's time to factor this out into a dedicated helper
function and comment it a bit more.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
arch/arm/mach-imx/imx6.c | 44 +++++++++++++++++++++-------------------
1 file changed, 23 insertions(+), 21 deletions(-)
diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index 3ee42fd966dd..256288b25a88 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -31,10 +31,29 @@
#define MX6_OCOTP_CFG0 0x410
#define MX6_OCOTP_CFG1 0x420
+static void imx6_configure_aips(void __iomem *aips)
+{
+ /*
+ * Set all MPROTx to be non-bufferable, trusted for R/W,
+ * not forced to user-mode.
+ */
+ writel(0x77777777, aips);
+ writel(0x77777777, aips + 0x4);
+
+ /*
+ * Set all OPACRx to be non-bufferable, not require
+ * supervisor privilege level for access,allow for
+ * write access and untrusted master access.
+ */
+ writel(0, aips + 0x40);
+ writel(0, aips + 0x44);
+ writel(0, aips + 0x48);
+ writel(0, aips + 0x4c);
+ writel(0, aips + 0x50);
+}
+
static void imx6_init_lowlevel(void)
{
- void __iomem *aips1 = (void *)MX6_AIPS1_ON_BASE_ADDR;
- void __iomem *aips2 = (void *)MX6_AIPS2_ON_BASE_ADDR;
bool is_imx6q = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6Q;
bool is_imx6d = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6D;
uint32_t val_480;
@@ -51,25 +70,8 @@ static void imx6_init_lowlevel(void)
if ((readl(MXC_CCM_CCGR6) & 0x3))
imx_reset_otg_controller(IOMEM(MX6_OTG_BASE_ADDR));
- /*
- * Set all MPROTx to be non-bufferable, trusted for R/W,
- * not forced to user-mode.
- */
- writel(0x77777777, aips1);
- writel(0x77777777, aips1 + 0x4);
- writel(0, aips1 + 0x40);
- writel(0, aips1 + 0x44);
- writel(0, aips1 + 0x48);
- writel(0, aips1 + 0x4c);
- writel(0, aips1 + 0x50);
-
- writel(0x77777777, aips2);
- writel(0x77777777, aips2 + 0x4);
- writel(0, aips2 + 0x40);
- writel(0, aips2 + 0x44);
- writel(0, aips2 + 0x48);
- writel(0, aips2 + 0x4c);
- writel(0, aips2 + 0x50);
+ imx6_configure_aips(IOMEM(MX6_AIPS1_ON_BASE_ADDR));
+ imx6_configure_aips(IOMEM(MX6_AIPS2_ON_BASE_ADDR));
/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
* to make sure PFD is working right, otherwise, PFDs may
--
2.30.2
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^ permalink raw reply [flat|nested] 3+ messages in thread* [PATCH RFT 2/2] ARM: i.MX6: configure AIPS3 for i.MX6ULL/i.MX6SX
2022-03-03 14:42 [PATCH 1/2] ARM: i.MX: factor out AIPS configuration into helper function Ahmad Fatoum
@ 2022-03-03 14:42 ` Ahmad Fatoum
2022-03-04 14:29 ` [PATCH 1/2] ARM: i.MX: factor out AIPS configuration into helper function Sascha Hauer
1 sibling, 0 replies; 3+ messages in thread
From: Ahmad Fatoum @ 2022-03-03 14:42 UTC (permalink / raw)
To: barebox; +Cc: Christian Melki, Ahmad Fatoum
UltraLiteLite and SoloX both have an AIPS3, which has e.g. RNGB on it.
COnfigure that likewise to AIPS1 and AIPS2.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
Untested on actual HW.
---
arch/arm/mach-imx/imx6.c | 5 +++++
arch/arm/mach-imx/include/mach/imx6-regs.h | 10 ++++++++++
2 files changed, 15 insertions(+)
diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index 256288b25a88..7bd29446e927 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -56,6 +56,9 @@ static void imx6_init_lowlevel(void)
{
bool is_imx6q = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6Q;
bool is_imx6d = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6D;
+ bool is_imx6ull = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6ULL;
+ bool is_imx6sx = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6SX;
+
uint32_t val_480;
uint32_t val_528;
uint32_t periph_sel_1;
@@ -72,6 +75,8 @@ static void imx6_init_lowlevel(void)
imx6_configure_aips(IOMEM(MX6_AIPS1_ON_BASE_ADDR));
imx6_configure_aips(IOMEM(MX6_AIPS2_ON_BASE_ADDR));
+ if (is_imx6ull || is_imx6sx)
+ imx6_configure_aips(IOMEM(MX6_AIPS3_ON_BASE_ADDR));
/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
* to make sure PFD is working right, otherwise, PFDs may
diff --git a/arch/arm/mach-imx/include/mach/imx6-regs.h b/arch/arm/mach-imx/include/mach/imx6-regs.h
index b2753b0fa7dd..35f03036cb5b 100644
--- a/arch/arm/mach-imx/include/mach/imx6-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx6-regs.h
@@ -11,9 +11,13 @@
#define MX6_AIPS1_ARB_BASE_ADDR 0x02000000
#define MX6_AIPS2_ARB_BASE_ADDR 0x02100000
+#define MX6_AIPS3_ARB_BASE_ADDR 0x02200000
+#define MX6_AIPS3_ARB_END_ADDR 0x022FFFFF
+
/* Defines for Blocks connected via AIPS (SkyBlue) */
#define MX6_ATZ1_BASE_ADDR MX6_AIPS1_ARB_BASE_ADDR
#define MX6_ATZ2_BASE_ADDR MX6_AIPS2_ARB_BASE_ADDR
+#define MX6_ATZ3_BASE_ADDR MX6_AIPS3_ARB_BASE_ADDR
/* slots 0,7 of SDMA reserved, therefore left unused in IPMUX3 */
#define MX6_SPDIF_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x04000)
@@ -81,6 +85,12 @@
#define MX6_CAAM_BASE_ADDR (MX6_ATZ2_BASE_ADDR)
#define MX6_ARM_BASE_ADDR (MX6_ATZ2_BASE_ADDR + 0x40000)
+/* ATZ#3- On Platform */
+#define MX6_AIPS3_ON_BASE_ADDR (MX6_ATZ3_BASE_ADDR + 0x7C000)
+
+/* ATZ#2- Off Platform */
+#define MX6_AIPS3_OFF_BASE_ADDR (MX6_ATZ3_BASE_ADDR + 0x80000)
+
#define MX6_USBOH3_PL301_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x0000)
#define MX6_USBOH3_USB_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x4000)
#define MX6_OTG_BASE_ADDR MX6_USBOH3_USB_BASE_ADDR
--
2.30.2
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^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH 1/2] ARM: i.MX: factor out AIPS configuration into helper function
2022-03-03 14:42 [PATCH 1/2] ARM: i.MX: factor out AIPS configuration into helper function Ahmad Fatoum
2022-03-03 14:42 ` [PATCH RFT 2/2] ARM: i.MX6: configure AIPS3 for i.MX6ULL/i.MX6SX Ahmad Fatoum
@ 2022-03-04 14:29 ` Sascha Hauer
1 sibling, 0 replies; 3+ messages in thread
From: Sascha Hauer @ 2022-03-04 14:29 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: barebox, Christian Melki
On Thu, Mar 03, 2022 at 03:42:45PM +0100, Ahmad Fatoum wrote:
> We have the exact same sequence twice for each AIPS and i.MX6ULL/SX add
> another AIPS, so it's time to factor this out into a dedicated helper
> function and comment it a bit more.
>
> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
> arch/arm/mach-imx/imx6.c | 44 +++++++++++++++++++++-------------------
> 1 file changed, 23 insertions(+), 21 deletions(-)
Applied, thanks
Sascha
>
> diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
> index 3ee42fd966dd..256288b25a88 100644
> --- a/arch/arm/mach-imx/imx6.c
> +++ b/arch/arm/mach-imx/imx6.c
> @@ -31,10 +31,29 @@
> #define MX6_OCOTP_CFG0 0x410
> #define MX6_OCOTP_CFG1 0x420
>
> +static void imx6_configure_aips(void __iomem *aips)
> +{
> + /*
> + * Set all MPROTx to be non-bufferable, trusted for R/W,
> + * not forced to user-mode.
> + */
> + writel(0x77777777, aips);
> + writel(0x77777777, aips + 0x4);
> +
> + /*
> + * Set all OPACRx to be non-bufferable, not require
> + * supervisor privilege level for access,allow for
> + * write access and untrusted master access.
> + */
> + writel(0, aips + 0x40);
> + writel(0, aips + 0x44);
> + writel(0, aips + 0x48);
> + writel(0, aips + 0x4c);
> + writel(0, aips + 0x50);
> +}
> +
> static void imx6_init_lowlevel(void)
> {
> - void __iomem *aips1 = (void *)MX6_AIPS1_ON_BASE_ADDR;
> - void __iomem *aips2 = (void *)MX6_AIPS2_ON_BASE_ADDR;
> bool is_imx6q = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6Q;
> bool is_imx6d = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6D;
> uint32_t val_480;
> @@ -51,25 +70,8 @@ static void imx6_init_lowlevel(void)
> if ((readl(MXC_CCM_CCGR6) & 0x3))
> imx_reset_otg_controller(IOMEM(MX6_OTG_BASE_ADDR));
>
> - /*
> - * Set all MPROTx to be non-bufferable, trusted for R/W,
> - * not forced to user-mode.
> - */
> - writel(0x77777777, aips1);
> - writel(0x77777777, aips1 + 0x4);
> - writel(0, aips1 + 0x40);
> - writel(0, aips1 + 0x44);
> - writel(0, aips1 + 0x48);
> - writel(0, aips1 + 0x4c);
> - writel(0, aips1 + 0x50);
> -
> - writel(0x77777777, aips2);
> - writel(0x77777777, aips2 + 0x4);
> - writel(0, aips2 + 0x40);
> - writel(0, aips2 + 0x44);
> - writel(0, aips2 + 0x48);
> - writel(0, aips2 + 0x4c);
> - writel(0, aips2 + 0x50);
> + imx6_configure_aips(IOMEM(MX6_AIPS1_ON_BASE_ADDR));
> + imx6_configure_aips(IOMEM(MX6_AIPS2_ON_BASE_ADDR));
>
> /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
> * to make sure PFD is working right, otherwise, PFDs may
> --
> 2.30.2
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
>
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