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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:e::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.ext.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-5.3 required=4.0 tests=AWL,BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: [PATCH 1/2] phy: rockchip: align naneng-combphy clocks and resets with binding X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.ext.pengutronix.de) There was no device tree binding in mainline Linux when this driver was introduced in barebox. This has changed in the mean time, hence we need to align the clocks and resets in this driver. This step is a prerequisite for replacing the initial rk3568.dtsi in arch/arm/dts with the mainline Linux version. For compatibility, the former is updated accordingly. Signed-off-by: Michael Riesch --- arch/arm/dts/rk3568.dtsi | 10 ++++------ .../rockchip/phy-rockchip-naneng-combphy.c | 19 ++++--------------- 2 files changed, 8 insertions(+), 21 deletions(-) diff --git a/arch/arm/dts/rk3568.dtsi b/arch/arm/dts/rk3568.dtsi index 0f19d3f0c0..28121dbdf3 100644 --- a/arch/arm/dts/rk3568.dtsi +++ b/arch/arm/dts/rk3568.dtsi @@ -367,11 +367,10 @@ #phy-cells = <1>; clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>, <&cru PCLK_PIPE>; - clock-names = "refclk", "apbclk", "pipe_clk"; + clock-names = "ref", "apb", "pipe"; assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; assigned-clock-rates = <24000000>; - resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>; - reset-names = "combphy-apb", "combphy"; + resets = <&cru SRST_PIPEPHY0>; rockchip,pipe-grf = <&pipegrf>; rockchip,pipe-phy-grf = <&pipe_phy_grf0>; status = "disabled"; @@ -383,11 +382,10 @@ #phy-cells = <1>; clocks = <&pmucru CLK_PCIEPHY1_REF>, <&cru PCLK_PIPEPHY1>, <&cru PCLK_PIPE>; - clock-names = "refclk", "apbclk", "pipe_clk"; + clock-names = "ref", "apb", "pipe"; assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; assigned-clock-rates = <24000000>; - resets = <&cru SRST_P_PIPEPHY1>, <&cru SRST_PIPEPHY1>; - reset-names = "combphy-apb", "combphy"; + resets = <&cru SRST_PIPEPHY1>; rockchip,pipe-grf = <&pipegrf>; rockchip,pipe-phy-grf = <&pipe_phy_grf1>; status = "disabled"; diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index 445703ecd8..2d86d86334 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -83,7 +83,6 @@ struct rockchip_combphy_priv { struct regmap *pipe_grf; struct regmap *phy_grf; struct phy *phy; - struct reset_control *apb_rst; struct reset_control *phy_rst; const struct rockchip_combphy_cfg *cfg; }; @@ -317,17 +316,7 @@ static int rockchip_combphy_parse_dt(struct device_d *dev, param_write(priv->pipe_grf, &phy_cfg->grfcfg->pipe_sgmii_mac_sel, true); - priv->apb_rst = reset_control_get(dev, "combphy-apb"); - if (IS_ERR(priv->apb_rst)) { - ret = PTR_ERR(priv->apb_rst); - - if (ret != -EPROBE_DEFER) - dev_warn(dev, "failed to get apb reset\n"); - - return ret; - } - - priv->phy_rst = reset_control_get(dev, "combphy"); + priv->phy_rst = reset_control_get(dev, NULL); if (IS_ERR(priv->phy_rst)) { ret = PTR_ERR(priv->phy_rst); @@ -579,9 +568,9 @@ static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = { }; static const struct clk_bulk_data rk3568_clks[] = { - { .id = "refclk" }, - { .id = "apbclk" }, - { .id = "pipe_clk" }, + { .id = "ref" }, + { .id = "apb" }, + { .id = "pipe" }, }; static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = { -- 2.30.2 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox