Currently we have three different definitions for EMIF management: - Offsets - Offsets relative to the base address - Offsets in the structure The patch represents the first attempt to unify this. Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com> --- arch/arm/boards/afi-gf/lowlevel.c | 39 +++++++++--------- arch/arm/mach-omap/am33xx_generic.c | 41 +++++++++---------- .../mach-omap/include/mach/am33xx-silicon.h | 10 +---- 3 files changed, 42 insertions(+), 48 deletions(-) diff --git a/arch/arm/boards/afi-gf/lowlevel.c b/arch/arm/boards/afi-gf/lowlevel.c index de40f6c5af..88ffcfae5b 100644 --- a/arch/arm/boards/afi-gf/lowlevel.c +++ b/arch/arm/boards/afi-gf/lowlevel.c @@ -130,34 +130,35 @@ static void board_config_vtp(void) static void board_config_emif_ddr(void) { + const void __iomem *emif4 = IOMEM(AM33XX_EMIF4_BASE); u32 i; /*Program EMIF0 CFG Registers*/ - __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1)); - __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1_SHADOW)); - __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_2)); - __raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1)); - __raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1_SHADOW)); - __raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2)); - __raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2_SHADOW)); - __raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3)); - __raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3_SHADOW)); - - __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG)); - __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2)); - - __raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL)); - __raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW)); + __raw_writel(EMIF_READ_LATENCY, emif4 + EMIF4_DDR_PHY_CTRL_1); + __raw_writel(EMIF_READ_LATENCY, emif4 + EMIF4_DDR_PHY_CTRL_1_SHADOW); + __raw_writel(EMIF_READ_LATENCY, emif4 + EMIF4_DDR_PHY_CTRL_2); + __raw_writel(EMIF_TIM1, emif4 + EMIF4_SDRAM_TIM_1); + __raw_writel(EMIF_TIM1, emif4 + EMIF4_SDRAM_TIM_1_SHADOW); + __raw_writel(EMIF_TIM2, emif4 + EMIF4_SDRAM_TIM_2); + __raw_writel(EMIF_TIM2, emif4 + EMIF4_SDRAM_TIM_2_SHADOW); + __raw_writel(EMIF_TIM3, emif4 + EMIF4_SDRAM_TIM_3); + __raw_writel(EMIF_TIM3, emif4 + EMIF4_SDRAM_TIM_3_SHADOW); + + __raw_writel(EMIF_SDCFG, emif4 + EMIF4_SDRAM_CONFIG); + __raw_writel(EMIF_SDCFG, emif4 + EMIF4_SDRAM_CONFIG2); + + __raw_writel(0x00004650, emif4 + EMIF4_SDRAM_REF_CTRL); + __raw_writel(0x00004650, emif4 + EMIF4_SDRAM_REF_CTRL_SHADOW); for (i = 0; i < 5000; i++) { } - __raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL)); - __raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW)); + __raw_writel(EMIF_SDREF, emif4 + EMIF4_SDRAM_REF_CTRL); + __raw_writel(EMIF_SDREF, emif4 + EMIF4_SDRAM_REF_CTRL_SHADOW); - __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG)); - __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2)); + __raw_writel(EMIF_SDCFG, emif4 + EMIF4_SDRAM_CONFIG); + __raw_writel(EMIF_SDCFG, emif4 + EMIF4_SDRAM_CONFIG2); } static void board_config_ddr(void) diff --git a/arch/arm/mach-omap/am33xx_generic.c b/arch/arm/mach-omap/am33xx_generic.c index 3c5cdf065c..896968f2f3 100644 --- a/arch/arm/mach-omap/am33xx_generic.c +++ b/arch/arm/mach-omap/am33xx_generic.c @@ -307,18 +307,20 @@ void am33xx_ddr_phydata_cmd_macro(const struct am33xx_cmd_control *cmd_ctrl) void am33xx_config_sdram(const struct am33xx_emif_regs *regs) { - writel(regs->emif_read_latency, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1)); - writel(regs->emif_read_latency, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1_SHADOW)); - writel(regs->emif_read_latency, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_2)); - writel(regs->emif_tim1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1)); - writel(regs->emif_tim1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1_SHADOW)); - writel(regs->emif_tim2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2)); - writel(regs->emif_tim2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2_SHADOW)); - writel(regs->emif_tim3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3)); - writel(regs->emif_tim3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3_SHADOW)); + const void __iomem *emif4 = IOMEM(AM33XX_EMIF4_BASE); + + writel(regs->emif_read_latency, emif4 + EMIF4_DDR_PHY_CTRL_1); + writel(regs->emif_read_latency, emif4 + EMIF4_DDR_PHY_CTRL_1_SHADOW); + writel(regs->emif_read_latency, emif4 + EMIF4_DDR_PHY_CTRL_2); + writel(regs->emif_tim1, emif4 + EMIF4_SDRAM_TIM_1); + writel(regs->emif_tim1, emif4 + EMIF4_SDRAM_TIM_1_SHADOW); + writel(regs->emif_tim2, emif4 + EMIF4_SDRAM_TIM_2); + writel(regs->emif_tim2, emif4 + EMIF4_SDRAM_TIM_2_SHADOW); + writel(regs->emif_tim3, emif4 + EMIF4_SDRAM_TIM_3); + writel(regs->emif_tim3, emif4 + EMIF4_SDRAM_TIM_3_SHADOW); if (regs->ocp_config) - writel(regs->ocp_config, AM33XX_EMIF4_0_REG(OCP_CONFIG)); + writel(regs->ocp_config, emif4 + EMIF4_OCP_CONFIG); if (regs->zq_config) { /* @@ -326,20 +328,17 @@ void am33xx_config_sdram(const struct am33xx_emif_regs *regs) * about 570us for a delay, which will be long enough * to configure things. */ - writel(0x2800, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL)); - writel(regs->zq_config, AM33XX_EMIF4_0_REG(ZQ_CONFIG)); + writel(0x2800, emif4 + EMIF4_SDRAM_REF_CTRL); + writel(regs->zq_config, emif4 + EMIF4_ZQ_CONFIG); writel(regs->sdram_config, CM_EMIF_SDRAM_CONFIG); - writel(regs->sdram_config, AM33XX_EMIF4_0_REG(SDRAM_CONFIG)); - writel(regs->sdram_ref_ctrl, - AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL)); - writel(regs->sdram_ref_ctrl, - AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW)); - + writel(regs->sdram_config, emif4 + EMIF4_SDRAM_CONFIG); + writel(regs->sdram_ref_ctrl, emif4 + EMIF4_SDRAM_REF_CTRL); + writel(regs->sdram_ref_ctrl, emif4 + EMIF4_SDRAM_REF_CTRL_SHADOW); } - writel(regs->sdram_ref_ctrl, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL)); - writel(regs->sdram_ref_ctrl, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW)); - writel(regs->sdram_config, AM33XX_EMIF4_0_REG(SDRAM_CONFIG)); + writel(regs->sdram_ref_ctrl, emif4 + EMIF4_SDRAM_REF_CTRL); + writel(regs->sdram_ref_ctrl, emif4 + EMIF4_SDRAM_REF_CTRL_SHADOW); + writel(regs->sdram_config, emif4 + EMIF4_SDRAM_CONFIG); } /** diff --git a/arch/arm/mach-omap/include/mach/am33xx-silicon.h b/arch/arm/mach-omap/include/mach/am33xx-silicon.h index 0467dac03b..d090b0f29c 100644 --- a/arch/arm/mach-omap/include/mach/am33xx-silicon.h +++ b/arch/arm/mach-omap/include/mach/am33xx-silicon.h @@ -37,9 +37,6 @@ #define AM33XX_GPIO2_BASE (AM33XX_L4_PER_BASE + 0x1AC000 + 0x100) #define AM33XX_GPIO3_BASE (AM33XX_L4_PER_BASE + 0x1AE000 + 0x100) -/* EMFI Registers */ -#define AM33XX_EMFI0_BASE 0x4C000000 - #define AM33XX_DRAM_ADDR_SPACE_START 0x80000000 #define AM33XX_DRAM_ADDR_SPACE_END 0xC0000000 @@ -83,8 +80,8 @@ #define AM33XX_WDT_BASE 0x44E35000 /* EMIF Base address */ -#define AM33XX_EMIF4_0_CFG_BASE 0x4C000000 -#define AM33XX_EMIF4_1_CFG_BASE 0x4D000000 +#define AM33XX_EMIF4_BASE 0x4c000000 + #define AM33XX_DMM_BASE 0x4E000000 #define AM335X_CPSW_BASE 0x4A100000 @@ -97,9 +94,6 @@ #define AM33XX_DMM_LISA_MAP__3 (AM33XX_DMM_BASE + 0x4C) #define AM33XX_DMM_PAT_BASE_ADDR (AM33XX_DMM_BASE + 0x460) -#define AM33XX_EMIF4_0_REG(REGNAME) (AM33XX_EMIF4_0_CFG_BASE + EMIF4_##REGNAME) -#define AM33XX_EMIF4_1_REG(REGNAME) (AM33XX_EMIF4_1_CFG_BASE + EMIF4_##REGNAME) - #define EMIF4_MOD_ID_REV 0x0 #define EMIF4_SDRAM_STATUS 0x04 #define EMIF4_SDRAM_CONFIG 0x08 -- 2.32.0 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com> --- arch/arm/boards/afi-gf/lowlevel.c | 1 + arch/arm/mach-omap/am33xx_generic.c | 1 + .../mach-omap/include/mach/am33xx-silicon.h | 21 ------------------- arch/arm/mach-omap/include/mach/emif4.h | 21 +++++++++++++++++++ 4 files changed, 23 insertions(+), 21 deletions(-) diff --git a/arch/arm/boards/afi-gf/lowlevel.c b/arch/arm/boards/afi-gf/lowlevel.c index 88ffcfae5b..d28cc8fad3 100644 --- a/arch/arm/boards/afi-gf/lowlevel.c +++ b/arch/arm/boards/afi-gf/lowlevel.c @@ -10,6 +10,7 @@ #include <mach/am33xx-generic.h> #include <mach/am33xx-silicon.h> #include <mach/am33xx-clock.h> +#include <mach/emif4.h> #include <mach/sdrc.h> #include <mach/sys_info.h> #include <mach/syslib.h> diff --git a/arch/arm/mach-omap/am33xx_generic.c b/arch/arm/mach-omap/am33xx_generic.c index 896968f2f3..bdfa0e9e26 100644 --- a/arch/arm/mach-omap/am33xx_generic.c +++ b/arch/arm/mach-omap/am33xx_generic.c @@ -23,6 +23,7 @@ #include <asm/barebox-arm.h> #include <mach/am33xx-silicon.h> #include <mach/am33xx-clock.h> +#include <mach/emif4.h> #include <mach/generic.h> #include <mach/sys_info.h> #include <mach/am33xx-generic.h> diff --git a/arch/arm/mach-omap/include/mach/am33xx-silicon.h b/arch/arm/mach-omap/include/mach/am33xx-silicon.h index d090b0f29c..671706ff49 100644 --- a/arch/arm/mach-omap/include/mach/am33xx-silicon.h +++ b/arch/arm/mach-omap/include/mach/am33xx-silicon.h @@ -94,27 +94,6 @@ #define AM33XX_DMM_LISA_MAP__3 (AM33XX_DMM_BASE + 0x4C) #define AM33XX_DMM_PAT_BASE_ADDR (AM33XX_DMM_BASE + 0x460) -#define EMIF4_MOD_ID_REV 0x0 -#define EMIF4_SDRAM_STATUS 0x04 -#define EMIF4_SDRAM_CONFIG 0x08 -#define EMIF4_SDRAM_CONFIG2 0x0C -#define EMIF4_SDRAM_REF_CTRL 0x10 -#define EMIF4_SDRAM_REF_CTRL_SHADOW 0x14 -#define EMIF4_SDRAM_TIM_1 0x18 -#define EMIF4_SDRAM_TIM_1_SHADOW 0x1C -#define EMIF4_SDRAM_TIM_2 0x20 -#define EMIF4_SDRAM_TIM_2_SHADOW 0x24 -#define EMIF4_SDRAM_TIM_3 0x28 -#define EMIF4_SDRAM_TIM_3_SHADOW 0x2C -#define EMIF0_SDRAM_MGMT_CTRL 0x38 -#define EMIF0_SDRAM_MGMT_CTRL_SHD 0x3C -#define EMIF4_OCP_CONFIG 0x54 -#define EMIF4_ZQ_CONFIG 0xC8 -#define EMIF4_DDR_PHY_CTRL_1 0xE4 -#define EMIF4_DDR_PHY_CTRL_1_SHADOW 0xE8 -#define EMIF4_DDR_PHY_CTRL_2 0xEC -#define EMIF4_IODFT_TLGC 0x60 - #define AM33XX_VTP0_CTRL_REG 0x44E10E0C #define AM33XX_VTP1_CTRL_REG 0x48140E10 diff --git a/arch/arm/mach-omap/include/mach/emif4.h b/arch/arm/mach-omap/include/mach/emif4.h index 1f9c2938a1..559443c9a6 100644 --- a/arch/arm/mach-omap/include/mach/emif4.h +++ b/arch/arm/mach-omap/include/mach/emif4.h @@ -24,6 +24,27 @@ #ifndef _EMIF_H_ #define _EMIF_H_ +#define EMIF4_MOD_ID_REV 0x0 +#define EMIF4_STATUS 0x04 +#define EMIF4_SDRAM_CONFIG 0x08 +#define EMIF4_SDRAM_CONFIG2 0x0c +#define EMIF4_SDRAM_REF_CTRL 0x10 +#define EMIF4_SDRAM_REF_CTRL_SHADOW 0x14 +#define EMIF4_SDRAM_TIM_1 0x18 +#define EMIF4_SDRAM_TIM_1_SHADOW 0x1c +#define EMIF4_SDRAM_TIM_2 0x20 +#define EMIF4_SDRAM_TIM_2_SHADOW 0x24 +#define EMIF4_SDRAM_TIM_3 0x28 +#define EMIF4_SDRAM_TIM_3_SHADOW 0x2c +#define EMIF4_POWER_MANAGEMENT_CTRL 0x38 +#define EMIF4_POWER_MANAGEMENT_CTRL_SHADOW 0x3c +#define EMIF4_OCP_CONFIG 0x54 +#define EMIF4_ZQ_CONFIG 0xc8 +#define EMIF4_DDR_PHY_CTRL_1 0xe4 +#define EMIF4_DDR_PHY_CTRL_1_SHADOW 0xe8 +#define EMIF4_DDR_PHY_CTRL_2 0xec +#define EMIF4_IODFT_TLGC 0x60 + /* * Configuration values */ -- 2.32.0 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com> --- arch/arm/mach-omap/am35xx_emif4.c | 40 ++++++++++++------------- arch/arm/mach-omap/include/mach/emif4.h | 24 --------------- 2 files changed, 20 insertions(+), 44 deletions(-) diff --git a/arch/arm/mach-omap/am35xx_emif4.c b/arch/arm/mach-omap/am35xx_emif4.c index 678a338fd6..8780dfb539 100644 --- a/arch/arm/mach-omap/am35xx_emif4.c +++ b/arch/arm/mach-omap/am35xx_emif4.c @@ -21,58 +21,58 @@ */ void am35xx_emif4_init(void) { + const void __iomem *emif4 = IOMEM(OMAP3_SDRC_BASE); unsigned int regval; - struct emif4 *emif4_base = IOMEM(OMAP3_SDRC_BASE); /* Set the DDR PHY parameters in PHY ctrl registers */ regval = (EMIF4_DDR1_READ_LAT | EMIF4_DDR1_PWRDN_DIS | EMIF4_DDR1_EXT_STRB_DIS); - writel(regval, &emif4_base->ddr_phyctrl1); - writel(regval, &emif4_base->ddr_phyctrl1_shdw); - writel(0, &emif4_base->ddr_phyctrl2); + writel(regval, emif4 + EMIF4_DDR_PHY_CTRL_1); + writel(regval, emif4 + EMIF4_DDR_PHY_CTRL_1_SHADOW); + writel(0, emif4 + EMIF4_DDR_PHY_CTRL_2); /* Reset the DDR PHY and wait till completed */ - regval = readl(&emif4_base->sdram_iodft_tlgc); + regval = readl(emif4 + EMIF4_IODFT_TLGC); regval |= (1 << 10); - writel(regval, &emif4_base->sdram_iodft_tlgc); + writel(regval, emif4 + EMIF4_IODFT_TLGC); /* Wait till that bit clears*/ - while (readl(&emif4_base->sdram_iodft_tlgc) & (1 << 10)); + while (readl(emif4 + EMIF4_IODFT_TLGC) & (1 << 10)); /* Re-verify the DDR PHY status*/ - while ((readl(&emif4_base->sdram_sts) & (1 << 2)) == 0x0); + while ((readl(emif4 + EMIF4_STATUS) & (1 << 2)) == 0x0); regval |= (1 << 0); - writel(regval, &emif4_base->sdram_iodft_tlgc); + writel(regval, emif4 + EMIF4_IODFT_TLGC); /* Set SDR timing registers */ regval = (EMIF4_TIM1_T_WTR | EMIF4_TIM1_T_RRD | EMIF4_TIM1_T_RC | EMIF4_TIM1_T_RAS | EMIF4_TIM1_T_WR | EMIF4_TIM1_T_RCD | EMIF4_TIM1_T_RP); - writel(regval, &emif4_base->sdram_time1); - writel(regval, &emif4_base->sdram_time1_shdw); + writel(regval, emif4 + EMIF4_SDRAM_TIM_1); + writel(regval, emif4 + EMIF4_SDRAM_TIM_1_SHADOW); regval = (EMIF4_TIM2_T_CKE | EMIF4_TIM2_T_RTP | EMIF4_TIM2_T_XSRD | EMIF4_TIM2_T_XSNR | EMIF4_TIM2_T_ODT | EMIF4_TIM2_T_XP); - writel(regval, &emif4_base->sdram_time2); - writel(regval, &emif4_base->sdram_time2_shdw); + writel(regval, emif4 + EMIF4_SDRAM_TIM_2); + writel(regval, emif4 + EMIF4_SDRAM_TIM_2_SHADOW); regval = (EMIF4_TIM3_T_RAS_MAX | EMIF4_TIM3_T_RFC); - writel(regval, &emif4_base->sdram_time3); - writel(regval, &emif4_base->sdram_time3_shdw); + writel(regval, emif4 + EMIF4_SDRAM_TIM_3); + writel(regval, emif4 + EMIF4_SDRAM_TIM_3_SHADOW); /* Set the PWR control register */ regval = (EMIF4_PWR_PM_TIM | EMIF4_PWR_LP_MODE | EMIF4_PWR_DPD_DIS | EMIF4_PWR_IDLE_MODE); - writel(regval, &emif4_base->sdram_pwr_mgmt); - writel(regval, &emif4_base->sdram_pwr_mgmt_shdw); + writel(regval, emif4 + EMIF4_POWER_MANAGEMENT_CTRL); + writel(regval, emif4 + EMIF4_POWER_MANAGEMENT_CTRL_SHADOW); /* Set the DDR refresh rate control register */ regval = (EMIF4_REFRESH_RATE | EMIF4_INITREF_DIS); - writel(regval, &emif4_base->sdram_refresh_ctrl); - writel(regval, &emif4_base->sdram_refresh_ctrl_shdw); + writel(regval, emif4 + EMIF4_SDRAM_REF_CTRL); + writel(regval, emif4 + EMIF4_SDRAM_REF_CTRL_SHADOW); /* set the SDRAM configuration register */ regval = (EMIF4_CFG_PGSIZE | EMIF4_CFG_EBANK | @@ -81,5 +81,5 @@ void am35xx_emif4_init(void) EMIF4_CFG_SDR_DRV | EMIF4_CFG_DDR_DIS_DLL | EMIF4_CFG_DDR2_DDQS | EMIF4_CFG_DDR_TERM | EMIF4_CFG_IBANK_POS | EMIF4_CFG_SDRAM_TYP); - writel(regval, &emif4_base->sdram_config); + writel(regval, emif4 + EMIF4_SDRAM_CONFIG); } diff --git a/arch/arm/mach-omap/include/mach/emif4.h b/arch/arm/mach-omap/include/mach/emif4.h index 559443c9a6..06dabc5939 100644 --- a/arch/arm/mach-omap/include/mach/emif4.h +++ b/arch/arm/mach-omap/include/mach/emif4.h @@ -97,30 +97,6 @@ #define EMIF4_DDR1_PWRDN_EN (0x1 << 6) #define EMIF4_DDR1_READ_LAT (0x6 << 0) -struct emif4 { - unsigned int emif_mod_id_rev; - unsigned int sdram_sts; - unsigned int sdram_config; - unsigned int res1; - unsigned int sdram_refresh_ctrl; - unsigned int sdram_refresh_ctrl_shdw; - unsigned int sdram_time1; - unsigned int sdram_time1_shdw; - unsigned int sdram_time2; - unsigned int sdram_time2_shdw; - unsigned int sdram_time3; - unsigned int sdram_time3_shdw; - unsigned char res2[8]; - unsigned int sdram_pwr_mgmt; - unsigned int sdram_pwr_mgmt_shdw; - unsigned char res3[32]; - unsigned int sdram_iodft_tlgc; - unsigned char res4[128]; - unsigned int ddr_phyctrl1; - unsigned int ddr_phyctrl1_shdw; - unsigned int ddr_phyctrl2; -}; - void am35xx_emif4_init(void); #endif /* endif _EMIF_H_ */ -- 2.32.0 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com> --- arch/arm/mach-omap/am35xx_emif4.c | 53 ++++++++++++++++++++++++- arch/arm/mach-omap/include/mach/emif4.h | 52 ------------------------ 2 files changed, 52 insertions(+), 53 deletions(-) diff --git a/arch/arm/mach-omap/am35xx_emif4.c b/arch/arm/mach-omap/am35xx_emif4.c index 8780dfb539..bd4fbd21e3 100644 --- a/arch/arm/mach-omap/am35xx_emif4.c +++ b/arch/arm/mach-omap/am35xx_emif4.c @@ -15,7 +15,58 @@ #include <mach/omap3-silicon.h> /* - * do_pac200_emif4_init - + * AM35xx configuration values + */ +#define EMIF4_TIM1_T_RP (0x3 << 25) +#define EMIF4_TIM1_T_RCD (0x3 << 21) +#define EMIF4_TIM1_T_WR (0x3 << 17) +#define EMIF4_TIM1_T_RAS (0x7 << 12) +#define EMIF4_TIM1_T_RC (0xa << 6) +#define EMIF4_TIM1_T_RRD (0x2 << 3) +#define EMIF4_TIM1_T_WTR (0x2) + +#define EMIF4_TIM2_T_XP (0x2 << 28) +#define EMIF4_TIM2_T_ODT (0x0 << 25) +#define EMIF4_TIM2_T_XSNR (0x1c << 16) +#define EMIF4_TIM2_T_XSRD (0xc8 << 6) +#define EMIF4_TIM2_T_RTP (0x1 << 3) +#define EMIF4_TIM2_T_CKE (0x2) + +#define EMIF4_TIM3_T_RFC (0x15 << 4) +#define EMIF4_TIM3_T_RAS_MAX (0xf) + +#define EMIF4_PWR_IDLE_MODE (0x2 << 30) +#define EMIF4_PWR_DPD_DIS (0x0 << 10) +#define EMIF4_PWR_DPD_EN (0x1 << 10) +#define EMIF4_PWR_LP_MODE (0x0 << 8) +#define EMIF4_PWR_PM_TIM (0x0) + +#define EMIF4_INITREF_DIS (0x0 << 31) +#define EMIF4_REFRESH_RATE (0x257) + +#define EMIF4_CFG_SDRAM_TYP (0x2 << 29) +#define EMIF4_CFG_IBANK_POS (0x0 << 27) +#define EMIF4_CFG_DDR_TERM (0x3 << 24) +#define EMIF4_CFG_DDR2_DDQS (0x1 << 23) +#define EMIF4_CFG_DDR_DIS_DLL (0x0 << 20) +#define EMIF4_CFG_SDR_DRV (0x0 << 18) +#define EMIF4_CFG_NARROW_MD (0x0 << 14) +#define EMIF4_CFG_CL (0x5 << 10) +#define EMIF4_CFG_ROWSIZE (0x0 << 7) +#define EMIF4_CFG_IBANK (0x3 << 4) +#define EMIF4_CFG_EBANK (0x0 << 3) +#define EMIF4_CFG_PGSIZE (0x2) + +/* + * EMIF4 PHY Control 1 register configuration + */ +#define EMIF4_DDR1_EXT_STRB_EN (0x1 << 7) +#define EMIF4_DDR1_EXT_STRB_DIS (0x0 << 7) +#define EMIF4_DDR1_PWRDN_DIS (0x0 << 6) +#define EMIF4_DDR1_PWRDN_EN (0x1 << 6) +#define EMIF4_DDR1_READ_LAT (0x6 << 0) + +/* * - Init the emif4 module for DDR access * - Early init routines, called from flash or SRAM. */ diff --git a/arch/arm/mach-omap/include/mach/emif4.h b/arch/arm/mach-omap/include/mach/emif4.h index 06dabc5939..23d5c18fcf 100644 --- a/arch/arm/mach-omap/include/mach/emif4.h +++ b/arch/arm/mach-omap/include/mach/emif4.h @@ -45,58 +45,6 @@ #define EMIF4_DDR_PHY_CTRL_2 0xec #define EMIF4_IODFT_TLGC 0x60 -/* - * Configuration values - */ -#define EMIF4_TIM1_T_RP (0x3 << 25) -#define EMIF4_TIM1_T_RCD (0x3 << 21) -#define EMIF4_TIM1_T_WR (0x3 << 17) -#define EMIF4_TIM1_T_RAS (0x7 << 12) /* 8->7 */ -#define EMIF4_TIM1_T_RC (0xA << 6) -#define EMIF4_TIM1_T_RRD (0x2 << 3) -#define EMIF4_TIM1_T_WTR (0x2) - -#define EMIF4_TIM2_T_XP (0x2 << 28) -#define EMIF4_TIM2_T_ODT (0x0 << 25) /* 2? */ -#define EMIF4_TIM2_T_XSNR (0x1C << 16) -#define EMIF4_TIM2_T_XSRD (0xC8 << 6) -#define EMIF4_TIM2_T_RTP (0x1 << 3) -#define EMIF4_TIM2_T_CKE (0x2) - -#define EMIF4_TIM3_T_RFC (0x15 << 4) /* 25->15 */ -#define EMIF4_TIM3_T_RAS_MAX (0xf) /* 7->f */ - -#define EMIF4_PWR_IDLE_MODE (0x2 << 30) -#define EMIF4_PWR_DPD_DIS (0x0 << 10) -#define EMIF4_PWR_DPD_EN (0x1 << 10) -#define EMIF4_PWR_LP_MODE (0x0 << 8) -#define EMIF4_PWR_PM_TIM (0x0) - -#define EMIF4_INITREF_DIS (0x0 << 31) -#define EMIF4_REFRESH_RATE (0x257) /* 50f->257 */ - -#define EMIF4_CFG_SDRAM_TYP (0x2 << 29) -#define EMIF4_CFG_IBANK_POS (0x0 << 27) -#define EMIF4_CFG_DDR_TERM (0x3 << 24) /* --> 0x3 */ -#define EMIF4_CFG_DDR2_DDQS (0x1 << 23) -#define EMIF4_CFG_DDR_DIS_DLL (0x0 << 20) -#define EMIF4_CFG_SDR_DRV (0x0 << 18) -#define EMIF4_CFG_NARROW_MD (0x0 << 14) -#define EMIF4_CFG_CL (0x5 << 10) -#define EMIF4_CFG_ROWSIZE (0x0 << 7) /* --> 0x4: a0..a12 */ -#define EMIF4_CFG_IBANK (0x3 << 4) -#define EMIF4_CFG_EBANK (0x0 << 3) -#define EMIF4_CFG_PGSIZE (0x2) /* 10 columns */ - -/* - * EMIF4 PHY Control 1 register configuration - */ -#define EMIF4_DDR1_EXT_STRB_EN (0x1 << 7) -#define EMIF4_DDR1_EXT_STRB_DIS (0x0 << 7) -#define EMIF4_DDR1_PWRDN_DIS (0x0 << 6) -#define EMIF4_DDR1_PWRDN_EN (0x1 << 6) -#define EMIF4_DDR1_READ_LAT (0x6 << 0) - void am35xx_emif4_init(void); #endif /* endif _EMIF_H_ */ -- 2.32.0 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com> --- arch/arm/boards/wago-pfc-am35xx/lowlevel.c | 2 +- arch/arm/mach-omap/am35xx_emif4.c | 4 +--- arch/arm/mach-omap/include/mach/emif4.h | 2 +- 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/arm/boards/wago-pfc-am35xx/lowlevel.c b/arch/arm/boards/wago-pfc-am35xx/lowlevel.c index 7da8fd0331..63afd043a0 100644 --- a/arch/arm/boards/wago-pfc-am35xx/lowlevel.c +++ b/arch/arm/boards/wago-pfc-am35xx/lowlevel.c @@ -200,7 +200,7 @@ static noinline void pfc200_board_init(void) /* Dont reconfigure SDRAM while running in SDRAM */ if (!in_sdram) - am35xx_emif4_init(); + am35xx_emif4_init(IOMEM(OMAP3_SDRC_BASE)); barebox_arm_entry(0x80000000, SZ_256M, NULL); } diff --git a/arch/arm/mach-omap/am35xx_emif4.c b/arch/arm/mach-omap/am35xx_emif4.c index bd4fbd21e3..e61cf00c57 100644 --- a/arch/arm/mach-omap/am35xx_emif4.c +++ b/arch/arm/mach-omap/am35xx_emif4.c @@ -12,7 +12,6 @@ #include <common.h> #include <io.h> #include <mach/emif4.h> -#include <mach/omap3-silicon.h> /* * AM35xx configuration values @@ -70,9 +69,8 @@ * - Init the emif4 module for DDR access * - Early init routines, called from flash or SRAM. */ -void am35xx_emif4_init(void) +void am35xx_emif4_init(const void __iomem *emif4) { - const void __iomem *emif4 = IOMEM(OMAP3_SDRC_BASE); unsigned int regval; /* Set the DDR PHY parameters in PHY ctrl registers */ diff --git a/arch/arm/mach-omap/include/mach/emif4.h b/arch/arm/mach-omap/include/mach/emif4.h index 23d5c18fcf..10ecfe6c6b 100644 --- a/arch/arm/mach-omap/include/mach/emif4.h +++ b/arch/arm/mach-omap/include/mach/emif4.h @@ -45,6 +45,6 @@ #define EMIF4_DDR_PHY_CTRL_2 0xec #define EMIF4_IODFT_TLGC 0x60 -void am35xx_emif4_init(void); +void am35xx_emif4_init(const void __iomem *emif4); #endif /* endif _EMIF_H_ */ -- 2.32.0 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
EMIF can be used for other CPU variants. Let's rename it to be more generic. Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com> --- arch/arm/mach-omap/Makefile | 2 +- arch/arm/mach-omap/{am35xx_emif4.c => emif4.c} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename arch/arm/mach-omap/{am35xx_emif4.c => emif4.c} (100%) diff --git a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile index e81284ec3b..2c7f577856 100644 --- a/arch/arm/mach-omap/Makefile +++ b/arch/arm/mach-omap/Makefile @@ -22,7 +22,7 @@ pbl-$(CONFIG_ARCH_OMAP3) += omap3_generic.o auxcr.o obj-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o pbl-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o obj-pbl-$(CONFIG_ARCH_AM33XX) += am33xx_generic.o am33xx_clock.o am33xx_mux.o am3xxx.o -obj-pbl-$(CONFIG_ARCH_AM35XX) += am3xxx.o am35xx_emif4.o +obj-pbl-$(CONFIG_ARCH_AM35XX) += am3xxx.o emif4.o obj-$(CONFIG_ARCH_AM33XX) += am33xx_scrm.o obj-$(CONFIG_ARCH_OMAP3) += omap3_clock.o pbl-$(CONFIG_ARCH_OMAP3) += omap3_clock.o diff --git a/arch/arm/mach-omap/am35xx_emif4.c b/arch/arm/mach-omap/emif4.c similarity index 100% rename from arch/arm/mach-omap/am35xx_emif4.c rename to arch/arm/mach-omap/emif4.c -- 2.32.0 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Instead of using the registers of the control module, we will use the EMIF registers in am335x_sdram_size(). This can help when porting this function to other CPU variants. Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com> --- arch/arm/mach-omap/am33xx_generic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-omap/am33xx_generic.c b/arch/arm/mach-omap/am33xx_generic.c index bdfa0e9e26..2727ebdf7f 100644 --- a/arch/arm/mach-omap/am33xx_generic.c +++ b/arch/arm/mach-omap/am33xx_generic.c @@ -349,9 +349,9 @@ void am33xx_config_sdram(const struct am33xx_emif_regs *regs) */ unsigned long am335x_sdram_size(void) { + uint32_t sdram_config = readl(IOMEM(AM33XX_EMIF4_BASE + EMIF4_SDRAM_CONFIG)); int rows, cols, width, banks; unsigned long size; - uint32_t sdram_config = readl(CM_EMIF_SDRAM_CONFIG); rows = ((sdram_config >> 7) & 0x7) + 9; cols = (sdram_config & 0x7) + 8; -- 2.32.0 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com> --- arch/arm/mach-omap/Makefile | 2 +- arch/arm/mach-omap/am33xx_generic.c | 53 +------------------ arch/arm/mach-omap/am33xx_scrm.c | 4 +- arch/arm/mach-omap/emif4.c | 50 +++++++++++++++++ .../mach-omap/include/mach/am33xx-silicon.h | 1 - arch/arm/mach-omap/include/mach/emif4.h | 2 + 6 files changed, 58 insertions(+), 54 deletions(-) diff --git a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile index 2c7f577856..88c6b1d594 100644 --- a/arch/arm/mach-omap/Makefile +++ b/arch/arm/mach-omap/Makefile @@ -21,7 +21,7 @@ obj-$(CONFIG_ARCH_OMAP3) += omap3_generic.o auxcr.o pbl-$(CONFIG_ARCH_OMAP3) += omap3_generic.o auxcr.o obj-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o pbl-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o -obj-pbl-$(CONFIG_ARCH_AM33XX) += am33xx_generic.o am33xx_clock.o am33xx_mux.o am3xxx.o +obj-pbl-$(CONFIG_ARCH_AM33XX) += am33xx_generic.o am33xx_clock.o am33xx_mux.o am3xxx.o emif4.o obj-pbl-$(CONFIG_ARCH_AM35XX) += am3xxx.o emif4.o obj-$(CONFIG_ARCH_AM33XX) += am33xx_scrm.o obj-$(CONFIG_ARCH_OMAP3) += omap3_clock.o diff --git a/arch/arm/mach-omap/am33xx_generic.c b/arch/arm/mach-omap/am33xx_generic.c index 2727ebdf7f..bfe5b3dc73 100644 --- a/arch/arm/mach-omap/am33xx_generic.c +++ b/arch/arm/mach-omap/am33xx_generic.c @@ -342,59 +342,10 @@ void am33xx_config_sdram(const struct am33xx_emif_regs *regs) writel(regs->sdram_config, emif4 + EMIF4_SDRAM_CONFIG); } -/** - * am335x_sdram_size - read back SDRAM size from sdram_config register - * - * @return: The SDRAM size - */ -unsigned long am335x_sdram_size(void) -{ - uint32_t sdram_config = readl(IOMEM(AM33XX_EMIF4_BASE + EMIF4_SDRAM_CONFIG)); - int rows, cols, width, banks; - unsigned long size; - - rows = ((sdram_config >> 7) & 0x7) + 9; - cols = (sdram_config & 0x7) + 8; - - switch ((sdram_config >> 14) & 0x3) { - case 0: - width = 4; - break; - case 1: - width = 2; - break; - default: - return 0; - } - - switch ((sdram_config >> 4) & 0x7) { - case 0: - banks = 1; - break; - case 1: - banks = 2; - break; - case 2: - banks = 4; - break; - case 3: - banks = 8; - break; - default: - return 0; - } - - size = (1 << rows) * (1 << cols) * banks * width; - - debug("%s: sdram_config: 0x%08x cols: %2d rows: %2d width: %2d banks: %2d size: 0x%08lx\n", - __func__, sdram_config, cols, rows, width, banks, size); - - return size; -} - void __noreturn am335x_barebox_entry(void *boarddata) { - barebox_arm_entry(0x80000000, am335x_sdram_size(), boarddata); + barebox_arm_entry(0x80000000, + emif4_sdram_size(IOMEM(AM33XX_EMIF4_BASE)), boarddata); } void am33xx_config_io_ctrl(int ioctrl) diff --git a/arch/arm/mach-omap/am33xx_scrm.c b/arch/arm/mach-omap/am33xx_scrm.c index 0f13a9deb6..e10e80ce31 100644 --- a/arch/arm/mach-omap/am33xx_scrm.c +++ b/arch/arm/mach-omap/am33xx_scrm.c @@ -21,10 +21,12 @@ #include <asm/barebox-arm.h> #include <asm/memory.h> #include <mach/am33xx-silicon.h> +#include <mach/emif4.h> static int am33xx_scrm_probe(struct device_d *dev) { - return arm_add_mem_device("ram0", 0x80000000, am335x_sdram_size()); + return arm_add_mem_device("ram0", 0x80000000, + emif4_sdram_size(IOMEM(AM33XX_EMIF4_BASE))); } static __maybe_unused struct of_device_id am33xx_scrm_dt_ids[] = { diff --git a/arch/arm/mach-omap/emif4.c b/arch/arm/mach-omap/emif4.c index e61cf00c57..b5a53e8c63 100644 --- a/arch/arm/mach-omap/emif4.c +++ b/arch/arm/mach-omap/emif4.c @@ -65,6 +65,56 @@ #define EMIF4_DDR1_PWRDN_EN (0x1 << 6) #define EMIF4_DDR1_READ_LAT (0x6 << 0) +/** + * emif4_sdram_size - read back SDRAM size from sdram_config register + * + * @return: The SDRAM size + */ +unsigned long emif4_sdram_size(const void __iomem *emif4) +{ + uint32_t sdram_config = readl(emif4 + EMIF4_SDRAM_CONFIG); + int rows, cols, width, banks; + unsigned long size; + + rows = ((sdram_config >> 7) & 0x7) + 9; + cols = (sdram_config & 0x7) + 8; + + switch ((sdram_config >> 14) & 0x3) { + case 0: + width = 4; + break; + case 1: + width = 2; + break; + default: + return 0; + } + + switch ((sdram_config >> 4) & 0x7) { + case 0: + banks = 1; + break; + case 1: + banks = 2; + break; + case 2: + banks = 4; + break; + case 3: + banks = 8; + break; + default: + return 0; + } + + size = (1 << rows) * (1 << cols) * banks * width; + + debug("SDRAM_CONFIG: 0x%08x, cols: %2d, rows: %2d, width: %2d, banks: %2d, size: 0x%08lx\n", + sdram_config, cols, rows, width, banks, size); + + return size; +} + /* * - Init the emif4 module for DDR access * - Early init routines, called from flash or SRAM. diff --git a/arch/arm/mach-omap/include/mach/am33xx-silicon.h b/arch/arm/mach-omap/include/mach/am33xx-silicon.h index 671706ff49..74b0b7638e 100644 --- a/arch/arm/mach-omap/include/mach/am33xx-silicon.h +++ b/arch/arm/mach-omap/include/mach/am33xx-silicon.h @@ -220,7 +220,6 @@ void am33xx_config_ddr_data(const struct am33xx_ddr_data *data, int macronr); void am335x_sdram_init(int ioctrl, const struct am33xx_cmd_control *cmd_ctrl, const struct am33xx_emif_regs *emif_regs, const struct am33xx_ddr_data *ddr_data); -unsigned long am335x_sdram_size(void); void am335x_barebox_entry(void *boarddata); #endif diff --git a/arch/arm/mach-omap/include/mach/emif4.h b/arch/arm/mach-omap/include/mach/emif4.h index 10ecfe6c6b..00702e60e8 100644 --- a/arch/arm/mach-omap/include/mach/emif4.h +++ b/arch/arm/mach-omap/include/mach/emif4.h @@ -45,6 +45,8 @@ #define EMIF4_DDR_PHY_CTRL_2 0xec #define EMIF4_IODFT_TLGC 0x60 +unsigned long emif4_sdram_size(const void __iomem *emif4); + void am35xx_emif4_init(const void __iomem *emif4); #endif /* endif _EMIF_H_ */ -- 2.32.0 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
On Fri, Jun 03, 2022 at 02:25:33PM +0300, Alexander Shiyan wrote: > Currently we have three different definitions for EMIF management: > - Offsets > - Offsets relative to the base address > - Offsets in the structure > > The patch represents the first attempt to unify this. > > Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com> > --- > arch/arm/boards/afi-gf/lowlevel.c | 39 +++++++++--------- > arch/arm/mach-omap/am33xx_generic.c | 41 +++++++++---------- > .../mach-omap/include/mach/am33xx-silicon.h | 10 +---- > 3 files changed, 42 insertions(+), 48 deletions(-) Looks all good and is a nice cleanup, so applied despite its RFC status. One thing I found in the context of this patch: > static void board_config_emif_ddr(void) > { > + const void __iomem *emif4 = IOMEM(AM33XX_EMIF4_BASE); > u32 i; [...] > > for (i = 0; i < 5000; i++) { > > } I wonder if this works. I made the experience that the compiler optimizes such loops away when the counter isn't declared as volatile. Sascha -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
вт, 7 июн. 2022 г. в 10:38, Sascha Hauer <sha@pengutronix.de> > On Fri, Jun 03, 2022 at 02:25:33PM +0300, Alexander Shiyan wrote: > > Currently we have three different definitions for EMIF management: > > - Offsets > > - Offsets relative to the base address > > - Offsets in the structure > > > > The patch represents the first attempt to unify this. > > > > Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com> > > --- > > arch/arm/boards/afi-gf/lowlevel.c | 39 +++++++++--------- > > arch/arm/mach-omap/am33xx_generic.c | 41 +++++++++---------- > > .../mach-omap/include/mach/am33xx-silicon.h | 10 +---- > > 3 files changed, 42 insertions(+), 48 deletions(-) > > Looks all good and is a nice cleanup, so applied despite its RFC status. > > One thing I found in the context of this patch: > > > static void board_config_emif_ddr(void) > > { > > + const void __iomem *emif4 = IOMEM(AM33XX_EMIF4_BASE); > > u32 i; > > [...] > > > > > for (i = 0; i < 5000; i++) { > > > > } > > I wonder if this works. I made the experience that the compiler > optimizes such loops away when the counter isn't declared as volatile. Hello. I did not touch the logic of the procedures, this is a topic for other patches, although yes, I think this empty loop can be removed. _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox