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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:3::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.ext.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-2.7 required=4.0 tests=AWL,BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.2 Subject: [RFC 2/2] clocksource: arm_global_timer: Convert driver to use clocksource context field X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.ext.pengutronix.de) Signed-off-by: Alexander Shiyan --- drivers/clocksource/arm_global_timer.c | 27 +++++++++++++++----------- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/drivers/clocksource/arm_global_timer.c b/drivers/clocksource/arm_global_timer.c index 6e2fae9ba4..3e9b90059a 100644 --- a/drivers/clocksource/arm_global_timer.c +++ b/drivers/clocksource/arm_global_timer.c @@ -27,8 +27,6 @@ #define GT_CONTROL 0x08 #define GT_CONTROL_TIMER_ENABLE BIT(0) /* this bit is NOT banked */ -static void __iomem *gt_base; - /* * To get the value from the Global Timer Counter register proceed as follows: * 1. Read the upper 32-bit timer counter register @@ -39,6 +37,7 @@ static void __iomem *gt_base; */ static uint64_t arm_global_clocksource_read(void *ctx) { + void __iomem *gt_base = ctx; uint64_t counter; uint32_t lower; uint32_t upper, old_upper; @@ -56,11 +55,25 @@ static uint64_t arm_global_clocksource_read(void *ctx) return counter; } +static int arm_global_timer_init(struct clocksource *cs) +{ + void __iomem *gt_base = cs->ctx; + + writel(0, gt_base + GT_CONTROL); + writel(0, gt_base + GT_COUNTER0); + writel(0, gt_base + GT_COUNTER1); + /* enables timer on all the cores */ + writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL); + + return 0; +} + static struct clocksource cs = { .read = arm_global_clocksource_read, .mask = CLOCKSOURCE_MASK(64), .shift = 0, .priority = 70, + .init = arm_global_timer_init, }; static int arm_global_timer_probe(struct device_d *dev) @@ -86,17 +99,9 @@ static int arm_global_timer_probe(struct device_d *dev) return ret; } - gt_base = IOMEM(iores->start); - cs.mult = clocksource_hz2mult(clk_get_rate(clk), cs.shift); - writel(0, gt_base + GT_CONTROL); - writel(0, gt_base + GT_COUNTER0); - writel(0, gt_base + GT_COUNTER1); - /* enables timer on all the cores */ - writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL); - - return init_clock(&cs, NULL); + return init_clock(&cs, IOMEM(iores->start)); } static struct of_device_id arm_global_timer_dt_ids[] = { -- 2.32.0 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox