[PATCH v2 master 3/5] ARM: i.MX8M: esdctl: ignore ADDRMAP8 for non-DDR4

[Ahmad Fatoum <a.fatoum@pengutronix.de>]

ADDRMAP8 handling was added for i.MX8MN DDR4 handling,
but as done currently has a few issues:

  - Bank groups are a DDR4 feature (well, borrowed from GDDR5),
    so we should just skip it for other RAM types

  - addrmap[8] == 0 is actually a valid value according
    to both reference manual and spreadsheet

  - Spreadsheet claims DDRC_ADDRMAP8_BG_B0 to be 6-bit, while
    reference manual claims 5-bit

  - Spreadsheet claims DDRC_ADDRMAP8_BG_B0 == 63 to be the
    neutral value. The code assumes 31 and the reference manual
    describes all values 0-31 to have an effect.

This commit fixes the first two issues. The calculation may still
be wrong, but at least for the i.MX8MN-DDR4-EVK it seems to return
a correct value of 2G.

Fixes: 42d45ef380c5 ("ARM: imx: Add imx8 support for SDRAM with two or more bank groups")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
v1 -> v2:
  - remove is_imx8 && in condition. The bit is reserved on i.MX7 and
    0 by default and the variable has been replaced in a previous
    patch
---
 arch/arm/mach-imx/esdctl.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c
index 35c9fa9a4248..a55ee06b8346 100644
--- a/arch/arm/mach-imx/esdctl.c
+++ b/arch/arm/mach-imx/esdctl.c
@@ -317,6 +317,7 @@ static int vf610_ddrmc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
 #define DDRC_ADDRMAP0_CS_BIT0			GENMASK(4, 0)
 
 #define DDRC_MSTR				0x0000
+#define DDRC_MSTR_DDR4				BIT(4)
 #define DDRC_MSTR_LPDDR4			BIT(5)
 #define DDRC_MSTR_DATA_BUS_WIDTH		GENMASK(13, 12)
 #define DDRC_MSTR_ACTIVE_RANKS			GENMASK(27, 24)
@@ -424,7 +425,12 @@ imx_ddrc_sdram_size(void __iomem *ddrc, const u32 addrmap[DDRC_ADDRMAP_LENGTH],
 	if (FIELD_GET(DDRC_ADDRMAP1_BANK_B2, addrmap[1]) != 0b11111)
 		banks++;
 
-	if (addrmap[8]) {
+	if (mstr & DDRC_MSTR_DDR4) {
+		/* FIXME: DDR register spreasheet claims this to be
+		 * 6-bit and 63 meaning bank group address bit 0 is 0,
+		 * but reference manual claims 5-bit without 'neutral' value
+		 * See MX8M_Mini_DDR4_RPA_v17, MX8M_Nano_DDR4_RPA_v8
+		 */
 		if (FIELD_GET(DDRC_ADDRMAP8_BG_B0, addrmap[8]) != 0b11111)
 			banks++;
 		if (FIELD_GET(DDRC_ADDRMAP8_BG_B1, addrmap[8]) != 0b111111)
-- 
2.30.2