[PATCH 1/3] video: stm32: stm32_ltdc: fix data enable polarity

[PATCH 1/3] video: stm32: stm32_ltdc: fix data enable polarity

[Ahmad Fatoum]

From: Yannick FERTRE <yannick.fertre@foss.st.com>

Wrong DISPLAY_FLAGS used to set the data enable polarity.

Signed-off-by: Yannick FERTRE <yannick.fertre@foss.st.com>
Origin: https://st-md-mailman.stormreply.com/pipermail/uboot-stm32/2022-April/005122.html
[afa: cherry-picked from U-Boot driver]
Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
---
 drivers/video/stm32_ltdc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/video/stm32_ltdc.c b/drivers/video/stm32_ltdc.c
index 645c20b5545f..9dc35ade6124 100644
--- a/drivers/video/stm32_ltdc.c
+++ b/drivers/video/stm32_ltdc.c
@@ -98,7 +98,7 @@ static void ltdc_set_mode(struct ltdc_fb *priv,
 		val |= GCR_HSPOL;
 	if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
 		val |= GCR_VSPOL;
-	if (mode->display_flags & DISPLAY_FLAGS_DE_HIGH)
+	if (mode->display_flags & DISPLAY_FLAGS_DE_LOW)
 		val |= GCR_DEPOL;
 	if (mode->display_flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
 		val |= GCR_PCPOL;
-- 
2.34.1

[PATCH 2/3] pinctrl: stm32: keep GPIO bank clocks enabled throughout

[Ahmad Fatoum]

Mirror the Linux change of always keeping the clocks running. For
barebox. This simplifies the code and improves bitbanging throughput.

Origin: https://lore.kernel.org/all/20220422143608.226580-1-fabien.dessenne@foss.st.com/
Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
---
 drivers/pinctrl/pinctrl-stm32.c | 42 +++++++--------------------------
 1 file changed, 9 insertions(+), 33 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-stm32.c b/drivers/pinctrl/pinctrl-stm32.c
index cee10636cef9..fc0cc78f430d 100644
--- a/drivers/pinctrl/pinctrl-stm32.c
+++ b/drivers/pinctrl/pinctrl-stm32.c
@@ -24,7 +24,6 @@
 struct stm32_gpio_bank {
 	void __iomem *base;
 	struct gpio_chip chip;
-	struct clk *clk;
 	const char *name;
 };
 
@@ -154,8 +153,6 @@ static int __stm32_pinctrl_set_state(struct device_d *dev, struct device_node *p
 			"fn %u, mode %u, alt %u\n",
 			bank->name, offset, func, mode, alt);
 
-		clk_enable(bank->clk);
-
 		__stm32_pmx_set_mode(bank->base, offset, mode, alt);
 
 		if (adjust_slew_rate)
@@ -173,8 +170,6 @@ static int __stm32_pinctrl_set_state(struct device_d *dev, struct device_node *p
 			__stm32_pmx_gpio_output(bank->base, offset, 0);
 		else if (dir == PIN_OUTPUT_HIGH)
 			__stm32_pmx_gpio_output(bank->base, offset, 1);
-
-		clk_disable(bank->clk);
 	}
 
 	return 0;
@@ -219,8 +214,6 @@ static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
 	int ret;
 	u32 mode, alt;
 
-	clk_enable(bank->clk);
-
 	__stm32_pmx_get_mode(bank->base, stm32_gpio_pin(gpio, NULL), &mode, &alt);
 	if ((alt == 0) && (mode == 0))
 		ret = 1;
@@ -229,8 +222,6 @@ static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
 	else
 		ret = -EINVAL;
 
-	clk_disable(bank->clk);
-
 	return ret;
 }
 
@@ -238,37 +229,22 @@ static void stm32_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
 {
 	struct stm32_gpio_bank *bank = to_stm32_gpio_bank(chip);
 
-	clk_enable(bank->clk);
-
 	__stm32_pmx_gpio_set(bank->base, stm32_gpio_pin(gpio, NULL), value);
-
-	clk_disable(bank->clk);
 }
 
 static int stm32_gpio_get(struct gpio_chip *chip, unsigned gpio)
 {
 	struct stm32_gpio_bank *bank = to_stm32_gpio_bank(chip);
-	int ret;
-
-	clk_enable(bank->clk);
-
-	ret = __stm32_pmx_gpio_get(bank->base, stm32_gpio_pin(gpio, NULL));
 
-	clk_disable(bank->clk);
-
-	return ret;
+	return __stm32_pmx_gpio_get(bank->base, stm32_gpio_pin(gpio, NULL));
 }
 
 static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
 {
 	struct stm32_gpio_bank *bank = to_stm32_gpio_bank(chip);
 
-	clk_enable(bank->clk);
-
 	__stm32_pmx_gpio_input(bank->base, stm32_gpio_pin(gpio, NULL));
 
-	clk_disable(bank->clk);
-
 	return 0;
 }
 
@@ -277,12 +253,8 @@ static int stm32_gpio_direction_output(struct gpio_chip *chip,
 {
 	struct stm32_gpio_bank *bank = to_stm32_gpio_bank(chip);
 
-	clk_enable(bank->clk);
-
 	__stm32_pmx_gpio_output(bank->base, stm32_gpio_pin(gpio, NULL), value);
 
-	clk_disable(bank->clk);
-
 	return 0;
 }
 
@@ -302,6 +274,7 @@ static int stm32_gpiochip_add(struct stm32_gpio_bank *bank,
 	struct resource *iores;
 	enum { PINCTRL_PHANDLE, GPIOCTRL_OFFSET, PINCTRL_OFFSET, PINCOUNT, GPIO_RANGE_NCELLS };
 	const __be32 *gpio_ranges;
+	struct clk *clk;
 	u32 ngpios;
 	int ret, size;
 
@@ -350,12 +323,15 @@ static int stm32_gpiochip_add(struct stm32_gpio_bank *bank,
 	bank->chip.base = be32_to_cpu(gpio_ranges[PINCTRL_OFFSET]);
 	bank->chip.ops  = &stm32_gpio_ops;
 	bank->chip.dev  = dev;
-	bank->clk = clk_get(dev, NULL);
-	if (IS_ERR(bank->clk)) {
-		dev_err(dev, "failed to get clk (%ld)\n", PTR_ERR(bank->clk));
-		return PTR_ERR(bank->clk);
+
+	clk = clk_get(dev, NULL);
+	if (IS_ERR(clk)) {
+		dev_err(dev, "failed to get clk (%ld)\n", PTR_ERR(clk));
+		return PTR_ERR(clk);
 	}
 
+	clk_enable(clk);
+
 	return gpiochip_add(&bank->chip);
 }
 
-- 
2.34.1

[PATCH 3/3] spi: stm32: fix reads for sizes bigger than SZ_64K-1

[Ahmad Fatoum]

stm32_spi_transfer_one() can transfer no more than SPI_CR2_TSIZE (64K - 1),
while e.g. imd tends to read more than  (64K - 1) from SPI flash:

  barebox:/ imd /dev/m25p0
  imd: error 90

Define spi_controller_mem_ops::exec_op for the SPI controller to fix
this.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
---
 drivers/spi/stm32_spi.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/spi/stm32_spi.c b/drivers/spi/stm32_spi.c
index 0cb04a968c8a..d38207edac5f 100644
--- a/drivers/spi/stm32_spi.c
+++ b/drivers/spi/stm32_spi.c
@@ -11,6 +11,7 @@
 #include <init.h>
 #include <errno.h>
 #include <linux/reset.h>
+#include <linux/spi/spi-mem.h>
 #include <spi/spi.h>
 #include <linux/bitops.h>
 #include <clock.h>
@@ -474,6 +475,24 @@ out:
 	return ret;
 }
 
+static int stm32_spi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
+{
+	if (op->data.nbytes > SPI_CR2_TSIZE)
+		op->data.nbytes = SPI_CR2_TSIZE;
+
+	return 0;
+}
+
+static int stm32_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
+{
+	return -ENOTSUPP;
+}
+
+static const struct spi_controller_mem_ops stm32_spi_mem_ops = {
+	.adjust_op_size = stm32_spi_adjust_op_size,
+	.exec_op = stm32_spi_exec_op,
+};
+
 static int stm32_spi_get_fifo_size(struct stm32_spi_priv *priv)
 {
 	u32 count = 0;
@@ -522,6 +541,7 @@ static int stm32_spi_probe(struct device_d *dev)
 
 	master->setup = stm32_spi_setup;
 	master->transfer = stm32_spi_transfer;
+	master->mem_ops = stm32_spi_mem_ops;
 
 	master->bus_num = -1;
 	stm32_spi_dt_probe(priv);
-- 
2.34.1

Re: [PATCH 1/3] video: stm32: stm32_ltdc: fix data enable polarity

[Sascha Hauer]

On Fri, Jul 08, 2022 at 07:52:48AM +0200, Ahmad Fatoum wrote:
> From: Yannick FERTRE <yannick.fertre@foss.st.com>
> 
> Wrong DISPLAY_FLAGS used to set the data enable polarity.
> 
> Signed-off-by: Yannick FERTRE <yannick.fertre@foss.st.com>
> Origin: https://st-md-mailman.stormreply.com/pipermail/uboot-stm32/2022-April/005122.html
> [afa: cherry-picked from U-Boot driver]
> Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
> ---
>  drivers/video/stm32_ltdc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Applied, thanks

Sascha

> 
> diff --git a/drivers/video/stm32_ltdc.c b/drivers/video/stm32_ltdc.c
> index 645c20b5545f..9dc35ade6124 100644
> --- a/drivers/video/stm32_ltdc.c
> +++ b/drivers/video/stm32_ltdc.c
> @@ -98,7 +98,7 @@ static void ltdc_set_mode(struct ltdc_fb *priv,
>  		val |= GCR_HSPOL;
>  	if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
>  		val |= GCR_VSPOL;
> -	if (mode->display_flags & DISPLAY_FLAGS_DE_HIGH)
> +	if (mode->display_flags & DISPLAY_FLAGS_DE_LOW)
>  		val |= GCR_DEPOL;
>  	if (mode->display_flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
>  		val |= GCR_PCPOL;
> -- 
> 2.34.1
> 
> 
> 

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