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From: Sascha Hauer <sha@pengutronix.de>
To: Alexander Shiyan <eagle.alexander923@gmail.com>
Cc: barebox@lists.infradead.org
Subject: Re: [PATCH] clk: imx5: Add support for watchdog clock
Date: Wed, 26 Oct 2022 06:20:31 +0200	[thread overview]
Message-ID: <20221026042031.GO6702@pengutronix.de> (raw)
In-Reply-To: <20221024114940.26197-1-eagle.alexander923@gmail.com>

On Mon, Oct 24, 2022 at 02:49:40PM +0300, Alexander Shiyan wrote:
> This adds a dummy clock definition for i.MX-50/51/53 CPUs,
> what makes the driver work.
> 
> Fixes: 87cad179648 ("watchdog: imxwd: get and enable clock")
> Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com>
> ---
>  drivers/clk/imx/clk-imx5.c | 7 +++++++
>  1 file changed, 7 insertions(+)

Applied to master, thanks

Sascha

> 
> diff --git a/drivers/clk/imx/clk-imx5.c b/drivers/clk/imx/clk-imx5.c
> index c7a1818bd7..81af9a9c88 100644
> --- a/drivers/clk/imx/clk-imx5.c
> +++ b/drivers/clk/imx/clk-imx5.c
> @@ -205,6 +205,8 @@ static void __init mx5_clocks_common_init(struct device_d *dev, void __iomem *ba
>  	writel(0xffffffff, base + CCM_CCGR6);
>  	writel(0xffffffff, base + CCM_CCGR7);
>  
> +	clks[IMX5_CLK_DUMMY] = clk_fixed("dummy", 0);
> +
>  	if (!IS_ENABLED(CONFIG_COMMON_CLK_OF_PROVIDER) || !dev->device_node) {
>  		clks[IMX5_CLK_CKIL] = clk_fixed("ckil", 32768);
>  		clks[IMX5_CLK_OSC] = clk_fixed("osc", 24000000);
> @@ -312,6 +314,7 @@ static int __init mx50_clocks_init(struct device_d *dev, void __iomem *regs)
>  	clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX50_PWM1_BASE_ADDR, "per");
>  	clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX50_PWM2_BASE_ADDR, "per");
>  	clkdev_add_physbase(clks[IMX5_CLK_AHB], MX50_OTG_BASE_ADDR, NULL);
> +	clkdev_add_physbase(clks[IMX5_CLK_DUMMY], MX50_WDOG1_BASE_ADDR, NULL);
>  
>  	return 0;
>  }
> @@ -392,6 +395,8 @@ static int __init mx51_clocks_init(struct device_d *dev, void __iomem *regs)
>  	clkdev_add_physbase(clks[IMX5_CLK_IPG], MX51_ATA_BASE_ADDR, NULL);
>  	clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX51_PWM1_BASE_ADDR, "per");
>  	clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX51_PWM2_BASE_ADDR, "per");
> +	clkdev_add_physbase(clks[IMX5_CLK_DUMMY], MX51_WDOG_BASE_ADDR, NULL);
> +	clkdev_add_physbase(clks[IMX5_CLK_DUMMY], MX51_WDOG2_BASE_ADDR, NULL);
>  
>  	if (IS_ENABLED(CONFIG_DRIVER_VIDEO_IMX_IPUV3))
>  		mx51_clocks_ipu_init(regs);
> @@ -488,6 +493,8 @@ static int __init mx53_clocks_init(struct device_d *dev, void __iomem *regs)
>  	clkdev_add_physbase(clks[IMX5_CLK_AHB], MX53_SATA_BASE_ADDR, NULL);
>  	clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX53_PWM1_BASE_ADDR, "per");
>  	clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX53_PWM2_BASE_ADDR, "per");
> +	clkdev_add_physbase(clks[IMX5_CLK_DUMMY], MX53_WDOG1_BASE_ADDR, NULL);
> +	clkdev_add_physbase(clks[IMX5_CLK_DUMMY], MX53_WDOG2_BASE_ADDR, NULL);
>  
>  	if (IS_ENABLED(CONFIG_DRIVER_VIDEO_IMX_IPUV3))
>  		mx53_clocks_ipu_init(regs);
> -- 
> 2.37.3
> 
> 
> 

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      reply	other threads:[~2022-10-26  4:22 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-24 11:49 Alexander Shiyan
2022-10-26  4:20 ` Sascha Hauer [this message]

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