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[2.205.236.27]) by smtp.gmail.com with ESMTPSA id g7-20020a056402090700b00463b9d47e1fsm482851edz.71.2022.11.01.03.33.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Nov 2022 03:33:46 -0700 (PDT) From: Vyacheslav Yurkov To: barebox@lists.infradead.org Cc: Vyacheslav Yurkov Date: Tue, 1 Nov 2022 11:33:27 +0100 Message-Id: <20221101103327.985435-2-uvv.mail@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221101103327.985435-1-uvv.mail@gmail.com> References: <20221101103327.985435-1-uvv.mail@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221101_033348_900304_72D3B02D X-CRM114-Status: GOOD ( 10.71 ) X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:3::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.ext.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-5.0 required=4.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.2 Subject: [PATCH v2 2/2] ARM: socfpga: Configure F2SDRAM bridges X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.ext.pengutronix.de) From: Vyacheslav Yurkov When DDR firewall configuration is updated the F2SDRAM bridges need to be brought from reset. Signed-off-by: Vyacheslav Yurkov --- arch/arm/mach-socfpga/arria10-sdram.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/mach-socfpga/arria10-sdram.c b/arch/arm/mach-socfpga/arria10-sdram.c index b7eade0b17..a6eb63299a 100644 --- a/arch/arm/mach-socfpga/arria10-sdram.c +++ b/arch/arm/mach-socfpga/arria10-sdram.c @@ -468,6 +468,18 @@ static void arria10_sdram_mmr_init(void) } } +static void arria10_f2sdram_bridges_reset(void) +{ + uint32_t val; + + /* Release F2SDRAM bridges from reset */ + val = readl(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_BRGMODRST); + val &= ~(ARRIA10_RSTMGR_BRGMODRST_F2SSDRAM0 | + ARRIA10_RSTMGR_BRGMODRST_F2SSDRAM1 | + ARRIA10_RSTMGR_BRGMODRST_F2SSDRAM2); + writel(val, ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_BRGMODRST); +} + static int arria10_sdram_firewall_setup(void) { uint32_t mpu_en = 0; @@ -512,6 +524,8 @@ static int arria10_sdram_firewall_setup(void) writel(0xffff0000, ARRIA10_NOC_FW_DDR_L3_HPSREGION0ADDR); writel(ARRIA10_NOC_FW_DDR_L3_HPSREG0EN, ARRIA10_NOC_FW_DDR_L3_EN); + arria10_f2sdram_bridges_reset(); + return 0; } -- 2.25.1