From: Marco Felsch <m.felsch@pengutronix.de>
To: John Watts <contact@jookia.org>
Cc: barebox@lists.infradead.org
Subject: Re: [PATCH] ARM: i.MX6: Specify OCRAM base address and size
Date: Thu, 26 Jan 2023 19:45:11 +0100 [thread overview]
Message-ID: <20230126184511.a4an5antemsc6lvl@pengutronix.de> (raw)
In-Reply-To: <20230126183624.85500-1-contact@jookia.org>
Hi John,
thanks for the patch.
On 23-01-27, John Watts wrote:
> The i.MX6 includes some on-chip RAM: 128KiB on most variants, with 256KiB
> on the Dual and Quad variants.
>
> This region is where the first stage of Barebox gets loaded if RAM
> initialization isn't hard coded using DCD information.
>
> Add the base address and size so it can be used to calculate where to put
> the stack at boot.
>
> Signed-off-by: John Watts <contact@jookia.org>
> ---
> arch/arm/mach-imx/include/mach/imx6-regs.h | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm/mach-imx/include/mach/imx6-regs.h b/arch/arm/mach-imx/include/mach/imx6-regs.h
> index 39e2751533..4acbb9796b 100644
> --- a/arch/arm/mach-imx/include/mach/imx6-regs.h
> +++ b/arch/arm/mach-imx/include/mach/imx6-regs.h
> @@ -3,6 +3,10 @@
> #ifndef __MACH_IMX6_REGS_H
> #define __MACH_IMX6_REGS_H
>
> +/* Set MAX_SIZE to 128K, only the Quad and Dual have 256K */
> +#define MX6_OCRAM_BASE_ADDR 0x00900000
> +#define MX6_OCRAM_MAX_SIZE 0x00100000
^
But this is not 128K instead it is 1M, therefore and for better
readability can we please use the SZ_128K macro? :)
Regards,
Marco
next prev parent reply other threads:[~2023-01-26 18:46 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-26 18:36 John Watts
2023-01-26 18:45 ` Marco Felsch [this message]
2023-01-26 19:02 ` [PATCH v2] " John Watts
2023-01-27 8:06 ` Marco Felsch
2023-01-27 8:56 ` John Watts
2023-01-30 8:08 ` Sascha Hauer
2023-01-30 8:08 ` Sascha Hauer
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