* [PATCH] ARM: i.MX6: Specify OCRAM base address and size
@ 2023-01-26 18:36 John Watts
2023-01-26 18:45 ` Marco Felsch
2023-01-26 19:02 ` [PATCH v2] " John Watts
0 siblings, 2 replies; 7+ messages in thread
From: John Watts @ 2023-01-26 18:36 UTC (permalink / raw)
To: barebox; +Cc: John Watts
The i.MX6 includes some on-chip RAM: 128KiB on most variants, with 256KiB
on the Dual and Quad variants.
This region is where the first stage of Barebox gets loaded if RAM
initialization isn't hard coded using DCD information.
Add the base address and size so it can be used to calculate where to put
the stack at boot.
Signed-off-by: John Watts <contact@jookia.org>
---
arch/arm/mach-imx/include/mach/imx6-regs.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-imx/include/mach/imx6-regs.h b/arch/arm/mach-imx/include/mach/imx6-regs.h
index 39e2751533..4acbb9796b 100644
--- a/arch/arm/mach-imx/include/mach/imx6-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx6-regs.h
@@ -3,6 +3,10 @@
#ifndef __MACH_IMX6_REGS_H
#define __MACH_IMX6_REGS_H
+/* Set MAX_SIZE to 128K, only the Quad and Dual have 256K */
+#define MX6_OCRAM_BASE_ADDR 0x00900000
+#define MX6_OCRAM_MAX_SIZE 0x00100000
+
#define MX6_APBH_BASE_ADDR 0x00110000
#define MX6_GPMI_BASE_ADDR 0x00112000
#define MX6_BCH_BASE_ADDR 0x00114000
--
2.39.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] ARM: i.MX6: Specify OCRAM base address and size
2023-01-26 18:36 [PATCH] ARM: i.MX6: Specify OCRAM base address and size John Watts
@ 2023-01-26 18:45 ` Marco Felsch
2023-01-26 19:02 ` [PATCH v2] " John Watts
1 sibling, 0 replies; 7+ messages in thread
From: Marco Felsch @ 2023-01-26 18:45 UTC (permalink / raw)
To: John Watts; +Cc: barebox
Hi John,
thanks for the patch.
On 23-01-27, John Watts wrote:
> The i.MX6 includes some on-chip RAM: 128KiB on most variants, with 256KiB
> on the Dual and Quad variants.
>
> This region is where the first stage of Barebox gets loaded if RAM
> initialization isn't hard coded using DCD information.
>
> Add the base address and size so it can be used to calculate where to put
> the stack at boot.
>
> Signed-off-by: John Watts <contact@jookia.org>
> ---
> arch/arm/mach-imx/include/mach/imx6-regs.h | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm/mach-imx/include/mach/imx6-regs.h b/arch/arm/mach-imx/include/mach/imx6-regs.h
> index 39e2751533..4acbb9796b 100644
> --- a/arch/arm/mach-imx/include/mach/imx6-regs.h
> +++ b/arch/arm/mach-imx/include/mach/imx6-regs.h
> @@ -3,6 +3,10 @@
> #ifndef __MACH_IMX6_REGS_H
> #define __MACH_IMX6_REGS_H
>
> +/* Set MAX_SIZE to 128K, only the Quad and Dual have 256K */
> +#define MX6_OCRAM_BASE_ADDR 0x00900000
> +#define MX6_OCRAM_MAX_SIZE 0x00100000
^
But this is not 128K instead it is 1M, therefore and for better
readability can we please use the SZ_128K macro? :)
Regards,
Marco
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2] ARM: i.MX6: Specify OCRAM base address and size
2023-01-26 18:36 [PATCH] ARM: i.MX6: Specify OCRAM base address and size John Watts
2023-01-26 18:45 ` Marco Felsch
@ 2023-01-26 19:02 ` John Watts
2023-01-27 8:06 ` Marco Felsch
2023-01-30 8:08 ` Sascha Hauer
1 sibling, 2 replies; 7+ messages in thread
From: John Watts @ 2023-01-26 19:02 UTC (permalink / raw)
To: barebox; +Cc: John Watts
The i.MX6 includes some on-chip RAM: 128KiB on most variants, with 256KiB on
the Dual and Quad variants.
This region is where the first stage of Barebox gets loaded if RAM
initialization isn't hard coded using DCD information.
Add the base address and size so it can be used to calculate where to put the
stack at boot.
Signed-off-by: John Watts <contact@jookia.org>
---
Changes v1 -> v2:
- Fixed wrong size (thanks Marco!)
---
arch/arm/mach-imx/include/mach/imx6-regs.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-imx/include/mach/imx6-regs.h b/arch/arm/mach-imx/include/mach/imx6-regs.h
index 39e2751533..89a3b267c6 100644
--- a/arch/arm/mach-imx/include/mach/imx6-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx6-regs.h
@@ -3,6 +3,12 @@
#ifndef __MACH_IMX6_REGS_H
#define __MACH_IMX6_REGS_H
+#include <linux/sizes.h>
+
+/* Set MAX_SIZE to 128K, only the Quad and Dual have 256K */
+#define MX6_OCRAM_BASE_ADDR 0x00900000
+#define MX6_OCRAM_MAX_SIZE SZ_128K
+
#define MX6_APBH_BASE_ADDR 0x00110000
#define MX6_GPMI_BASE_ADDR 0x00112000
#define MX6_BCH_BASE_ADDR 0x00114000
--
2.39.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2] ARM: i.MX6: Specify OCRAM base address and size
2023-01-26 19:02 ` [PATCH v2] " John Watts
@ 2023-01-27 8:06 ` Marco Felsch
2023-01-27 8:56 ` John Watts
2023-01-30 8:08 ` Sascha Hauer
1 sibling, 1 reply; 7+ messages in thread
From: Marco Felsch @ 2023-01-27 8:06 UTC (permalink / raw)
To: John Watts; +Cc: barebox
Hi John,
On 23-01-27, John Watts wrote:
> The i.MX6 includes some on-chip RAM: 128KiB on most variants, with 256KiB on
> the Dual and Quad variants.
>
> This region is where the first stage of Barebox gets loaded if RAM
> initialization isn't hard coded using DCD information.
>
> Add the base address and size so it can be used to calculate where to put the
> stack at boot.
>
> Signed-off-by: John Watts <contact@jookia.org>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2] ARM: i.MX6: Specify OCRAM base address and size
2023-01-27 8:06 ` Marco Felsch
@ 2023-01-27 8:56 ` John Watts
2023-01-30 8:08 ` Sascha Hauer
0 siblings, 1 reply; 7+ messages in thread
From: John Watts @ 2023-01-27 8:56 UTC (permalink / raw)
To: Marco Felsch; +Cc: barebox
On Fri, Jan 27, 2023 at 09:06:33AM +0100, Marco Felsch wrote:
> Hi John,
>
> On 23-01-27, John Watts wrote:
> > The i.MX6 includes some on-chip RAM: 128KiB on most variants, with 256KiB on
> > the Dual and Quad variants.
> >
> > This region is where the first stage of Barebox gets loaded if RAM
> > initialization isn't hard coded using DCD information.
> >
> > Add the base address and size so it can be used to calculate where to put the
> > stack at boot.
> >
> > Signed-off-by: John Watts <contact@jookia.org>
>
> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Do I add that to a V3? :)
Should I add the review stuff to my Novena patches too?
John.
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2] ARM: i.MX6: Specify OCRAM base address and size
2023-01-27 8:56 ` John Watts
@ 2023-01-30 8:08 ` Sascha Hauer
0 siblings, 0 replies; 7+ messages in thread
From: Sascha Hauer @ 2023-01-30 8:08 UTC (permalink / raw)
To: John Watts; +Cc: Marco Felsch, barebox
On Fri, Jan 27, 2023 at 07:56:42PM +1100, John Watts wrote:
> On Fri, Jan 27, 2023 at 09:06:33AM +0100, Marco Felsch wrote:
> > Hi John,
> >
> > On 23-01-27, John Watts wrote:
> > > The i.MX6 includes some on-chip RAM: 128KiB on most variants, with 256KiB on
> > > the Dual and Quad variants.
> > >
> > > This region is where the first stage of Barebox gets loaded if RAM
> > > initialization isn't hard coded using DCD information.
> > >
> > > Add the base address and size so it can be used to calculate where to put the
> > > stack at boot.
> > >
> > > Signed-off-by: John Watts <contact@jookia.org>
> >
> > Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
>
> Do I add that to a V3? :)
No. I collect the Reviewed-by tags while applying. Or better, git b4
does this automatically for me ;)
> Should I add the review stuff to my Novena patches too?
Usually when sending a new series you add the tags you got from the
previous one, but just adding tags is not a reason for resending.
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2] ARM: i.MX6: Specify OCRAM base address and size
2023-01-26 19:02 ` [PATCH v2] " John Watts
2023-01-27 8:06 ` Marco Felsch
@ 2023-01-30 8:08 ` Sascha Hauer
1 sibling, 0 replies; 7+ messages in thread
From: Sascha Hauer @ 2023-01-30 8:08 UTC (permalink / raw)
To: John Watts; +Cc: barebox
On Fri, Jan 27, 2023 at 06:02:58AM +1100, John Watts wrote:
> The i.MX6 includes some on-chip RAM: 128KiB on most variants, with 256KiB on
> the Dual and Quad variants.
>
> This region is where the first stage of Barebox gets loaded if RAM
> initialization isn't hard coded using DCD information.
>
> Add the base address and size so it can be used to calculate where to put the
> stack at boot.
>
> Signed-off-by: John Watts <contact@jookia.org>
> ---
> Changes v1 -> v2:
> - Fixed wrong size (thanks Marco!)
> ---
> arch/arm/mach-imx/include/mach/imx6-regs.h | 6 ++++++
> 1 file changed, 6 insertions(+)
Applied, thanks
Sascha
>
> diff --git a/arch/arm/mach-imx/include/mach/imx6-regs.h b/arch/arm/mach-imx/include/mach/imx6-regs.h
> index 39e2751533..89a3b267c6 100644
> --- a/arch/arm/mach-imx/include/mach/imx6-regs.h
> +++ b/arch/arm/mach-imx/include/mach/imx6-regs.h
> @@ -3,6 +3,12 @@
> #ifndef __MACH_IMX6_REGS_H
> #define __MACH_IMX6_REGS_H
>
> +#include <linux/sizes.h>
> +
> +/* Set MAX_SIZE to 128K, only the Quad and Dual have 256K */
> +#define MX6_OCRAM_BASE_ADDR 0x00900000
> +#define MX6_OCRAM_MAX_SIZE SZ_128K
> +
> #define MX6_APBH_BASE_ADDR 0x00110000
> #define MX6_GPMI_BASE_ADDR 0x00112000
> #define MX6_BCH_BASE_ADDR 0x00114000
> --
> 2.39.1
>
>
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 7+ messages in thread
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2023-01-26 18:36 [PATCH] ARM: i.MX6: Specify OCRAM base address and size John Watts
2023-01-26 18:45 ` Marco Felsch
2023-01-26 19:02 ` [PATCH v2] " John Watts
2023-01-27 8:06 ` Marco Felsch
2023-01-27 8:56 ` John Watts
2023-01-30 8:08 ` Sascha Hauer
2023-01-30 8:08 ` Sascha Hauer
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