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X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Denis Orlov Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:3::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.ext.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-4.5 required=4.0 tests=AWL,BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: [PATCH 3/4] MIPS: dma: add arch-specific dma_alloc() implementation X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.ext.pengutronix.de) DMA allocations should be aligned on a cache line size, at least on cache non-coherent MIPS systems. Instead of using some hardcoded value for an alignment from a generic implementation (which may be wrong for us), we can get cache info from 'current_cpu_data' variable, so use it. Signed-off-by: Denis Orlov --- arch/mips/include/asm/dma.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/mips/include/asm/dma.h b/arch/mips/include/asm/dma.h index e0b4689172..49eeaac1a2 100644 --- a/arch/mips/include/asm/dma.h +++ b/arch/mips/include/asm/dma.h @@ -6,6 +6,18 @@ #ifndef __ASM_DMA_H #define __ASM_DMA_H +#include +#include +#include + +#define dma_alloc dma_alloc +static inline void *dma_alloc(size_t size) +{ + unsigned long max_linesz = max(current_cpu_data.dcache.linesz, + current_cpu_data.scache.linesz); + return xmemalign(max_linesz, ALIGN(size, max_linesz)); +} + #include "asm/dma-mapping.h" #endif /* __ASM_DMA_H */ -- 2.30.2