[PATCH v1 1/2] ARM: i.MX6 MMDC: Add register offset comments to struct

[PATCH v1 1/2] ARM: i.MX6 MMDC: Add register offset comments to struct

[Oleksij Rempel]

From: Sascha Hauer <s.hauer@pengutronix.de>

Lying structs over registers is a U-Boot paradigm I'll never understand.
The only thing it does is to successfully prevent a reader from
knowing/verifying the register offset without counting struct members. I
am currently not in the mood of rewriting this, but at least add some
comments with the register offsets as a debugging aid.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 include/mach/imx/imx6-mmdc.h | 100 +++++++++++++++++------------------
 1 file changed, 50 insertions(+), 50 deletions(-)

diff --git a/include/mach/imx/imx6-mmdc.h b/include/mach/imx/imx6-mmdc.h
index bf8d41fe58..1df87bf6bd 100644
--- a/include/mach/imx/imx6-mmdc.h
+++ b/include/mach/imx/imx6-mmdc.h
@@ -145,60 +145,60 @@ struct mx6sx_iomux_grp_regs {
  */
 #define MX6DQ_IOM_DDR_BASE      0x020e0500
 struct mx6dq_iomux_ddr_regs {
-	u32 res1[3];
-	u32 dram_sdqs5;
-	u32 dram_dqm5;
-	u32 dram_dqm4;
-	u32 dram_sdqs4;
-	u32 dram_sdqs3;
-	u32 dram_dqm3;
-	u32 dram_sdqs2;
-	u32 dram_dqm2;
-	u32 res2[16];
-	u32 dram_cas;
-	u32 res3[2];
-	u32 dram_ras;
-	u32 dram_reset;
-	u32 res4[2];
-	u32 dram_sdclk_0;
-	u32 dram_sdba2;
-	u32 dram_sdcke0;
-	u32 dram_sdclk_1;
-	u32 dram_sdcke1;
-	u32 dram_sdodt0;
-	u32 dram_sdodt1;
-	u32 res5;
-	u32 dram_sdqs0;
-	u32 dram_dqm0;
-	u32 dram_sdqs1;
-	u32 dram_dqm1;
-	u32 dram_sdqs6;
-	u32 dram_dqm6;
-	u32 dram_sdqs7;
-	u32 dram_dqm7;
+	u32 res1[3];		/* 0x020e0500 */
+	u32 dram_sdqs5;		/* 0x020e050c */
+	u32 dram_dqm5;		/* 0x020e0510 */
+	u32 dram_dqm4;		/* 0x020e0514 */
+	u32 dram_sdqs4;		/* 0x020e0518 */
+	u32 dram_sdqs3;		/* 0x020e051c */
+	u32 dram_dqm3;		/* 0x020e0520 */
+	u32 dram_sdqs2;		/* 0x020e0524 */
+	u32 dram_dqm2;		/* 0x020e0528 */
+	u32 res2[16];		/* 0x020e052c */
+	u32 dram_cas;		/* 0x020e056c */
+	u32 res3[2];		/* 0x020e0570 */
+	u32 dram_ras;		/* 0x020e0578 */
+	u32 dram_reset;		/* 0x020e057c */
+	u32 res4[2];		/* 0x020e0580 */
+	u32 dram_sdclk_0;	/* 0x020e0588 */
+	u32 dram_sdba2;		/* 0x020e058c */
+	u32 dram_sdcke0;	/* 0x020e0590 */
+	u32 dram_sdclk_1;	/* 0x020e0594 */
+	u32 dram_sdcke1;	/* 0x020e0598 */
+	u32 dram_sdodt0;	/* 0x020e059c */
+	u32 dram_sdodt1;	/* 0x020e05a0 */
+	u32 res5;		/* 0x020e05a4 */
+	u32 dram_sdqs0;		/* 0x020e05a8 */
+	u32 dram_dqm0;		/* 0x020e05ac */
+	u32 dram_sdqs1;		/* 0x020e05b0 */
+	u32 dram_dqm1;		/* 0x020e05b4 */
+	u32 dram_sdqs6;		/* 0x020e05b8 */
+	u32 dram_dqm6;		/* 0x020e05bc */
+	u32 dram_sdqs7;		/* 0x020e05c0 */
+	u32 dram_dqm7;		/* 0x020e05c4 */
 };
 
 #define MX6DQ_IOM_GRP_BASE      0x020e0700
 struct mx6dq_iomux_grp_regs {
-	u32 res1[18];
-	u32 grp_b7ds;
-	u32 grp_addds;
-	u32 grp_ddrmode_ctl;
-	u32 res2;
-	u32 grp_ddrpke;
-	u32 res3[6];
-	u32 grp_ddrmode;
-	u32 res4[3];
-	u32 grp_b0ds;
-	u32 grp_b1ds;
-	u32 grp_ctlds;
-	u32 res5;
-	u32 grp_b2ds;
-	u32 grp_ddr_type;
-	u32 grp_b3ds;
-	u32 grp_b4ds;
-	u32 grp_b5ds;
-	u32 grp_b6ds;
+	u32 res1[18];		/* 0x020e0700 */
+	u32 grp_b7ds;		/* 0x020e0748 */
+	u32 grp_addds;		/* 0x020e074c */
+	u32 grp_ddrmode_ctl;	/* 0x020e0750 */
+	u32 res2;		/* 0x020e0754 */
+	u32 grp_ddrpke;		/* 0x020e0758 */
+	u32 res3[6];		/* 0x020e075c */
+	u32 grp_ddrmode;	/* 0x020e0774 */
+	u32 res4[3];		/* 0x020e0778 */
+	u32 grp_b0ds;		/* 0x020e0784 */
+	u32 grp_b1ds;		/* 0x020e0788 */
+	u32 grp_ctlds;		/* 0x020e078c */
+	u32 res5;		/* 0x020e0790 */
+	u32 grp_b2ds;		/* 0x020e0794 */
+	u32 grp_ddr_type;	/* 0x020e0798 */
+	u32 grp_b3ds;		/* 0x020e079c */
+	u32 grp_b4ds;		/* 0x020e07a0 */
+	u32 grp_b5ds;		/* 0x020e07a4 */
+	u32 grp_b6ds;		/* 0x020e07a8 */
 };
 
 #define MX6SDL_IOM_DDR_BASE     0x020e0400
-- 
2.39.2

[PATCH v1 2/2] ARM: skov-imx6: Remove unused board variants

[Oleksij Rempel]

From: Sascha Hauer <s.hauer@pengutronix.de>

The board variants 12 and 18 are no longer used. Remove them.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/boards/skov-imx6/lowlevel.c | 136 ---------------------------
 1 file changed, 136 deletions(-)

diff --git a/arch/arm/boards/skov-imx6/lowlevel.c b/arch/arm/boards/skov-imx6/lowlevel.c
index c9a695ced4..16809dd4a6 100644
--- a/arch/arm/boards/skov-imx6/lowlevel.c
+++ b/arch/arm/boards/skov-imx6/lowlevel.c
@@ -28,122 +28,6 @@ static void __udelay(int us)
 
 /* ------------------------------------------------------------------------ */
 
-/*
- * Micron MT41K512M16HA-125 IT:E ->  8 GBit = 64 Meg x 16 x 8 banks
- *
- * Speed Grade   Data Rate (MT/s)  tRCD-tRP-CL   tRCD(ns)  tRP(ns)  CL(ns)
- *    -125          1600            11-11-11      13.75     13.75   13.75
- *               (=800 MHz)
- *
- * Memory configuration used by variant:
- * - "Max Performance", 64 bit data bus, 1066 MHz, 4 GiB memory
- */
-static const struct mx6_ddr3_cfg skov_imx6_cfg_4x512Mb_1066MHz = {
-	.mem_speed = 1066,
-	.density = 8, /* GiBit */
-	.width = 16, /* 16 bit data per device */
-	.banks = 8,
-	.rowaddr = 16, /* 64 k */
-	.coladdr = 10, /* 1 k */
-	.pagesz = 2, /* [kiB] */
-	.trcd = 1375, /* 13.75 ns = 11 clocks @ 1.6 GHz */
-	.trcmin = 4875, /* 48.75 ns = 39 clocks @ 1.6 GHz */
-	.trasmin = 3500, /* 35 ns = 28 clocks @ 1.6 GHz */
-	.SRT = 0,
-};
-
-static const struct mx6_ddr_sysinfo skov_imx6_sysinfo_4x512Mb_1066MHz = {
-	.dsize = 2, /* 64 bit wide = 4 devices, 16 bit each */
-	.cs_density = 32, /* four 8 GBit devices connected */
-	.ncs = 1, /* one CS line for all devices */
-	.cs1_mirror = 1, /* TODO */
-	.bi_on = 1, /* TODO */
-	.rtt_nom = 1, /* MX6_MMDC_P0_MPODTCTRL -> 0x00022227 */
-	.rtt_wr = 0, /* is LW_EN is 0 in their code */
-	.ralat = 5, /* TODO */
-	.walat = 1, /* TODO */
-	.mif3_mode = 3, /* TODO */
-	.rst_to_cke = 0x23, /* used in their code as well */
-	.sde_to_rst = 0x10, /* used in their code as well */
-	.pd_fast_exit = 0, /* TODO */
-};
-
-static const struct mx6_mmdc_calibration skov_imx6_calib_4x512Mb_1066MHz = {
-	.p0_mpwldectrl0 = 0x001a0017,
-	.p0_mpwldectrl1 = 0x001F001F,
-	.p0_mpdgctrl0 = 0x43040319,
-	.p0_mpdgctrl1 = 0x03040279,
-	.p0_mprddlctl = 0x4d434248,
-	.p0_mpwrdlctl = 0x34424543,
-
-	.p1_mpwldectrl0 = 0x00170027,
-	.p1_mpwldectrl1 = 0x000a001f,
-	.p1_mpdgctrl0 = 0x43040321,
-	.p1_mpdgctrl1 = 0x03030251,
-	.p1_mprddlctl = 0x42413c4d,
-	.p1_mpwrdlctl = 0x49324933,
-};
-
-/* ------------------------------------------------------------------------ */
-
-/*
- * Micron MT41K256M16HA-125 IT:E ->  4 GBit = 32 Meg x 16 x 8 banks
- *
- * Speed Grade   Data Rate (MT/s)  tRCD-tRP-CL   tRCD(ns)  tRP(ns)  CL(ns)
- *    -125          1600            11-11-11      13.75     13.75   13.75
- *               (=800 MHz)
- *
- * Memory configuration used by variant:
- * - "Max Performance", 64 bit data bus, 1066 MHz, 2 GiB memory
- */
-static const struct mx6_ddr3_cfg skov_imx6_cfg_4x256Mb_1066MHz = {
-	.mem_speed = 1066,
-	.density = 4, /* GiBit */
-	.width = 16, /* 16 bit data per device */
-	.banks = 8,
-	.rowaddr = 15, /* 32 k */
-	.coladdr = 10, /* 1 k */
-	.pagesz = 2, /* [kiB] */
-	.trcd = 1375, /* 13.75 ns = 11 clocks @ 1.6 GHz */
-	.trcmin = 4875, /* 48.75 ns = 39 clocks @ 1.6 GHz */
-	.trasmin = 3500, /* 35 ns = 28 clocks @ 1.6 GHz */
-	.SRT = 0,
-};
-
-static const struct mx6_ddr_sysinfo skov_imx6_sysinfo_4x256Mb_1066MHz = {
-	.dsize = 2, /* 64 bit wide = 4 devices, 16 bit each */
-	.cs_density = 16, /* four 4 GBit devices connected */
-	.ncs = 1, /* one CS line for all devices */
-	.cs1_mirror = 1, /* TODO */
-	.bi_on = 1, /* TODO */
-	.rtt_nom = 1, /* MX6_MMDC_P0_MPODTCTRL -> 0x00022227 */
-	.rtt_wr = 0, /* is LW_EN is 0 in their code */
-	.ralat = 5, /* TODO */
-	.walat = 1, /* TODO */
-	.mif3_mode = 3, /* TODO */
-	.rst_to_cke = 0x23, /* used in their code as well */
-	.sde_to_rst = 0x10, /* used in their code as well */
-	.pd_fast_exit = 0, /* TODO */
-};
-
-static const struct mx6_mmdc_calibration skov_imx6_calib_4x256Mb_1066MHz = {
-	.p0_mpwldectrl0 = 0x001a0017,
-	.p0_mpwldectrl1 = 0x001F001F,
-	.p0_mpdgctrl0 = 0x43040319,
-	.p0_mpdgctrl1 = 0x03040279,
-	.p0_mprddlctl = 0x4d434248,
-	.p0_mpwrdlctl = 0x34424543,
-
-	.p1_mpwldectrl0 = 0x00170027,
-	.p1_mpwldectrl1 = 0x000a001f,
-	.p1_mpdgctrl0 = 0x43040321,
-	.p1_mpdgctrl1 = 0x03030251,
-	.p1_mprddlctl = 0x42413c4d,
-	.p1_mpwrdlctl = 0x49324933,
-};
-
-/* ------------------------------------------------------------------------ */
-
 /*
  * Micron MT41K128M16JT-125 IT:K ->  2 GBit = 16 Meg x 16 x 8 banks
  *
@@ -530,26 +414,6 @@ static void skov_imx6_init(int cpu_type, unsigned board_variant)
 	int instance;
 
 	switch (board_variant) {
-	case 12: /* P2 i.MX6Q, max performance */
-		if (cpu_type != IMX6_CPUTYPE_IMX6Q) {
-			pr_err("Invalid SoC! i.MX6Q expected\n");
-			return;
-		}
-		pr_debug("Initializing a P2 max performance system...\n");
-		spl_imx6q_dram_init(&skov_imx6_sysinfo_4x256Mb_1066MHz,
-					&skov_imx6_calib_4x256Mb_1066MHz,
-					&skov_imx6_cfg_4x256Mb_1066MHz);
-		break;
-	case 18: /* i.MX6Q+ */
-		if (cpu_type != IMX6_CPUTYPE_IMX6Q) {
-			pr_err("Invalid SoC! i.MX6Q expected\n");
-			return;
-		}
-		pr_debug("Initializing board variant 18\n");
-		spl_imx6q_dram_init(&skov_imx6_sysinfo_4x512Mb_1066MHz,
-					&skov_imx6_calib_4x512Mb_1066MHz,
-					&skov_imx6_cfg_4x512Mb_1066MHz);
-		break;
 	case 19: /* i.MX6S "Solo_R512M_F2G" */
 		if (cpu_type != IMX6_CPUTYPE_IMX6S) {
 			pr_err("Invalid SoC! i.MX6S expected\n");
-- 
2.39.2

Re: [PATCH v1 1/2] ARM: i.MX6 MMDC: Add register offset comments to struct

[Sascha Hauer]

On Thu, Sep 28, 2023 at 02:11:05PM +0200, Oleksij Rempel wrote:
> From: Sascha Hauer <s.hauer@pengutronix.de>
> 
> Lying structs over registers is a U-Boot paradigm I'll never understand.
> The only thing it does is to successfully prevent a reader from
> knowing/verifying the register offset without counting struct members. I
> am currently not in the mood of rewriting this, but at least add some
> comments with the register offsets as a debugging aid.
> 
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
>  include/mach/imx/imx6-mmdc.h | 100 +++++++++++++++++------------------
>  1 file changed, 50 insertions(+), 50 deletions(-)

Applied, thanks

Sascha

> 
> diff --git a/include/mach/imx/imx6-mmdc.h b/include/mach/imx/imx6-mmdc.h
> index bf8d41fe58..1df87bf6bd 100644
> --- a/include/mach/imx/imx6-mmdc.h
> +++ b/include/mach/imx/imx6-mmdc.h
> @@ -145,60 +145,60 @@ struct mx6sx_iomux_grp_regs {
>   */
>  #define MX6DQ_IOM_DDR_BASE      0x020e0500
>  struct mx6dq_iomux_ddr_regs {
> -	u32 res1[3];
> -	u32 dram_sdqs5;
> -	u32 dram_dqm5;
> -	u32 dram_dqm4;
> -	u32 dram_sdqs4;
> -	u32 dram_sdqs3;
> -	u32 dram_dqm3;
> -	u32 dram_sdqs2;
> -	u32 dram_dqm2;
> -	u32 res2[16];
> -	u32 dram_cas;
> -	u32 res3[2];
> -	u32 dram_ras;
> -	u32 dram_reset;
> -	u32 res4[2];
> -	u32 dram_sdclk_0;
> -	u32 dram_sdba2;
> -	u32 dram_sdcke0;
> -	u32 dram_sdclk_1;
> -	u32 dram_sdcke1;
> -	u32 dram_sdodt0;
> -	u32 dram_sdodt1;
> -	u32 res5;
> -	u32 dram_sdqs0;
> -	u32 dram_dqm0;
> -	u32 dram_sdqs1;
> -	u32 dram_dqm1;
> -	u32 dram_sdqs6;
> -	u32 dram_dqm6;
> -	u32 dram_sdqs7;
> -	u32 dram_dqm7;
> +	u32 res1[3];		/* 0x020e0500 */
> +	u32 dram_sdqs5;		/* 0x020e050c */
> +	u32 dram_dqm5;		/* 0x020e0510 */
> +	u32 dram_dqm4;		/* 0x020e0514 */
> +	u32 dram_sdqs4;		/* 0x020e0518 */
> +	u32 dram_sdqs3;		/* 0x020e051c */
> +	u32 dram_dqm3;		/* 0x020e0520 */
> +	u32 dram_sdqs2;		/* 0x020e0524 */
> +	u32 dram_dqm2;		/* 0x020e0528 */
> +	u32 res2[16];		/* 0x020e052c */
> +	u32 dram_cas;		/* 0x020e056c */
> +	u32 res3[2];		/* 0x020e0570 */
> +	u32 dram_ras;		/* 0x020e0578 */
> +	u32 dram_reset;		/* 0x020e057c */
> +	u32 res4[2];		/* 0x020e0580 */
> +	u32 dram_sdclk_0;	/* 0x020e0588 */
> +	u32 dram_sdba2;		/* 0x020e058c */
> +	u32 dram_sdcke0;	/* 0x020e0590 */
> +	u32 dram_sdclk_1;	/* 0x020e0594 */
> +	u32 dram_sdcke1;	/* 0x020e0598 */
> +	u32 dram_sdodt0;	/* 0x020e059c */
> +	u32 dram_sdodt1;	/* 0x020e05a0 */
> +	u32 res5;		/* 0x020e05a4 */
> +	u32 dram_sdqs0;		/* 0x020e05a8 */
> +	u32 dram_dqm0;		/* 0x020e05ac */
> +	u32 dram_sdqs1;		/* 0x020e05b0 */
> +	u32 dram_dqm1;		/* 0x020e05b4 */
> +	u32 dram_sdqs6;		/* 0x020e05b8 */
> +	u32 dram_dqm6;		/* 0x020e05bc */
> +	u32 dram_sdqs7;		/* 0x020e05c0 */
> +	u32 dram_dqm7;		/* 0x020e05c4 */
>  };
>  
>  #define MX6DQ_IOM_GRP_BASE      0x020e0700
>  struct mx6dq_iomux_grp_regs {
> -	u32 res1[18];
> -	u32 grp_b7ds;
> -	u32 grp_addds;
> -	u32 grp_ddrmode_ctl;
> -	u32 res2;
> -	u32 grp_ddrpke;
> -	u32 res3[6];
> -	u32 grp_ddrmode;
> -	u32 res4[3];
> -	u32 grp_b0ds;
> -	u32 grp_b1ds;
> -	u32 grp_ctlds;
> -	u32 res5;
> -	u32 grp_b2ds;
> -	u32 grp_ddr_type;
> -	u32 grp_b3ds;
> -	u32 grp_b4ds;
> -	u32 grp_b5ds;
> -	u32 grp_b6ds;
> +	u32 res1[18];		/* 0x020e0700 */
> +	u32 grp_b7ds;		/* 0x020e0748 */
> +	u32 grp_addds;		/* 0x020e074c */
> +	u32 grp_ddrmode_ctl;	/* 0x020e0750 */
> +	u32 res2;		/* 0x020e0754 */
> +	u32 grp_ddrpke;		/* 0x020e0758 */
> +	u32 res3[6];		/* 0x020e075c */
> +	u32 grp_ddrmode;	/* 0x020e0774 */
> +	u32 res4[3];		/* 0x020e0778 */
> +	u32 grp_b0ds;		/* 0x020e0784 */
> +	u32 grp_b1ds;		/* 0x020e0788 */
> +	u32 grp_ctlds;		/* 0x020e078c */
> +	u32 res5;		/* 0x020e0790 */
> +	u32 grp_b2ds;		/* 0x020e0794 */
> +	u32 grp_ddr_type;	/* 0x020e0798 */
> +	u32 grp_b3ds;		/* 0x020e079c */
> +	u32 grp_b4ds;		/* 0x020e07a0 */
> +	u32 grp_b5ds;		/* 0x020e07a4 */
> +	u32 grp_b6ds;		/* 0x020e07a8 */
>  };
>  
>  #define MX6SDL_IOM_DDR_BASE     0x020e0400
> -- 
> 2.39.2
> 
> 

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |