* [PATCH 01/19] soc/fsl: import immap_lsch3 from U-Boot
2024-01-04 14:17 [PATCH 00/19] ARM: add Layerscape LS1028a support Sascha Hauer
@ 2024-01-04 14:17 ` Sascha Hauer
2024-01-04 14:17 ` [PATCH 02/19] soc/fsl/immap_lsch2.h: cleanup Sascha Hauer
` (17 subsequent siblings)
18 siblings, 0 replies; 25+ messages in thread
From: Sascha Hauer @ 2024-01-04 14:17 UTC (permalink / raw)
To: Barebox List
For upcoming LS1028a support we'll need immap_lsch3.h. Import
it from U-Boot v2023.10-rc4.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
include/soc/fsl/immap_lsch3.h | 187 ++++++++++++++++++++++++++++++++++
1 file changed, 187 insertions(+)
create mode 100644 include/soc/fsl/immap_lsch3.h
diff --git a/include/soc/fsl/immap_lsch3.h b/include/soc/fsl/immap_lsch3.h
new file mode 100644
index 0000000000..f2fdb7dfb3
--- /dev/null
+++ b/include/soc/fsl/immap_lsch3.h
@@ -0,0 +1,187 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * LayerScape Internal Memory Map
+ *
+ * Copyright 2017-2020 NXP
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __ARCH_FSL_LSCH3_IMMAP_H_
+#define __ARCH_FSL_LSCH3_IMMAP_H_
+
+#define LSCH3_IMMR 0x01000000
+
+// LSCH3_2: ls1028a, lx2162a, lx2160a
+#define LSCH3_DDR_ADDR (LSCH3_IMMR + 0x00080000)
+#define LSCH3_DDR2_ADDR (LSCH3_IMMR + 0x00090000)
+#define LSCH3_DDR3_ADDR 0x08210000
+#define LSCH3_GUTS_ADDR (LSCH3_IMMR + 0x00E00000)
+#define LSCH3_PMU_ADDR (LSCH3_IMMR + 0x00E30000)
+#define LSCH3_RST_ADDR_LX21XXA (LSCH3_IMMR + 0x00e88180)
+#define LSCH3_RST_ADDR (LSCH3_IMMR + 0x00E60000)
+#define LSCH3_CH3_CLK_GRPA_ADDR (LSCH3_IMMR + 0x00300000)
+#define LSCH3_CH3_CLK_GRPB_ADDR (LSCH3_IMMR + 0x00310000)
+#define LSCH3_CH3_CLK_CTRL_ADDR (LSCH3_IMMR + 0x00370000)
+#define LSCH3_QSPI_ADDR_LSCH3 (LSCH3_IMMR + 0x010c0000)
+#define LSCH3_FSPI_ADDR (LSCH3_IMMR + 0x010c0000)
+#define LSCH3_ESDHC1_BASE_ADDR (LSCH3_IMMR + 0x01140000)
+#define LSCH3_ESDHC2_BASE_ADDR (LSCH3_IMMR + 0x01150000)
+#define LSCH3_IFC_ADDR (LSCH3_IMMR + 0x01240000)
+#define LSCH3_NS16550_COM1 (LSCH3_IMMR + 0x011C0500)
+#define LSCH3_NS16550_COM2 (LSCH3_IMMR + 0x011C0600)
+#define LSCH3_TIMER_ADDR (LSCH3_IMMR + 0x013e0000)
+#define LSCH3_CCI400_ADDR (LSCH3_IMMR + 0x03090000)
+#define LSCH3_PMU_CLTBENR (LSCH3_PMU_ADDR + 0x18A0)
+#define LSCH3_PCTBENR_OFFSET (LSCH3_PMU_ADDR + 0x8A0)
+#define LSCH3_SVR (LSCH3_GUTS_ADDR + 0xA4)
+
+#define LSCH3_WRIOP1_ADDR (LSCH3_IMMR + 0x7B80000)
+#define LSCH3_WRIOP1_MDIO1 (LSCH3_WRIOP1_ADDR + 0x16000)
+#define LSCH3_WRIOP1_MDIO2 (LSCH3_WRIOP1_ADDR + 0x17000)
+#define LSCH3_SERDES_ADDR (LSCH3_IMMR + 0xEA0000)
+
+#define LSCH3_DCSR_DDR_ADDR 0x70012c000ULL
+#define LSCH3_DCSR_DDR2_ADDR 0x70012d000ULL
+#define LSCH3_DCSR_DDR3_ADDR 0x700132000ULL
+
+#define LSCH3_I2C1_BASE_ADDR (LSCH3_IMMR + 0x01000000)
+#define LSCH3_I2C2_BASE_ADDR (LSCH3_IMMR + 0x01010000)
+#define LSCH3_I2C3_BASE_ADDR (LSCH3_IMMR + 0x01020000)
+#define LSCH3_I2C4_BASE_ADDR (LSCH3_IMMR + 0x01030000)
+#define LSCH3_I2C5_BASE_ADDR (LSCH3_IMMR + 0x01040000)
+#define LSCH3_I2C6_BASE_ADDR (LSCH3_IMMR + 0x01050000)
+#define LSCH3_I2C7_BASE_ADDR (LSCH3_IMMR + 0x01060000)
+#define LSCH3_I2C8_BASE_ADDR (LSCH3_IMMR + 0x01070000)
+
+/* EDMA */
+#define LSCH3_EDMA_BASE_ADDR (LSCH3_IMMR + 0x012c0000)
+
+/* MMU 500 */
+#define LSCH3_SMMU_SCR0 (SMMU_BASE + 0x0)
+#define LSCH3_SMMU_SCR1 (SMMU_BASE + 0x4)
+#define LSCH3_SMMU_SCR2 (SMMU_BASE + 0x8)
+#define LSCH3_SMMU_SACR (SMMU_BASE + 0x10)
+#define LSCH3_SMMU_IDR0 (SMMU_BASE + 0x20)
+#define LSCH3_SMMU_IDR1 (SMMU_BASE + 0x24)
+
+#define LSCH3_SMMU_NSCR0 (SMMU_BASE + 0x400)
+#define LSCH3_SMMU_NSCR2 (SMMU_BASE + 0x408)
+#define LSCH3_SMMU_NSACR (SMMU_BASE + 0x410)
+
+/* Device Configuration */
+#define LSCH3_DCFG_BASE 0x01e00000
+#define LSCH3_DCFG_PORSR1 0x000
+#define LSCH3_DCFG_PORSR1_RCW_SRC 0xff800000
+#define LSCH3_DCFG_PORSR1_RCW_SRC_SDHC1 0x04000000
+#define LSCH3_DCFG_PORSR1_RCW_SRC_SDHC2 0x04800000
+#define LSCH3_DCFG_PORSR1_RCW_SRC_I2C 0x05000000
+#define LSCH3_DCFG_PORSR1_RCW_SRC_FSPI_NOR 0x07800000
+#define LSCH3_DCFG_PORSR1_RCW_SRC_NOR 0x12f00000
+#define LSCH3_DCFG_RCWSR12 0x12c
+#define LSCH3_DCFG_RCWSR12_SDHC_SHIFT 24
+#define LSCH3_DCFG_RCWSR12_SDHC_MASK 0x7
+#define LSCH3_DCFG_RCWSR13 0x130
+#define LSCH3_DCFG_RCWSR13_SDHC_SHIFT 3
+#define LSCH3_DCFG_RCWSR13_SDHC_MASK 0x7
+#define LSCH3_DCFG_RCWSR13_DSPI (0 << 8)
+#define LSCH3_DCFG_RCWSR15 0x138
+#define LSCH3_DCFG_RCWSR15_IFCGRPABASE_QSPI 0x3
+
+#define LSCH3_DCFG_DCSR_BASE 0X700100000ULL
+#define LSCH3_DCFG_DCSR_PORCR1 0x000
+
+/* Supplemental Configuration */
+#define LSCH3_SCFG_BASE 0x01fc0000
+#define LSCH3_SCFG_USB3PRM1CR 0x000
+#define LSCH3_SCFG_USB3PRM1CR_INIT 0x27672b2a
+#define LSCH3_SCFG_USB_TXVREFTUNE 0x9
+#define LSCH3_SCFG_USB_SQRXTUNE_MASK 0x7
+#define LSCH3_SCFG_QSPICLKCTLR 0x10
+
+#define LSCH3_DCSR_BASE 0x700000000ULL
+#define LSCH3_DCSR_USB_PHY1 0x4600000
+#define LSCH3_DCSR_USB_PHY2 0x4610000
+#define LSCH3_DCSR_USB_PHY_RX_OVRD_IN_HI 0x200C
+#define LSCH3_DCSR_USB_IOCR1 0x108004
+#define LSCH3_DCSR_USB_PCSTXSWINGFULL 0x71
+
+#ifndef __ASSEMBLY__
+
+/* Global Utilities Block */
+struct lsch3_ccsr_gur {
+ u32 porsr1; /* POR status 1 */
+ u32 porsr2; /* POR status 2 */
+ u8 res_008[0x20-0x8];
+ u32 gpporcr1; /* General-purpose POR configuration */
+ u32 gpporcr2; /* General-purpose POR configuration 2 */
+ u32 gpporcr3;
+ u32 gpporcr4;
+ u8 res_030[0x60-0x30];
+ u32 dcfg_fusesr; /* Fuse status register */
+ u8 res_064[0x70-0x64];
+ u32 devdisr; /* Device disable control 1 */
+ u32 devdisr2; /* Device disable control 2 */
+ u32 devdisr3; /* Device disable control 3 */
+ u32 devdisr4; /* Device disable control 4 */
+ u32 devdisr5; /* Device disable control 5 */
+ u32 devdisr6; /* Device disable control 6 */
+ u8 res_088[0x94-0x88];
+ u32 coredisr; /* Device disable control 7 */
+ u8 res_098[0xa0-0x98];
+ u32 pvr; /* Processor version */
+ u32 svr; /* System version */
+ u8 res_0a8[0x100-0xa8];
+ u32 rcwsr[30]; /* Reset control word status */
+ u8 res_178[0x200-0x178];
+ u32 scratchrw[16]; /* Scratch Read/Write */
+ u8 res_240[0x300-0x240];
+ u32 scratchw1r[4]; /* Scratch Read (Write once) */
+ u8 res_310[0x400-0x310];
+ u32 bootlocptrl; /* Boot location pointer low-order addr */
+ u32 bootlocptrh; /* Boot location pointer high-order addr */
+ u8 res_408[0x520-0x408];
+ u32 usb1_amqr;
+ u32 usb2_amqr;
+ u8 res_528[0x530-0x528]; /* add more registers when needed */
+ u32 sdmm1_amqr;
+ u32 sdmm2_amqr;
+ u8 res_538[0x550 - 0x538]; /* add more registers when needed */
+ u32 sata1_amqr;
+ u32 sata2_amqr;
+ u32 sata3_amqr;
+ u32 sata4_amqr;
+ u8 res_560[0x570 - 0x560]; /* add more registers when needed */
+ u32 misc1_amqr;
+ u8 res_574[0x590-0x574]; /* add more registers when needed */
+ u32 spare1_amqr;
+ u32 spare2_amqr;
+ u32 spare3_amqr;
+ u8 res_59c[0x620 - 0x59c]; /* add more registers when needed */
+ u32 gencr[7]; /* General Control Registers */
+ u8 res_63c[0x640-0x63c]; /* add more registers when needed */
+ u32 cgensr1; /* Core General Status Register */
+ u8 res_644[0x660-0x644]; /* add more registers when needed */
+ u32 cgencr1; /* Core General Control Register */
+ u8 res_664[0x740-0x664]; /* add more registers when needed */
+ u32 tp_ityp[64]; /* Topology Initiator Type Register */
+ struct {
+ u32 upper;
+ u32 lower;
+ } tp_cluster[4]; /* Core cluster n Topology Register */
+ u8 res_864[0x920-0x864]; /* add more registers when needed */
+ u32 ioqoscr[8]; /*I/O Quality of Services Register */
+ u32 uccr;
+ u8 res_944[0x960-0x944]; /* add more registers when needed */
+ u32 ftmcr;
+ u8 res_964[0x990-0x964]; /* add more registers when needed */
+ u32 coredisablesr;
+ u8 res_994[0xa00-0x994]; /* add more registers when needed */
+ u32 sdbgcr; /*Secure Debug Confifuration Register */
+ u8 res_a04[0xbf8-0xa04]; /* add more registers when needed */
+ u32 ipbrr1;
+ u32 ipbrr2;
+ u8 res_858[0x1000-0xc00];
+};
+
+#endif /*__ASSEMBLY__ */
+#endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */
--
2.39.2
^ permalink raw reply [flat|nested] 25+ messages in thread* [PATCH 02/19] soc/fsl/immap_lsch2.h: cleanup
2024-01-04 14:17 [PATCH 00/19] ARM: add Layerscape LS1028a support Sascha Hauer
2024-01-04 14:17 ` [PATCH 01/19] soc/fsl: import immap_lsch3 from U-Boot Sascha Hauer
@ 2024-01-04 14:17 ` Sascha Hauer
2024-01-04 14:17 ` [PATCH 03/19] ARM: layerscape: decide SCFG endianess during runtime Sascha Hauer
` (16 subsequent siblings)
18 siblings, 0 replies; 25+ messages in thread
From: Sascha Hauer @ 2024-01-04 14:17 UTC (permalink / raw)
To: Barebox List
Some values differ between LS1046a and LS1021. Move them directly where
needed so that we can drop the #ifdef SOC_TYPE from immap_lsch2.h
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-layerscape/lowlevel-ls102xa.c | 5 +++++
include/soc/fsl/immap_lsch2.h | 6 ------
2 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-layerscape/lowlevel-ls102xa.c b/arch/arm/mach-layerscape/lowlevel-ls102xa.c
index 259d8866d5..7ea0a5b071 100644
--- a/arch/arm/mach-layerscape/lowlevel-ls102xa.c
+++ b/arch/arm/mach-layerscape/lowlevel-ls102xa.c
@@ -299,6 +299,11 @@ static void fsl_epu_clean(void *epu_base)
out_be32(epu_base + offset, 0);
}
+#define TIMER_COMP_VAL 0xffffffffffffffffull
+#define ARCH_TIMER_CTRL_ENABLE (1 << 0)
+#define SYS_COUNTER_CTRL_ENABLE (1 << 24)
+#define SCFG_QSPI_CLKSEL 0x50100000
+
/* ls102xa_init_lowlevel
* Based on ls1046 and U-boot ls102xa arch_cpu_init
*/
diff --git a/include/soc/fsl/immap_lsch2.h b/include/soc/fsl/immap_lsch2.h
index 62e48ae746..ce840d4223 100644
--- a/include/soc/fsl/immap_lsch2.h
+++ b/include/soc/fsl/immap_lsch2.h
@@ -63,10 +63,6 @@
#define LSCH2_QDMA_BASE_ADDR (LSCH2_IMMR + 0x07380000)
#define LSCH2_EHCI_USB1_ADDR (LSCH2_IMMR + 0x07600000)
-#define TIMER_COMP_VAL 0xffffffffffffffffull
-#define ARCH_TIMER_CTRL_ENABLE (1 << 0)
-#define SYS_COUNTER_CTRL_ENABLE (1 << 24)
-
struct ccsr_gur {
u32 porsr1; /* POR status 1 */
#define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000
@@ -306,13 +302,11 @@ struct ls102xa_ccsr_gur {
#define SCFG_USB_PHY3 0x08510000
#define SCFG_USB_PHY_RX_OVRD_IN_HI 0x200c
#if defined CONFIG_ARCH_LS1046
-#define SCFG_QSPI_CLKSEL 0x40100000
#define USB_PHY_RX_EQ_VAL_1 0x0000
#define USB_PHY_RX_EQ_VAL_2 0x0080
#define USB_PHY_RX_EQ_VAL_3 0x0380
#define USB_PHY_RX_EQ_VAL_4 0x0b80
#elif defined CONFIG_ARCH_LS1021
-#define SCFG_QSPI_CLKSEL 0x50100000
#define USB_PHY_RX_EQ_VAL_1 0x0000
#define USB_PHY_RX_EQ_VAL_2 0x8000
#define USB_PHY_RX_EQ_VAL_3 0x8004
--
2.39.2
^ permalink raw reply [flat|nested] 25+ messages in thread* [PATCH 03/19] ARM: layerscape: decide SCFG endianess during runtime
2024-01-04 14:17 [PATCH 00/19] ARM: add Layerscape LS1028a support Sascha Hauer
2024-01-04 14:17 ` [PATCH 01/19] soc/fsl: import immap_lsch3 from U-Boot Sascha Hauer
2024-01-04 14:17 ` [PATCH 02/19] soc/fsl/immap_lsch2.h: cleanup Sascha Hauer
@ 2024-01-04 14:17 ` Sascha Hauer
2024-01-04 14:17 ` [PATCH 04/19] ARM: layerscape: cleanup erratum_a009007 Sascha Hauer
` (15 subsequent siblings)
18 siblings, 0 replies; 25+ messages in thread
From: Sascha Hauer @ 2024-01-04 14:17 UTC (permalink / raw)
To: Barebox List
SCFG endianess differs between SoCs. Currently supported SoCs have a big
endian SCFG unit, but upcoming LS1028a support has a little endian SCFG.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-layerscape/Makefile | 2 +-
arch/arm/mach-layerscape/errata.c | 4 +-
arch/arm/mach-layerscape/lowlevel-ls102xa.c | 2 +
arch/arm/mach-layerscape/lowlevel-ls1046a.c | 2 +
arch/arm/mach-layerscape/soc.c | 56 +++++++++++++++++++++
include/soc/fsl/scfg.h | 19 +++++++
6 files changed, 81 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/mach-layerscape/soc.c
create mode 100644 include/soc/fsl/scfg.h
diff --git a/arch/arm/mach-layerscape/Makefile b/arch/arm/mach-layerscape/Makefile
index ed55867390..ebb030a1cb 100644
--- a/arch/arm/mach-layerscape/Makefile
+++ b/arch/arm/mach-layerscape/Makefile
@@ -4,7 +4,7 @@ obj- := __dummy__.o
lwl-y += errata.o
lwl-$(CONFIG_ARCH_LS1046) += lowlevel.o lowlevel-ls1046a.o
obj-$(CONFIG_ARCH_LS1046) += icid.o
-obj-pbl-y += boot.o
+obj-pbl-y += boot.o soc.o
pbl-y += xload-qspi.o xload.o
obj-$(CONFIG_ARCH_LAYERSCAPE_PPA) += ppa.o ppa-entry.o
obj-$(CONFIG_BOOTM) += pblimage.o
diff --git a/arch/arm/mach-layerscape/errata.c b/arch/arm/mach-layerscape/errata.c
index 6cb95453e7..e3793b3bcd 100644
--- a/arch/arm/mach-layerscape/errata.c
+++ b/arch/arm/mach-layerscape/errata.c
@@ -6,9 +6,7 @@
#include <asm/system.h>
#include <mach/layerscape/errata.h>
#include <mach/layerscape/lowlevel.h>
-
-#define scfg_clrsetbits32(addr, clear, set) clrsetbits_be32(addr, clear, set)
-#define scfg_clrbits32(addr, clear) clrbits_be32(addr, clear)
+#include <soc/fsl/scfg.h>
static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset)
{
diff --git a/arch/arm/mach-layerscape/lowlevel-ls102xa.c b/arch/arm/mach-layerscape/lowlevel-ls102xa.c
index 7ea0a5b071..440d50282a 100644
--- a/arch/arm/mach-layerscape/lowlevel-ls102xa.c
+++ b/arch/arm/mach-layerscape/lowlevel-ls102xa.c
@@ -14,6 +14,7 @@
#include <mach/layerscape/fsl_epu.h>
#include <soc/fsl/immap_lsch2.h>
#include <soc/fsl/fsl_immap.h>
+#include <soc/fsl/scfg.h>
void udelay(unsigned long usecs)
{
@@ -320,6 +321,7 @@ void ls102xa_init_lowlevel(void)
cortex_a7_lowlevel_init();
arm_cpu_lowlevel_init();
+ scfg_init(SCFG_ENDIANESS_BIG);
init_csu();
writel(SYS_COUNTER_CTRL_ENABLE, LSCH2_SYS_COUNTER_ADDR);
diff --git a/arch/arm/mach-layerscape/lowlevel-ls1046a.c b/arch/arm/mach-layerscape/lowlevel-ls1046a.c
index b2aa839f55..3393dc4903 100644
--- a/arch/arm/mach-layerscape/lowlevel-ls1046a.c
+++ b/arch/arm/mach-layerscape/lowlevel-ls1046a.c
@@ -7,6 +7,7 @@
#include <mach/layerscape/lowlevel.h>
#include <soc/fsl/immap_lsch2.h>
#include <soc/fsl/fsl_immap.h>
+#include <soc/fsl/scfg.h>
enum csu_cslx_access {
CSU_NS_SUP_R = 0x08,
@@ -222,6 +223,7 @@ void ls1046a_init_lowlevel(void)
struct ccsr_cci400 __iomem *cci = IOMEM(LSCH2_CCI400_ADDR);
struct ccsr_scfg *scfg = IOMEM(LSCH2_SCFG_ADDR);
+ scfg_init(SCFG_ENDIANESS_BIG);
init_csu();
ls1046a_init_l2_latency();
set_cntfrq(25000000);
diff --git a/arch/arm/mach-layerscape/soc.c b/arch/arm/mach-layerscape/soc.c
new file mode 100644
index 0000000000..2d9a2b4629
--- /dev/null
+++ b/arch/arm/mach-layerscape/soc.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include <soc/fsl/scfg.h>
+#include <io.h>
+#include <linux/bug.h>
+
+static enum scfg_endianess scfg_endianess = SCFG_ENDIANESS_INVALID;
+
+static void scfg_check_endianess(void)
+{
+ BUG_ON(scfg_endianess == SCFG_ENDIANESS_INVALID);
+}
+
+void scfg_clrsetbits32(void __iomem *addr, u32 clear, u32 set)
+{
+ scfg_check_endianess();
+
+ if (scfg_endianess == SCFG_ENDIANESS_LITTLE)
+ clrsetbits_le32(addr, clear, set);
+ else
+ clrsetbits_be32(addr, clear, set);
+}
+
+void scfg_clrbits32(void __iomem *addr, u32 clear)
+{
+ scfg_check_endianess();
+
+ if (scfg_endianess == SCFG_ENDIANESS_LITTLE)
+ clrbits_le32(addr, clear);
+ else
+ clrbits_be32(addr, clear);
+}
+
+void scfg_setbits32(void __iomem *addr, u32 set)
+{
+ scfg_check_endianess();
+
+ if (scfg_endianess == SCFG_ENDIANESS_LITTLE)
+ setbits_le32(addr, set);
+ else
+ setbits_be32(addr, set);
+}
+
+void scfg_out16(void __iomem *addr, u16 val)
+{
+ scfg_check_endianess();
+
+ if (scfg_endianess == SCFG_ENDIANESS_LITTLE)
+ out_le16(addr, val);
+ else
+ out_be16(addr, val);
+}
+
+void scfg_init(enum scfg_endianess endianess)
+{
+ scfg_endianess = endianess;
+}
diff --git a/include/soc/fsl/scfg.h b/include/soc/fsl/scfg.h
new file mode 100644
index 0000000000..bea184218e
--- /dev/null
+++ b/include/soc/fsl/scfg.h
@@ -0,0 +1,19 @@
+#ifndef __SOC_FSL_SCFG_H
+#define __SOC_FSL_SCFG_H
+
+#include <soc/fsl/scfg.h>
+#include <linux/compiler.h>
+
+enum scfg_endianess {
+ SCFG_ENDIANESS_INVALID,
+ SCFG_ENDIANESS_LITTLE,
+ SCFG_ENDIANESS_BIG,
+};
+
+void scfg_clrsetbits32(void __iomem *addr, u32 clear, u32 set);
+void scfg_clrbits32(void __iomem *addr, u32 clear);
+void scfg_setbits32(void __iomem *addr, u32 set);
+void scfg_out16(void __iomem *addr, u16 val);
+void scfg_init(enum scfg_endianess endianess);
+
+#endif /* __SOC_FSL_SCFG_H */
--
2.39.2
^ permalink raw reply [flat|nested] 25+ messages in thread* [PATCH 04/19] ARM: layerscape: cleanup erratum_a009007
2024-01-04 14:17 [PATCH 00/19] ARM: add Layerscape LS1028a support Sascha Hauer
` (2 preceding siblings ...)
2024-01-04 14:17 ` [PATCH 03/19] ARM: layerscape: decide SCFG endianess during runtime Sascha Hauer
@ 2024-01-04 14:17 ` Sascha Hauer
2024-01-04 14:17 ` [PATCH 05/19] ARM: layerscape: cleanup erratum_a008997 Sascha Hauer
` (14 subsequent siblings)
18 siblings, 0 replies; 25+ messages in thread
From: Sascha Hauer @ 2024-01-04 14:17 UTC (permalink / raw)
To: Barebox List
Drop the generic erratum_a009007_layerscape() function and move the
code into its SoC specific pendants to make the way free for additional
SoCs.
While at it remove the USB_PHY_RX_EQ_VAL_x defines from immap_lsch2.h
to get rid of conflicting defines in that file.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-layerscape/errata.c | 29 +++++++++++++----------------
include/soc/fsl/immap_lsch2.h | 13 +------------
2 files changed, 14 insertions(+), 28 deletions(-)
diff --git a/arch/arm/mach-layerscape/errata.c b/arch/arm/mach-layerscape/errata.c
index e3793b3bcd..8feb98b0f7 100644
--- a/arch/arm/mach-layerscape/errata.c
+++ b/arch/arm/mach-layerscape/errata.c
@@ -30,27 +30,24 @@ static void erratum_a008997_ls1046a(void)
set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3);
}
-#define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
- out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
- out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
- out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
- out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
-
-static void erratum_a009007_layerscape(void)
+static void erratum_a009007(void __iomem *phy, u16 val1, u16 val2, u16 val3, u16 val4)
{
- void __iomem *usb_phy = IOMEM(SCFG_USB_PHY1);
-
- usb_phy = (void __iomem *)SCFG_USB_PHY3;
- PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
+ scfg_out16(phy + SCFG_USB_PHY_RX_OVRD_IN_HI, val1);
+ scfg_out16(phy + SCFG_USB_PHY_RX_OVRD_IN_HI, val2);
+ scfg_out16(phy + SCFG_USB_PHY_RX_OVRD_IN_HI, val3);
+ scfg_out16(phy + SCFG_USB_PHY_RX_OVRD_IN_HI, val4);
}
static void erratum_a009007_ls1046a(void)
{
- void __iomem *usb_phy = IOMEM(SCFG_USB_PHY1);
+ erratum_a009007(IOMEM(SCFG_USB_PHY1), 0x0000, 0x0080, 0x0380, 0x0b80);
+ erratum_a009007(IOMEM(SCFG_USB_PHY2), 0x0000, 0x0080, 0x0380, 0x0b80);
+ erratum_a009007(IOMEM(SCFG_USB_PHY3), 0x0000, 0x0080, 0x0380, 0x0b80);
+}
- PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
- usb_phy = (void __iomem *)SCFG_USB_PHY2;
- PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
+static void erratum_a009007_ls1021a(void)
+{
+ erratum_a009007(IOMEM(SCFG_USB_PHY1), 0x0000, 0x8000, 0x8004, 0x800C);
}
static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset)
@@ -125,7 +122,6 @@ static void layerscape_errata(void)
erratum_a009008_layerscape();
erratum_a009798_layerscape();
erratum_a008997_layerscape();
- erratum_a009007_layerscape();
}
void ls1046a_errata(void)
@@ -140,6 +136,7 @@ void ls1046a_errata(void)
void ls1021a_errata(void)
{
layerscape_errata();
+ erratum_a009007_ls1021a();
erratum_a009008_ls1021a();
}
diff --git a/include/soc/fsl/immap_lsch2.h b/include/soc/fsl/immap_lsch2.h
index ce840d4223..0993fa1cd8 100644
--- a/include/soc/fsl/immap_lsch2.h
+++ b/include/soc/fsl/immap_lsch2.h
@@ -301,17 +301,6 @@ struct ls102xa_ccsr_gur {
#define SCFG_USB_PHY2 0x08500000
#define SCFG_USB_PHY3 0x08510000
#define SCFG_USB_PHY_RX_OVRD_IN_HI 0x200c
-#if defined CONFIG_ARCH_LS1046
-#define USB_PHY_RX_EQ_VAL_1 0x0000
-#define USB_PHY_RX_EQ_VAL_2 0x0080
-#define USB_PHY_RX_EQ_VAL_3 0x0380
-#define USB_PHY_RX_EQ_VAL_4 0x0b80
-#elif defined CONFIG_ARCH_LS1021
-#define USB_PHY_RX_EQ_VAL_1 0x0000
-#define USB_PHY_RX_EQ_VAL_2 0x8000
-#define USB_PHY_RX_EQ_VAL_3 0x8004
-#define USB_PHY_RX_EQ_VAL_4 0x800C
-#endif
#define SCFG_ETSECDMAMCR_LE_BD_FR 0x00000c00
#define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000
@@ -516,4 +505,4 @@ struct ls102xa_ccsr_scfg {
u32 core0sftrstsr;
u32 clusterpmcr;
};
-#endif /* __ARCH_FSL_LSCH2_IMMAP_H__*/
+#endif /* __ARCH_FSL_LSCH2_IMMAP_H__*/
--
2.39.2
^ permalink raw reply [flat|nested] 25+ messages in thread* [PATCH 05/19] ARM: layerscape: cleanup erratum_a008997
2024-01-04 14:17 [PATCH 00/19] ARM: add Layerscape LS1028a support Sascha Hauer
` (3 preceding siblings ...)
2024-01-04 14:17 ` [PATCH 04/19] ARM: layerscape: cleanup erratum_a009007 Sascha Hauer
@ 2024-01-04 14:17 ` Sascha Hauer
2024-01-04 14:17 ` [PATCH 06/19] ARM: layerscape: cleanup erratum_a009798 Sascha Hauer
` (13 subsequent siblings)
18 siblings, 0 replies; 25+ messages in thread
From: Sascha Hauer @ 2024-01-04 14:17 UTC (permalink / raw)
To: Barebox List
Drop generic erratum_a008997_layerscape() and move its implementation
into the SoC specific pendants to make the way free for more SoC
support.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-layerscape/errata.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-layerscape/errata.c b/arch/arm/mach-layerscape/errata.c
index 8feb98b0f7..e3093c07af 100644
--- a/arch/arm/mach-layerscape/errata.c
+++ b/arch/arm/mach-layerscape/errata.c
@@ -15,7 +15,7 @@ static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset)
SCFG_USB_PCSTXSWINGFULL << 9);
}
-static void erratum_a008997_layerscape(void)
+static void erratum_a008997_ls1021a(void)
{
u32 __iomem *scfg = (u32 __iomem *)LSCH2_SCFG_ADDR;
@@ -26,6 +26,7 @@ static void erratum_a008997_ls1046a(void)
{
u32 __iomem *scfg = (u32 __iomem *)LSCH2_SCFG_ADDR;
+ set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1);
set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2);
set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3);
}
@@ -121,7 +122,6 @@ static void layerscape_errata(void)
erratum_a008850_early();
erratum_a009008_layerscape();
erratum_a009798_layerscape();
- erratum_a008997_layerscape();
}
void ls1046a_errata(void)
@@ -136,6 +136,7 @@ void ls1046a_errata(void)
void ls1021a_errata(void)
{
layerscape_errata();
+ erratum_a008997_ls1021a();
erratum_a009007_ls1021a();
erratum_a009008_ls1021a();
}
--
2.39.2
^ permalink raw reply [flat|nested] 25+ messages in thread* [PATCH 06/19] ARM: layerscape: cleanup erratum_a009798
2024-01-04 14:17 [PATCH 00/19] ARM: add Layerscape LS1028a support Sascha Hauer
` (4 preceding siblings ...)
2024-01-04 14:17 ` [PATCH 05/19] ARM: layerscape: cleanup erratum_a008997 Sascha Hauer
@ 2024-01-04 14:17 ` Sascha Hauer
2024-01-04 14:17 ` [PATCH 07/19] ARM: layerscape: drop wrong errata workaround Sascha Hauer
` (12 subsequent siblings)
18 siblings, 0 replies; 25+ messages in thread
From: Sascha Hauer @ 2024-01-04 14:17 UTC (permalink / raw)
To: Barebox List
Drop generic erratum_a009798_layerscape() and move its implementation
into the SoC specific pendants to make the way free for more SoC
support.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-layerscape/errata.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-layerscape/errata.c b/arch/arm/mach-layerscape/errata.c
index e3093c07af..c03c092755 100644
--- a/arch/arm/mach-layerscape/errata.c
+++ b/arch/arm/mach-layerscape/errata.c
@@ -83,7 +83,7 @@ static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset)
scfg_clrbits32(scfg + offset / 4, SCFG_USB_SQRXTUNE_MASK << 23);
}
-static void erratum_a009798_layerscape(void)
+static void erratum_a009798_ls1021a(void)
{
u32 __iomem *scfg = IOMEM(LSCH2_SCFG_ADDR);
@@ -94,6 +94,7 @@ static void erratum_a009798_ls1046a(void)
{
u32 __iomem *scfg = IOMEM(LSCH2_SCFG_ADDR);
+ set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1);
set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2);
set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3);
}
@@ -121,7 +122,6 @@ static void layerscape_errata(void)
{
erratum_a008850_early();
erratum_a009008_layerscape();
- erratum_a009798_layerscape();
}
void ls1046a_errata(void)
@@ -136,6 +136,7 @@ void ls1046a_errata(void)
void ls1021a_errata(void)
{
layerscape_errata();
+ erratum_a009798_ls1021a();
erratum_a008997_ls1021a();
erratum_a009007_ls1021a();
erratum_a009008_ls1021a();
--
2.39.2
^ permalink raw reply [flat|nested] 25+ messages in thread* [PATCH 07/19] ARM: layerscape: drop wrong errata workaround
2024-01-04 14:17 [PATCH 00/19] ARM: add Layerscape LS1028a support Sascha Hauer
` (5 preceding siblings ...)
2024-01-04 14:17 ` [PATCH 06/19] ARM: layerscape: cleanup erratum_a009798 Sascha Hauer
@ 2024-01-04 14:17 ` Sascha Hauer
2024-01-04 14:17 ` [PATCH 08/19] ARM: layerscape: cleanup erratum_a009008 Sascha Hauer
` (11 subsequent siblings)
18 siblings, 0 replies; 25+ messages in thread
From: Sascha Hauer @ 2024-01-04 14:17 UTC (permalink / raw)
To: Barebox List
set_usb_txvreftune() works on the USB Parameter 1 Control Register.
USB Parameter 2 Control Register has a different register layout and
calling set_usb_txvreftune() on it is wrong. Drop the bogus errata
workaround.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-layerscape/errata.c | 8 --------
1 file changed, 8 deletions(-)
diff --git a/arch/arm/mach-layerscape/errata.c b/arch/arm/mach-layerscape/errata.c
index c03c092755..a193c061bc 100644
--- a/arch/arm/mach-layerscape/errata.c
+++ b/arch/arm/mach-layerscape/errata.c
@@ -71,13 +71,6 @@ static void erratum_a009008_ls1046a(void)
set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3);
}
-static void erratum_a009008_ls1021a(void)
-{
- u32 __iomem *scfg = IOMEM(LSCH2_SCFG_ADDR);
-
- set_usb_txvreftune(scfg, SCFG_USB3PRM2CR_USB1);
-}
-
static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset)
{
scfg_clrbits32(scfg + offset / 4, SCFG_USB_SQRXTUNE_MASK << 23);
@@ -139,7 +132,6 @@ void ls1021a_errata(void)
erratum_a009798_ls1021a();
erratum_a008997_ls1021a();
erratum_a009007_ls1021a();
- erratum_a009008_ls1021a();
}
static void erratum_a008850_post(void)
--
2.39.2
^ permalink raw reply [flat|nested] 25+ messages in thread* [PATCH 08/19] ARM: layerscape: cleanup erratum_a009008
2024-01-04 14:17 [PATCH 00/19] ARM: add Layerscape LS1028a support Sascha Hauer
` (6 preceding siblings ...)
2024-01-04 14:17 ` [PATCH 07/19] ARM: layerscape: drop wrong errata workaround Sascha Hauer
@ 2024-01-04 14:17 ` Sascha Hauer
2024-01-29 17:27 ` Uwe Kleine-König
2024-01-04 14:17 ` [PATCH 09/19] ARM: Layerscape: pass base addresses to errata functions Sascha Hauer
` (10 subsequent siblings)
18 siblings, 1 reply; 25+ messages in thread
From: Sascha Hauer @ 2024-01-04 14:17 UTC (permalink / raw)
To: Barebox List
Drop generic erratum_a00i9008_layerscape() and move its implementation
into the SoC specific pendants to make the way free for more SoC
support.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-layerscape/errata.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-layerscape/errata.c b/arch/arm/mach-layerscape/errata.c
index a193c061bc..4a8309167c 100644
--- a/arch/arm/mach-layerscape/errata.c
+++ b/arch/arm/mach-layerscape/errata.c
@@ -56,7 +56,7 @@ static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset)
scfg_clrsetbits32(scfg + offset / 4, 0xf << 6, SCFG_USB_TXVREFTUNE << 6);
}
-static void erratum_a009008_layerscape(void)
+static void erratum_a009008_ls1021a(void)
{
u32 __iomem *scfg = IOMEM(LSCH2_SCFG_ADDR);
@@ -67,6 +67,7 @@ static void erratum_a009008_ls1046a(void)
{
u32 __iomem *scfg = IOMEM(LSCH2_SCFG_ADDR);
+ set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1);
set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2);
set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3);
}
@@ -114,7 +115,6 @@ static void erratum_a008850_early(void)
static void layerscape_errata(void)
{
erratum_a008850_early();
- erratum_a009008_layerscape();
}
void ls1046a_errata(void)
@@ -129,6 +129,7 @@ void ls1046a_errata(void)
void ls1021a_errata(void)
{
layerscape_errata();
+ erratum_a009008_ls1021a();
erratum_a009798_ls1021a();
erratum_a008997_ls1021a();
erratum_a009007_ls1021a();
--
2.39.2
^ permalink raw reply [flat|nested] 25+ messages in thread* [PATCH 09/19] ARM: Layerscape: pass base addresses to errata functions
2024-01-04 14:17 [PATCH 00/19] ARM: add Layerscape LS1028a support Sascha Hauer
` (7 preceding siblings ...)
2024-01-04 14:17 ` [PATCH 08/19] ARM: layerscape: cleanup erratum_a009008 Sascha Hauer
@ 2024-01-04 14:17 ` Sascha Hauer
2024-01-04 14:17 ` [PATCH 10/19] ARM: Layerscape: add layerscape_uart_putc() Sascha Hauer
` (9 subsequent siblings)
18 siblings, 0 replies; 25+ messages in thread
From: Sascha Hauer @ 2024-01-04 14:17 UTC (permalink / raw)
To: Barebox List
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-layerscape/errata.c | 23 ++++++++---------------
1 file changed, 8 insertions(+), 15 deletions(-)
diff --git a/arch/arm/mach-layerscape/errata.c b/arch/arm/mach-layerscape/errata.c
index 4a8309167c..fe0d0ab45e 100644
--- a/arch/arm/mach-layerscape/errata.c
+++ b/arch/arm/mach-layerscape/errata.c
@@ -93,11 +93,10 @@ static void erratum_a009798_ls1046a(void)
set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3);
}
-static void erratum_a008850_early(void)
+static void erratum_a008850_early(struct ccsr_cci400 __iomem *cci,
+ struct ccsr_ddr __iomem *ddr)
{
/* part 1 of 2 */
- struct ccsr_cci400 __iomem *cci = IOMEM(LSCH2_CCI400_ADDR);
- struct ccsr_ddr __iomem *ddr = IOMEM(LSCH2_DDR_ADDR);
/* Skip if running at lower exception level */
#if __LINUX_ARM_ARCH__ > 7
@@ -112,14 +111,9 @@ static void erratum_a008850_early(void)
ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
}
-static void layerscape_errata(void)
-{
- erratum_a008850_early();
-}
-
void ls1046a_errata(void)
{
- layerscape_errata();
+ erratum_a008850_early(IOMEM(LSCH2_CCI400_ADDR), IOMEM(LSCH2_DDR_ADDR));
erratum_a009008_ls1046a();
erratum_a009798_ls1046a();
erratum_a008997_ls1046a();
@@ -128,18 +122,17 @@ void ls1046a_errata(void)
void ls1021a_errata(void)
{
- layerscape_errata();
+ erratum_a008850_early(IOMEM(LSCH2_CCI400_ADDR), IOMEM(LSCH2_DDR_ADDR));
erratum_a009008_ls1021a();
erratum_a009798_ls1021a();
erratum_a008997_ls1021a();
erratum_a009007_ls1021a();
}
-static void erratum_a008850_post(void)
+static void erratum_a008850_post(struct ccsr_cci400 __iomem *cci,
+ struct ccsr_ddr __iomem *ddr)
{
/* part 2 of 2 */
- struct ccsr_cci400 __iomem *cci = IOMEM(LSCH2_CCI400_ADDR);
- struct ccsr_ddr __iomem *ddr = IOMEM(LSCH2_DDR_ADDR);
u32 tmp;
/* Skip if running at lower exception level */
@@ -227,11 +220,11 @@ static void erratum_a009942_check_cpo(void)
void ls1046a_errata_post_ddr(void)
{
- erratum_a008850_post();
+ erratum_a008850_post(IOMEM(LSCH2_CCI400_ADDR), IOMEM(LSCH2_DDR_ADDR));
erratum_a009942_check_cpo();
}
void ls1021a_errata_post_ddr(void)
{
- erratum_a008850_post();
+ erratum_a008850_post(IOMEM(LSCH2_CCI400_ADDR), IOMEM(LSCH2_DDR_ADDR));
}
--
2.39.2
^ permalink raw reply [flat|nested] 25+ messages in thread* [PATCH 10/19] ARM: Layerscape: add layerscape_uart_putc()
2024-01-04 14:17 [PATCH 00/19] ARM: add Layerscape LS1028a support Sascha Hauer
` (8 preceding siblings ...)
2024-01-04 14:17 ` [PATCH 09/19] ARM: Layerscape: pass base addresses to errata functions Sascha Hauer
@ 2024-01-04 14:17 ` Sascha Hauer
2024-01-04 14:17 ` [PATCH 11/19] ARM: layerscape: implement ls1028a errata Sascha Hauer
` (8 subsequent siblings)
18 siblings, 0 replies; 25+ messages in thread
From: Sascha Hauer @ 2024-01-04 14:17 UTC (permalink / raw)
To: Barebox List
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
include/mach/layerscape/debug_ll.h | 23 ++++++++++++++++++++---
1 file changed, 20 insertions(+), 3 deletions(-)
diff --git a/include/mach/layerscape/debug_ll.h b/include/mach/layerscape/debug_ll.h
index 23af0118cc..bdb54ca4b9 100644
--- a/include/mach/layerscape/debug_ll.h
+++ b/include/mach/layerscape/debug_ll.h
@@ -21,24 +21,36 @@ static inline void debug_ll_write_reg(void __iomem *base, int reg, uint8_t val)
#include <debug_ll/ns16550.h>
-static inline void ls1046a_debug_ll_init(void)
+static inline void ls1046a_uart_setup(void *base)
{
- void __iomem *base = IOMEM(LS_UART_BASE(CONFIG_DEBUG_LAYERSCAPE_UART_PORT));
uint16_t divisor;
divisor = debug_ll_ns16550_calc_divisor(300000000);
debug_ll_ns16550_init(base, divisor);
}
-static inline void ls102xa_debug_ll_init(void)
+static inline void ls1046a_debug_ll_init(void)
{
void __iomem *base = IOMEM(LS_UART_BASE(CONFIG_DEBUG_LAYERSCAPE_UART_PORT));
+
+ ls1046a_uart_setup(base);
+}
+
+static inline void ls102xa_uart_setup(void *base)
+{
uint16_t divisor;
divisor = debug_ll_ns16550_calc_divisor(150000000);
debug_ll_ns16550_init(base, divisor);
}
+static inline void ls102xa_debug_ll_init(void)
+{
+ void __iomem *base = IOMEM(LS_UART_BASE(CONFIG_DEBUG_LAYERSCAPE_UART_PORT));
+
+ ls102xa_uart_setup(base);
+}
+
static inline void PUTC_LL(int c)
{
void __iomem *base = IOMEM(LS_UART_BASE(CONFIG_DEBUG_LAYERSCAPE_UART_PORT));
@@ -46,4 +58,9 @@ static inline void PUTC_LL(int c)
debug_ll_ns16550_putc(base, c);
}
+static inline void layerscape_uart_putc(void *base, int c)
+{
+ debug_ll_ns16550_putc(base, c);
+}
+
#endif /* __MACH_LAYERSCAPE_DEBUG_LL_H__ */
--
2.39.2
^ permalink raw reply [flat|nested] 25+ messages in thread* [PATCH 11/19] ARM: layerscape: implement ls1028a errata
2024-01-04 14:17 [PATCH 00/19] ARM: add Layerscape LS1028a support Sascha Hauer
` (9 preceding siblings ...)
2024-01-04 14:17 ` [PATCH 10/19] ARM: Layerscape: add layerscape_uart_putc() Sascha Hauer
@ 2024-01-04 14:17 ` Sascha Hauer
2024-01-04 14:17 ` [PATCH 12/19] ARM: layerscape: implement ls1028a debug_ll Sascha Hauer
` (7 subsequent siblings)
18 siblings, 0 replies; 25+ messages in thread
From: Sascha Hauer @ 2024-01-04 14:17 UTC (permalink / raw)
To: Barebox List
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-layerscape/errata.c | 49 +++++++++++++++++++++++++++++++
include/mach/layerscape/errata.h | 2 ++
2 files changed, 51 insertions(+)
diff --git a/arch/arm/mach-layerscape/errata.c b/arch/arm/mach-layerscape/errata.c
index fe0d0ab45e..deab584243 100644
--- a/arch/arm/mach-layerscape/errata.c
+++ b/arch/arm/mach-layerscape/errata.c
@@ -2,6 +2,7 @@
#include <common.h>
#include <io.h>
#include <soc/fsl/immap_lsch2.h>
+#include <soc/fsl/immap_lsch3.h>
#include <soc/fsl/fsl_ddr_sdram.h>
#include <asm/system.h>
#include <mach/layerscape/errata.h>
@@ -22,6 +23,15 @@ static void erratum_a008997_ls1021a(void)
set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1);
}
+static void erratum_a008997_ls1028a(void)
+{
+ void __iomem *dcsr = IOMEM(LSCH3_DCSR_BASE);
+
+ clrsetbits_le32(dcsr + LSCH3_DCSR_USB_IOCR1,
+ 0x7f << 11,
+ LSCH3_DCSR_USB_PCSTXSWINGFULL << 11);
+}
+
static void erratum_a008997_ls1046a(void)
{
u32 __iomem *scfg = (u32 __iomem *)LSCH2_SCFG_ADDR;
@@ -56,6 +66,11 @@ static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset)
scfg_clrsetbits32(scfg + offset / 4, 0xf << 6, SCFG_USB_TXVREFTUNE << 6);
}
+static void erratum_a009007_ls1028a(void)
+{
+ erratum_a009007(IOMEM(LSCH3_DCSR_BASE), 0x0000, 0x0080, 0x0380, 0x0b80);
+}
+
static void erratum_a009008_ls1021a(void)
{
u32 __iomem *scfg = IOMEM(LSCH2_SCFG_ADDR);
@@ -111,6 +126,26 @@ static void erratum_a008850_early(struct ccsr_cci400 __iomem *cci,
ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
}
+/*
+ * This erratum requires a register write before being Memory
+ * controller 3 being enabled.
+ */
+static void erratum_a008514(void)
+{
+ u32 *eddrtqcr1;
+
+ eddrtqcr1 = IOMEM(LSCH3_DCSR_DDR3_ADDR) + 0x800;
+ out_le32(eddrtqcr1, 0x63b20002);
+}
+
+static void erratum_a009798(void)
+{
+ u32 __iomem *scfg = IOMEM(LSCH3_SCFG_BASE);
+
+ clrbits_be32(scfg + LSCH3_SCFG_USB3PRM1CR / 4,
+ LSCH3_SCFG_USB_SQRXTUNE_MASK << 23);
+}
+
void ls1046a_errata(void)
{
erratum_a008850_early(IOMEM(LSCH2_CCI400_ADDR), IOMEM(LSCH2_DDR_ADDR));
@@ -129,6 +164,15 @@ void ls1021a_errata(void)
erratum_a009007_ls1021a();
}
+void ls1028a_errata(void)
+{
+ erratum_a008850_early(IOMEM(LSCH3_CCI400_ADDR), IOMEM(LSCH3_DDR_ADDR));
+ erratum_a009007_ls1028a();
+ erratum_a008997_ls1028a();
+ erratum_a008514();
+ erratum_a009798();
+}
+
static void erratum_a008850_post(struct ccsr_cci400 __iomem *cci,
struct ccsr_ddr __iomem *ddr)
{
@@ -228,3 +272,8 @@ void ls1021a_errata_post_ddr(void)
{
erratum_a008850_post(IOMEM(LSCH2_CCI400_ADDR), IOMEM(LSCH2_DDR_ADDR));
}
+
+void ls1028a_errata_post_ddr(void)
+{
+ erratum_a008850_post(IOMEM(LSCH3_CCI400_ADDR), IOMEM(LSCH3_DDR_ADDR));
+}
diff --git a/include/mach/layerscape/errata.h b/include/mach/layerscape/errata.h
index 4755031717..0611bd5f0f 100644
--- a/include/mach/layerscape/errata.h
+++ b/include/mach/layerscape/errata.h
@@ -4,8 +4,10 @@
#define __MACH_ERRATA_H
void ls1046a_errata(void);
+void ls1028a_errata(void);
void ls1021a_errata(void);
void ls1046a_errata_post_ddr(void);
+void ls1028a_errata_post_ddr(void);
void ls1021a_errata_post_ddr(void);
#endif /* __MACH_ERRATA_H */
--
2.39.2
^ permalink raw reply [flat|nested] 25+ messages in thread* [PATCH 12/19] ARM: layerscape: implement ls1028a debug_ll
2024-01-04 14:17 [PATCH 00/19] ARM: add Layerscape LS1028a support Sascha Hauer
` (10 preceding siblings ...)
2024-01-04 14:17 ` [PATCH 11/19] ARM: layerscape: implement ls1028a errata Sascha Hauer
@ 2024-01-04 14:17 ` Sascha Hauer
2024-01-04 14:17 ` [PATCH 13/19] include: <asm-generic/bug.h>: implement ASSERT() Sascha Hauer
` (6 subsequent siblings)
18 siblings, 0 replies; 25+ messages in thread
From: Sascha Hauer @ 2024-01-04 14:17 UTC (permalink / raw)
To: Barebox List
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
include/mach/layerscape/debug_ll.h | 21 ++++++++++++++++++++-
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/include/mach/layerscape/debug_ll.h b/include/mach/layerscape/debug_ll.h
index bdb54ca4b9..22c3224340 100644
--- a/include/mach/layerscape/debug_ll.h
+++ b/include/mach/layerscape/debug_ll.h
@@ -5,10 +5,14 @@
#include <io.h>
#include <soc/fsl/immap_lsch2.h>
+#include <soc/fsl/immap_lsch3.h>
#define __LS_UART_BASE(num) LSCH2_NS16550_COM##num
#define LS_UART_BASE(num) __LS_UART_BASE(num)
+#define __LSCH3_UART_BASE(num) LSCH3_NS16550_COM##num
+#define LSCH3_UART_BASE(num) __LSCH3_UART_BASE(num)
+
static inline uint8_t debug_ll_read_reg(void __iomem *base, int reg)
{
return readb(base + reg);
@@ -31,11 +35,26 @@ static inline void ls1046a_uart_setup(void *base)
static inline void ls1046a_debug_ll_init(void)
{
- void __iomem *base = IOMEM(LS_UART_BASE(CONFIG_DEBUG_LAYERSCAPE_UART_PORT));
+ void __iomem *base = IOMEM(LSCH3_UART_BASE(CONFIG_DEBUG_LAYERSCAPE_UART_PORT));
ls1046a_uart_setup(base);
}
+static inline void ls1028a_uart_setup(void *base)
+{
+ uint16_t divisor;
+
+ divisor = debug_ll_ns16550_calc_divisor(200000000);
+ debug_ll_ns16550_init(base, divisor);
+}
+
+static inline void ls1028a_debug_ll_init(void)
+{
+ void __iomem *base = IOMEM(LS_UART_BASE(CONFIG_DEBUG_LAYERSCAPE_UART_PORT));
+
+ ls1028a_uart_setup(base);
+}
+
static inline void ls102xa_uart_setup(void *base)
{
uint16_t divisor;
--
2.39.2
^ permalink raw reply [flat|nested] 25+ messages in thread* [PATCH 13/19] include: <asm-generic/bug.h>: implement ASSERT()
2024-01-04 14:17 [PATCH 00/19] ARM: add Layerscape LS1028a support Sascha Hauer
` (11 preceding siblings ...)
2024-01-04 14:17 ` [PATCH 12/19] ARM: layerscape: implement ls1028a debug_ll Sascha Hauer
@ 2024-01-04 14:17 ` Sascha Hauer
2024-01-04 14:17 ` [PATCH 14/19] ARM: Layerscape: add tzc400 support Sascha Hauer
` (5 subsequent siblings)
18 siblings, 0 replies; 25+ messages in thread
From: Sascha Hauer @ 2024-01-04 14:17 UTC (permalink / raw)
To: Barebox List
ASSERT() is a statement commonly used by other projects. This patch adds
an implementation for it.
It is normally compiled away and can be enabled with
CONFIG_BUG_ON_DATA_CORRUPTION.
While ASSERT() is usually written in lowercase letters, use uppercase
letters for barebox as we have a function hook in the reset controller
core that uses lowercase letters.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
include/asm-generic/bug.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/include/asm-generic/bug.h b/include/asm-generic/bug.h
index 5d0a458eae..18a1b419ff 100644
--- a/include/asm-generic/bug.h
+++ b/include/asm-generic/bug.h
@@ -62,4 +62,9 @@
unlikely(__ret_warn_once); \
})
+#define ASSERT(expr) do { \
+ if (IS_ENABLED(CONFIG_BUG_ON_DATA_CORRUPTION)) \
+ BUG_ON(!(expr)); \
+} while (0)
+
#endif
--
2.39.2
^ permalink raw reply [flat|nested] 25+ messages in thread* [PATCH 14/19] ARM: Layerscape: add tzc400 support
2024-01-04 14:17 [PATCH 00/19] ARM: add Layerscape LS1028a support Sascha Hauer
` (12 preceding siblings ...)
2024-01-04 14:17 ` [PATCH 13/19] include: <asm-generic/bug.h>: implement ASSERT() Sascha Hauer
@ 2024-01-04 14:17 ` Sascha Hauer
2024-01-29 17:32 ` Uwe Kleine-König
2024-01-04 14:17 ` [PATCH 15/19] ARM: Add ls1028a lowlevel init Sascha Hauer
` (4 subsequent siblings)
18 siblings, 1 reply; 25+ messages in thread
From: Sascha Hauer @ 2024-01-04 14:17 UTC (permalink / raw)
To: Barebox List
This adds the code necessary to initialize the TZC400 unit found on the
LS1028a. The code is taken from TF-A. It's mostly SoC independent, but
keep it in arch-layerscape for now until we get a second user and it's
clear which parts can be re-used.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-layerscape/Makefile | 1 +
arch/arm/mach-layerscape/tzc400.c | 303 +++++++++++++++++++++++++++++
arch/arm/mach-layerscape/tzc400.h | 164 ++++++++++++++++
include/mach/layerscape/lowlevel.h | 3 +
4 files changed, 471 insertions(+)
create mode 100644 arch/arm/mach-layerscape/tzc400.c
create mode 100644 arch/arm/mach-layerscape/tzc400.h
diff --git a/arch/arm/mach-layerscape/Makefile b/arch/arm/mach-layerscape/Makefile
index ebb030a1cb..8f288851ff 100644
--- a/arch/arm/mach-layerscape/Makefile
+++ b/arch/arm/mach-layerscape/Makefile
@@ -6,6 +6,7 @@ lwl-$(CONFIG_ARCH_LS1046) += lowlevel.o lowlevel-ls1046a.o
obj-$(CONFIG_ARCH_LS1046) += icid.o
obj-pbl-y += boot.o soc.o
pbl-y += xload-qspi.o xload.o
+pbl-$(CONFIG_ARCH_LS1028) += tzc400.o
obj-$(CONFIG_ARCH_LAYERSCAPE_PPA) += ppa.o ppa-entry.o
obj-$(CONFIG_BOOTM) += pblimage.o
diff --git a/arch/arm/mach-layerscape/tzc400.c b/arch/arm/mach-layerscape/tzc400.c
new file mode 100644
index 0000000000..04a97809f5
--- /dev/null
+++ b/arch/arm/mach-layerscape/tzc400.c
@@ -0,0 +1,303 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
+ *
+ */
+#define pr_fmt(fmt) "tzc400: " fmt
+
+#include <common.h>
+#include <linux/bitfield.h>
+#include <linux/sizes.h>
+#include <mach/layerscape/lowlevel.h>
+#include <mach/layerscape/layerscape.h>
+
+#include "tzc400.h"
+
+static inline void mmio_write_32(uintptr_t addr, uint32_t value)
+{
+ out_le32(addr, value);
+}
+
+static inline uint32_t mmio_read_32(uintptr_t addr)
+{
+ return in_le32(addr);
+}
+
+static inline void mmio_clrsetbits_32(uintptr_t addr,
+ uint32_t clear,
+ uint32_t set)
+{
+ clrsetbits_le32(addr, clear, set);
+}
+
+static inline unsigned int tzc_read_peripheral_id(uintptr_t base)
+{
+ unsigned int id;
+
+ id = mmio_read_32(base + PID0_OFF);
+ /* Masks DESC part in PID1 */
+ id |= ((mmio_read_32(base + PID1_OFF) & 0xFU) << 8U);
+
+ return id;
+}
+
+/*
+ * Implementation defined values used to validate inputs later.
+ * Filters : max of 4 ; 0 to 3
+ * Regions : max of 9 ; 0 to 8
+ * Address width : Values between 32 to 64
+ */
+struct tzc400_instance {
+ uintptr_t base;
+ uint8_t addr_width;
+ uint8_t num_filters;
+ uint8_t num_regions;
+};
+
+static struct tzc400_instance tzc400;
+
+static inline unsigned int tzc400_read_gate_keeper(void)
+{
+ uintptr_t base = tzc400.base;
+
+ return mmio_read_32(base + TZC400_GATE_KEEPER);
+}
+
+static inline void tzc400_write_gate_keeper(unsigned int val)
+{
+ uintptr_t base = tzc400.base;
+
+ mmio_write_32(base + TZC400_GATE_KEEPER, val);
+}
+
+static unsigned int tzc400_open_status(void)
+{
+ return FIELD_GET(TZC400_GATE_KEEPER_OS, tzc400_read_gate_keeper());
+}
+
+static unsigned int tzc400_get_gate_keeper(unsigned int filter)
+{
+ return (tzc400_open_status() >> filter) & GATE_KEEPER_FILTER_MASK;
+}
+
+/* This function is not MP safe. */
+static void tzc400_set_gate_keeper(unsigned int filter, int val)
+{
+ unsigned int os;
+
+ /* Upper half is current state. Lower half is requested state. */
+ os = tzc400_open_status();
+
+ if (val != 0)
+ os |= (1UL << filter);
+ else
+ os &= ~(1UL << filter);
+
+ tzc400_write_gate_keeper(FIELD_PREP(TZC400_GATE_KEEPER_OR, os));
+
+ /* Wait here until we see the change reflected in the TZC status. */
+ while ((tzc400_open_status()) != os)
+ ;
+}
+
+void tzc400_set_action(unsigned int action)
+{
+ uintptr_t base = tzc400.base;
+
+ ASSERT(base != 0U);
+ ASSERT(action <= TZC_ACTION_ERR_INT);
+
+ mmio_write_32(base + TZC400_ACTION, action);
+}
+
+void tzc400_init(uintptr_t base)
+{
+ unsigned int tzc400_id;
+ unsigned int tzc400_build;
+
+ tzc400.base = base;
+
+ tzc400_id = tzc_read_peripheral_id(base);
+ if (tzc400_id != TZC400_PERIPHERAL_ID)
+ panic("TZC-400 : Wrong device ID (0x%x).\n", tzc400_id);
+
+ /* Save values we will use later. */
+ tzc400_build = mmio_read_32(base + TZC400_BUILD_CONFIG);
+ tzc400.num_filters = FIELD_GET(TZC400_BUILD_CONFIG_NF, tzc400_build) + 1;
+ tzc400.addr_width = FIELD_GET(TZC400_BUILD_CONFIG_AW, tzc400_build) + 1;
+ tzc400.num_regions = FIELD_GET(TZC400_BUILD_CONFIG_NR, tzc400_build) + 1;
+}
+
+/*
+ * `tzc400_configure_region` is used to program regions into the TrustZone
+ * controller. A region can be associated with more than one filter. The
+ * associated filters are passed in as a bitmap (bit0 = filter0), except that
+ * the value TZC400_REGION_ATTR_FILTER_BIT_ALL selects all filters, based on
+ * the value of tzc400.num_filters.
+ * NOTE:
+ * Region 0 is special; it is preferable to use tzc400_configure_region0
+ * for this region (see comment for that function).
+ */
+void tzc400_configure_region(unsigned int filters, unsigned int region, uint64_t region_base,
+ uint64_t region_top, unsigned int sec_attr,
+ unsigned int nsaid_permissions)
+{
+ uintptr_t rbase = tzc400.base + TZC_REGION_OFFSET(TZC400_REGION_SIZE, region);
+
+ /* Adjust filter mask by real filter number */
+ if (filters == TZC400_REGION_ATTR_FILTER_BIT_ALL)
+ filters = (1U << tzc400.num_filters) - 1U;
+
+ /* Do range checks on filters and regions. */
+ ASSERT(((filters >> tzc400.num_filters) == 0U) &&
+ (region < tzc400.num_regions));
+
+ /*
+ * Do address range check based on TZC configuration. A 64bit address is
+ * the max and expected case.
+ */
+ ASSERT((region_top <= (U64_MAX >> (64U - tzc400.addr_width))) &&
+ (region_base < region_top));
+
+ /* region_base and (region_top + 1) must be 4KB aligned */
+ ASSERT(((region_base | (region_top + 1U)) & (4096U - 1U)) == 0U);
+
+ ASSERT(sec_attr <= TZC_REGION_S_RDWR);
+
+ pr_debug("TrustZone : Configuring region %u\n", region);
+ pr_debug("TrustZone : ... base = %llx, top = %llx,\n", region_base, region_top);
+ pr_debug("TrustZone : ... sec_attr = 0x%x, ns_devs = 0x%x)\n",
+ sec_attr, nsaid_permissions);
+
+ /***************************************************/
+ /* Inputs look ok, start programming registers. */
+ /* All the address registers are 32 bits wide and */
+ /* have a LOW and HIGH */
+ /* component used to construct an address up to a */
+ /* 64bit. */
+ /***************************************************/
+ mmio_write_32(rbase + TZC400_REGION_BASE_LOW_0, (uint32_t)region_base);
+ mmio_write_32(rbase + TZC400_REGION_BASE_HIGH_0, (uint32_t)(region_base >> 32));
+ mmio_write_32(rbase + TZC400_REGION_TOP_LOW_0, (uint32_t)region_top);
+ mmio_write_32(rbase + TZC400_REGION_TOP_HIGH_0, (uint32_t)(region_top >> 32));
+
+ /* Enable filter to the region and set secure attributes */
+ mmio_write_32(rbase + TZC400_REGION_ATTR_0,
+ (sec_attr << TZC_REGION_ATTR_SEC_SHIFT) | (filters << TZC_REGION_ATTR_F_EN_SHIFT));
+
+ /***************************************************/
+ /* Specify which non-secure devices have permission*/
+ /* to access this region. */
+ /***************************************************/
+ mmio_write_32(rbase + TZC400_REGION_ID_ACCESS_0, nsaid_permissions);
+}
+
+void tzc400_update_filters(unsigned int region, unsigned int filters)
+{
+ uintptr_t rbase = tzc400.base + TZC_REGION_OFFSET(TZC400_REGION_SIZE, region);
+ uint32_t filters_mask = GENMASK(tzc400.num_filters - 1U, 0);
+
+ /* Do range checks on filters and regions. */
+ ASSERT(((filters >> tzc400.num_filters) == 0U) &&
+ (region < tzc400.num_regions));
+
+ mmio_clrsetbits_32(rbase + TZC400_REGION_ATTR_0,
+ filters_mask << TZC_REGION_ATTR_F_EN_SHIFT,
+ filters << TZC_REGION_ATTR_F_EN_SHIFT);
+}
+
+void tzc400_enable_filters(void)
+{
+ unsigned int state;
+ unsigned int filter;
+
+ ASSERT(tzc400.base != 0U);
+
+ for (filter = 0U; filter < tzc400.num_filters; filter++) {
+ state = tzc400_get_gate_keeper(filter);
+ if (state != 0U) {
+ /* Filter 0 is special and cannot be disabled.
+ * So here we allow it being already enabled. */
+ if (filter == 0U)
+ continue;
+
+ /*
+ * The TZC filter is already configured. Changing the
+ * programmer's view in an active system can cause
+ * unpredictable behavior therefore panic for now rather
+ * than try to determine whether this is safe in this
+ * instance.
+ *
+ * See the 'ARM (R) CoreLink TM TZC-400 TrustZone (R)
+ * Address Space Controller' Technical Reference Manual.
+ */
+ panic("TZC-400 : Filter %u Gatekeeper already enabled.\n",
+ filter);
+ }
+ tzc400_set_gate_keeper(filter, 1);
+ }
+}
+
+void tzc400_disable_filters(void)
+{
+ unsigned int filter;
+ unsigned int state;
+ unsigned int start = 0U;
+
+ ASSERT(tzc400.base != 0U);
+
+ /* Filter 0 is special and cannot be disabled. */
+ state = tzc400_get_gate_keeper(0);
+ if (state != 0U)
+ start++;
+
+ for (filter = start; filter < tzc400.num_filters; filter++)
+ tzc400_set_gate_keeper(filter, 0);
+}
+
+unsigned long ls1028a_tzc400_init(unsigned long memsize)
+{
+ unsigned long lowmem, highmem, lowmem_end;
+
+ tzc400_init(LS1028A_TZC400_BASE);
+ tzc400_disable_filters();
+
+ /* Region 0 set to no access by default */
+ mmio_write_32(tzc400.base + TZC400_REGION_ATTR_0, TZC_REGION_S_NONE << TZC_REGION_ATTR_SEC_SHIFT);
+ mmio_write_32(tzc400.base + TZC400_REGION_ID_ACCESS_0, 0);
+
+ lowmem = min_t(unsigned long, LS1028A_DDR_SDRAM_LOWMEM_SIZE, memsize);
+ lowmem_end = LS1028A_DDR_SDRAM_BASE + lowmem;
+ highmem = memsize - lowmem;
+
+ /* region 1: secure memory */
+ tzc400_configure_region(1, 1,
+ lowmem_end - LS1028A_SECURE_DRAM_SIZE,
+ lowmem_end - 1,
+ TZC_REGION_S_RDWR, TZC_REGION_NS_NONE);
+
+ /* region 2: shared memory */
+ tzc400_configure_region(1, 2,
+ lowmem_end - LS1028A_SECURE_DRAM_SIZE - LS1028A_SP_SHARED_DRAM_SIZE,
+ lowmem_end - LS1028A_SECURE_DRAM_SIZE - 1,
+ TZC_REGION_S_RDWR, TZC_NS_ACCESS_ID);
+
+ /* region 3: nonsecure low memory */
+ tzc400_configure_region(1, 3,
+ LS1028A_DDR_SDRAM_BASE,
+ lowmem_end - LS1028A_SECURE_DRAM_SIZE - LS1028A_SP_SHARED_DRAM_SIZE - 1,
+ TZC_REGION_S_RDWR, TZC_NS_ACCESS_ID);
+
+ if (highmem)
+ /* nonsecure high memory */
+ tzc400_configure_region(1, 4,
+ LS1028A_DDR_SDRAM_HIGHMEM_BASE,
+ LS1028A_DDR_SDRAM_HIGHMEM_BASE + highmem - 1,
+ TZC_REGION_S_RDWR, TZC_NS_ACCESS_ID);
+
+ tzc400_set_action(TZC_ACTION_ERR);
+
+ tzc400_enable_filters();
+
+ return lowmem - LS1028A_SECURE_DRAM_SIZE - LS1028A_SP_SHARED_DRAM_SIZE;
+}
diff --git a/arch/arm/mach-layerscape/tzc400.h b/arch/arm/mach-layerscape/tzc400.h
new file mode 100644
index 0000000000..c8d4583622
--- /dev/null
+++ b/arch/arm/mach-layerscape/tzc400.h
@@ -0,0 +1,164 @@
+/*
+ * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef TZC400_H
+#define TZC400_H
+
+#include <linux/bits.h>
+
+/*
+ * Offset of core registers from the start of the base of configuration
+ * registers for each region.
+ */
+
+/* ID Registers */
+#define PID0_OFF 0xfe0
+#define PID1_OFF 0xfe4
+#define PID2_OFF 0xfe8
+#define PID3_OFF 0xfec
+#define PID4_OFF 0xfd0
+#define CID0_OFF 0xff0
+#define CID1_OFF 0xff4
+#define CID2_OFF 0xff8
+#define CID3_OFF 0xffc
+
+/*
+ * What type of action is expected when an access violation occurs.
+ * The memory requested is returned as zero. But we can also raise an event to
+ * let the system know it happened.
+ * We can raise an interrupt(INT) and/or cause an exception(ERR).
+ * TZC_ACTION_NONE - No interrupt, no Exception
+ * TZC_ACTION_ERR - No interrupt, raise exception -> sync external
+ * data abort
+ * TZC_ACTION_INT - Raise interrupt, no exception
+ * TZC_ACTION_ERR_INT - Raise interrupt, raise exception -> sync
+ * external data abort
+ */
+#define TZC_ACTION_NONE 0
+#define TZC_ACTION_ERR 1
+#define TZC_ACTION_INT 2
+#define TZC_ACTION_ERR_INT (TZC_ACTION_ERR | TZC_ACTION_INT)
+
+/* Bit positions of TZC_ACTION registers */
+#define TZC_ACTION_RV_SHIFT 0
+#define TZC_ACTION_RV_MASK 0x3
+#define TZC_ACTION_RV_LOWOK 0x0
+#define TZC_ACTION_RV_LOWERR 0x1
+#define TZC_ACTION_RV_HIGHOK 0x2
+#define TZC_ACTION_RV_HIGHERR 0x3
+
+/*
+ * Controls secure access to a region. If not enabled secure access is not
+ * allowed to region.
+ */
+#define TZC_REGION_S_NONE 0
+#define TZC_REGION_S_RD 1
+#define TZC_REGION_S_WR 2
+#define TZC_REGION_S_RDWR (TZC_REGION_S_RD | TZC_REGION_S_WR)
+
+#define TZC_REGION_ATTR_S_RD_SHIFT 30
+#define TZC_REGION_ATTR_S_WR_SHIFT 31
+#define TZC_REGION_ATTR_F_EN_SHIFT 0
+#define TZC_REGION_ATTR_SEC_SHIFT 30
+#define TZC_REGION_ATTR_S_RD_MASK 0x1
+#define TZC_REGION_ATTR_S_WR_MASK 0x1
+#define TZC_REGION_ATTR_SEC_MASK 0x3
+
+#define TZC_REGION_ACCESS_WR_EN_SHIFT 16
+#define TZC_REGION_ACCESS_RD_EN_SHIFT 0
+#define TZC_REGION_ACCESS_ID_MASK 0xf
+
+/* Macros for allowing Non-Secure access to a region based on NSAID */
+#define TZC_REGION_ACCESS_RD(nsaid) \
+ ((U(1) << ((nsaid) & TZC_REGION_ACCESS_ID_MASK)) << \
+ TZC_REGION_ACCESS_RD_EN_SHIFT)
+#define TZC_REGION_ACCESS_WR(nsaid) \
+ ((U(1) << ((nsaid) & TZC_REGION_ACCESS_ID_MASK)) << \
+ TZC_REGION_ACCESS_WR_EN_SHIFT)
+#define TZC_REGION_ACCESS_RDWR(nsaid) \
+ (TZC_REGION_ACCESS_RD(nsaid) | \
+ TZC_REGION_ACCESS_WR(nsaid))
+
+/* Returns offset of registers to program for a given region no */
+#define TZC_REGION_OFFSET(region_size, region_no) \
+ ((region_size) * (region_no))
+
+#define TZC400_BUILD_CONFIG 0x000
+#define TZC400_GATE_KEEPER 0x008
+#define TZC400_SPECULATION_CTRL 0x00c
+#define TZC400_INT_STATUS 0x010
+#define TZC400_INT_CLEAR 0x014
+
+#define TZC400_FAIL_ADDRESS_LOW 0x020
+#define TZC400_FAIL_ADDRESS_HIGH 0x024
+#define TZC400_FAIL_CONTROL 0x028
+#define TZC400_FAIL_ID 0x02c
+
+#define TZC400_BUILD_CONFIG_NF GENMASK(25, 24)
+#define TZC400_BUILD_CONFIG_AW GENMASK(13, 8)
+#define TZC400_BUILD_CONFIG_NR GENMASK(4, 0)
+
+/*
+ * Number of gate keepers is implementation defined. But we know the max for
+ * this device is 4. Get implementation details from BUILD_CONFIG.
+ */
+#define TZC400_GATE_KEEPER_OS GENMASK(19, 16)
+#define TZC400_GATE_KEEPER_OR GENMASK(3, 0)
+#define GATE_KEEPER_FILTER_MASK 0x1
+
+#define TZC400_FAIL_CONTROL_DIR_WRITE BIT(24)
+#define TZC400_FAIL_CONTROL_NS_NONSECURE BIT(21)
+#define TZC400_FAIL_CONTROL_PRIV BIT(20)
+
+#define TZC400_PERIPHERAL_ID 0x460
+
+/* Filter enable bits in a TZC */
+#define TZC400_REGION_ATTR_F_EN_MASK 0xf
+#define TZC400_REGION_ATTR_FILTER_BIT(x) (1) << (x))
+#define TZC400_REGION_ATTR_FILTER_BIT_ALL TZC400_REGION_ATTR_F_EN_MASK
+
+/*
+ * All TZC region configuration registers are placed one after another. It
+ * depicts size of block of registers for programming each region.
+ */
+#define TZC400_REGION_SIZE 0x20
+#define TZC400_ACTION 0x4
+
+#define FILTER_OFFSET 0x10
+
+#define TZC400_REGION_BASE_LOW_0 0x100
+#define TZC400_REGION_BASE_HIGH_0 0x104
+#define TZC400_REGION_TOP_LOW_0 0x108
+#define TZC400_REGION_TOP_HIGH_0 0x10c
+#define TZC400_REGION_ATTR_0 0x110
+#define TZC400_REGION_ID_ACCESS_0 0x114
+
+#define TZC_REGION_NS_NONE 0x00000000U
+
+/*
+ * NXP Platforms do not support NS Access ID (NSAID) based non-secure access.
+ * Supports only non secure through generic NS ACCESS ID
+ */
+#define TZC_NS_ACCESS_ID 0xFFFFFFFFU
+
+/*******************************************************************************
+ * Function & variable prototypes
+ ******************************************************************************/
+void tzc400_init(uintptr_t base);
+void tzc400_configure_region0(unsigned int sec_attr,
+ unsigned int ns_device_access);
+void tzc400_configure_region(unsigned int filters,
+ unsigned int region,
+ unsigned long long region_base,
+ unsigned long long region_top,
+ unsigned int sec_attr,
+ unsigned int nsaid_permissions);
+void tzc400_update_filters(unsigned int region, unsigned int filters);
+void tzc400_set_action(unsigned int action);
+void tzc400_enable_filters(void);
+void tzc400_disable_filters(void);
+
+#endif /* TZC400_H */
diff --git a/include/mach/layerscape/lowlevel.h b/include/mach/layerscape/lowlevel.h
index d013c5e610..e59fb67740 100644
--- a/include/mach/layerscape/lowlevel.h
+++ b/include/mach/layerscape/lowlevel.h
@@ -4,7 +4,10 @@
#define __MACH_LOWLEVEL_H
void ls1046a_init_lowlevel(void);
+void ls1028a_init_lowlevel(void);
void ls1046a_init_l2_latency(void);
void ls102xa_init_lowlevel(void);
+unsigned long ls1028a_tzc400_init(unsigned long memsize);
+
#endif /* __MACH_LOWLEVEL_H */
--
2.39.2
^ permalink raw reply [flat|nested] 25+ messages in thread* [PATCH 15/19] ARM: Add ls1028a lowlevel init
2024-01-04 14:17 [PATCH 00/19] ARM: add Layerscape LS1028a support Sascha Hauer
` (13 preceding siblings ...)
2024-01-04 14:17 ` [PATCH 14/19] ARM: Layerscape: add tzc400 support Sascha Hauer
@ 2024-01-04 14:17 ` Sascha Hauer
2024-01-04 14:17 ` [PATCH 16/19] ARM: atf: add bl31 v2 calling method Sascha Hauer
` (3 subsequent siblings)
18 siblings, 0 replies; 25+ messages in thread
From: Sascha Hauer @ 2024-01-04 14:17 UTC (permalink / raw)
To: Barebox List
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-layerscape/Makefile | 2 +
arch/arm/mach-layerscape/lowlevel-ls1028a.c | 42 +++++++++++++++++++++
include/mach/layerscape/layerscape.h | 7 ++++
3 files changed, 51 insertions(+)
create mode 100644 arch/arm/mach-layerscape/lowlevel-ls1028a.c
diff --git a/arch/arm/mach-layerscape/Makefile b/arch/arm/mach-layerscape/Makefile
index 8f288851ff..e4bb1b42f2 100644
--- a/arch/arm/mach-layerscape/Makefile
+++ b/arch/arm/mach-layerscape/Makefile
@@ -12,3 +12,5 @@ obj-$(CONFIG_BOOTM) += pblimage.o
lwl-$(CONFIG_ARCH_LS1021) += lowlevel-ls102xa.o
obj-$(CONFIG_ARCH_LS1021) += restart.o ls102xa_stream_id.o
+
+lwl-$(CONFIG_ARCH_LS1028) += lowlevel-ls1028a.o
diff --git a/arch/arm/mach-layerscape/lowlevel-ls1028a.c b/arch/arm/mach-layerscape/lowlevel-ls1028a.c
new file mode 100644
index 0000000000..fd013b2b52
--- /dev/null
+++ b/arch/arm/mach-layerscape/lowlevel-ls1028a.c
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <common.h>
+#include <io.h>
+#include <asm/syscounter.h>
+#include <asm/system.h>
+#include <mach/layerscape/errata.h>
+#include <mach/layerscape/lowlevel.h>
+#include <soc/fsl/immap_lsch3.h>
+#include <soc/fsl/scfg.h>
+
+static void ls1028a_timer_init(void)
+{
+ u32 __iomem *cntcr = IOMEM(LSCH3_TIMER_ADDR);
+ u32 __iomem *cltbenr = IOMEM(LSCH3_PMU_CLTBENR);
+
+ u32 __iomem *pctbenr = IOMEM(LSCH3_PCTBENR_OFFSET);
+
+ /* Enable timebase for all clusters.
+ * It is safe to do so even some clusters are not enabled.
+ */
+ out_le32(cltbenr, 0xf);
+
+ /*
+ * In certain Layerscape SoCs, the clock for each core's
+ * has an enable bit in the PMU Physical Core Time Base Enable
+ * Register (PCTBENR), which allows the watchdog to operate.
+ */
+ setbits_le32(pctbenr, 0xff);
+
+ /* Enable clock for timer
+ * This is a global setting.
+ */
+ out_le32(cntcr, 0x1);
+}
+
+void ls1028a_init_lowlevel(void)
+{
+ scfg_init(SCFG_ENDIANESS_LITTLE);
+ set_cntfrq(25000000);
+ ls1028a_timer_init();
+ ls1028a_errata();
+}
diff --git a/include/mach/layerscape/layerscape.h b/include/mach/layerscape/layerscape.h
index c3dfe4d860..95c230b8f3 100644
--- a/include/mach/layerscape/layerscape.h
+++ b/include/mach/layerscape/layerscape.h
@@ -9,6 +9,13 @@
#define LS1021A_DDR_SDRAM_BASE 0x80000000
#define LS1021A_DDR_FREQ 1600000000
+#define LS1028A_DDR_SDRAM_BASE 0x80000000
+#define LS1028A_DDR_SDRAM_LOWMEM_SIZE 0x80000000
+#define LS1028A_DDR_SDRAM_HIGHMEM_BASE 0x2080000000
+#define LS1028A_SECURE_DRAM_SIZE SZ_64M
+#define LS1028A_SP_SHARED_DRAM_SIZE SZ_2M
+#define LS1028A_TZC400_BASE 0x01100000
+
enum bootsource ls1046a_bootsource_get(void);
enum bootsource ls1021a_bootsource_get(void);
--
2.39.2
^ permalink raw reply [flat|nested] 25+ messages in thread* [PATCH 16/19] ARM: atf: add bl31 v2 calling method
2024-01-04 14:17 [PATCH 00/19] ARM: add Layerscape LS1028a support Sascha Hauer
` (14 preceding siblings ...)
2024-01-04 14:17 ` [PATCH 15/19] ARM: Add ls1028a lowlevel init Sascha Hauer
@ 2024-01-04 14:17 ` Sascha Hauer
2024-01-04 14:17 ` [PATCH 17/19] mci: imx-esdhc-pbl: factor out common function Sascha Hauer
` (2 subsequent siblings)
18 siblings, 0 replies; 25+ messages in thread
From: Sascha Hauer @ 2024-01-04 14:17 UTC (permalink / raw)
To: Barebox List
Newer bl31 binaries require a slightly different parameter structure.
This patch adds support for it. The code is taken from U-Boot and
changed to static initializers for improved readability.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/cpu/atf.c | 94 +++++++++++++++++++++++++++++++
arch/arm/include/asm/atf_common.h | 40 +++++++++++++
2 files changed, 134 insertions(+)
diff --git a/arch/arm/cpu/atf.c b/arch/arm/cpu/atf.c
index ccd540d32a..d01e20508c 100644
--- a/arch/arm/cpu/atf.c
+++ b/arch/arm/cpu/atf.c
@@ -80,3 +80,97 @@ void bl31_entry(uintptr_t bl31_entry, uintptr_t bl32_entry,
atf_entry(&bl31_params, fdt_addr);
}
+
+struct bl2_to_bl31_params_mem_v2 *bl2_plat_get_bl31_params_v2(uintptr_t bl32_entry,
+ uintptr_t bl33_entry, uintptr_t fdt_addr)
+{
+ static struct bl2_to_bl31_params_mem_v2 p = {
+ .bl_params = {
+ .h = {
+ .type = ATF_PARAM_BL_PARAMS,
+ .version = ATF_VERSION_2,
+ .size = sizeof(struct bl_params),
+ .attr = 0,
+ },
+ .head = &p.bl31_params_node,
+ },
+ .bl31_params_node = {
+ .image_id = ATF_BL31_IMAGE_ID,
+ .image_info = &p.bl31_image_info,
+ .ep_info = &p.bl31_ep_info,
+ .next_params_info = &p.bl32_params_node,
+ },
+ .bl32_params_node = {
+ .image_id = ATF_BL32_IMAGE_ID,
+ .image_info = &p.bl32_image_info,
+ .ep_info = &p.bl32_ep_info,
+ .next_params_info = &p.bl33_params_node,
+ },
+ .bl33_params_node = {
+ .image_id = ATF_BL33_IMAGE_ID,
+ .image_info = &p.bl33_image_info,
+ .ep_info = &p.bl33_ep_info,
+ .next_params_info = NULL,
+ },
+ .bl32_ep_info = {
+ .h = {
+ .type = ATF_PARAM_EP,
+ .version = ATF_VERSION_2,
+ .size = sizeof(struct entry_point_info),
+ .attr = ATF_EP_SECURE,
+ },
+ .spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXECPTIONS),
+ },
+ .bl33_ep_info = {
+ .h = {
+ .type = ATF_PARAM_EP,
+ .version = ATF_VERSION_2,
+ .size = sizeof(struct entry_point_info),
+ .attr = ATF_EP_NON_SECURE,
+ },
+ .spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXECPTIONS),
+ },
+ .bl33_image_info = {
+ .h = {
+ .type = ATF_PARAM_IMAGE_BINARY,
+ .version = ATF_VERSION_2,
+ .size = sizeof(struct atf_image_info),
+ .attr = 0,
+ },
+ },
+ .bl32_image_info = {
+ .h = {
+ .type = ATF_PARAM_IMAGE_BINARY,
+ .version = ATF_VERSION_2,
+ .size = sizeof(struct atf_image_info),
+ .attr = ATF_EP_SECURE,
+ },
+ },
+ .bl31_image_info = {
+ .h = {
+ .type = ATF_PARAM_IMAGE_BINARY,
+ .version = ATF_VERSION_2,
+ .size = sizeof(struct atf_image_info),
+ .attr = 0,
+ },
+ },
+ };
+
+ p.bl33_ep_info.args.arg0 = 0xffff & read_mpidr();
+ p.bl33_ep_info.pc = bl33_entry;
+ p.bl32_ep_info.args.arg3 = fdt_addr;
+ p.bl32_ep_info.pc = bl32_entry;
+
+ return &p;
+}
+
+void bl31_entry_v2(uintptr_t bl31_entry, struct bl_params *params, void *fdt_addr)
+{
+ void (*atf_entry)(struct bl_params *params, uintptr_t plat_params);
+
+ raw_write_daif(SPSR_EXCEPTION_MASK);
+
+ atf_entry = (void *)bl31_entry;
+
+ atf_entry(params, (uintptr_t)fdt_addr);
+}
diff --git a/arch/arm/include/asm/atf_common.h b/arch/arm/include/asm/atf_common.h
index 56e2d3ffaa..ab99cd3ac1 100644
--- a/arch/arm/include/asm/atf_common.h
+++ b/arch/arm/include/asm/atf_common.h
@@ -14,8 +14,14 @@
#define ATF_PARAM_EP 0x01
#define ATF_PARAM_IMAGE_BINARY 0x02
#define ATF_PARAM_BL31 0x03
+#define ATF_PARAM_BL_PARAMS 0x05
#define ATF_VERSION_1 0x01
+#define ATF_VERSION_2 0x02
+
+#define ATF_BL31_IMAGE_ID 0x03
+#define ATF_BL32_IMAGE_ID 0x04
+#define ATF_BL33_IMAGE_ID 0x05
#define ATF_EP_SECURE 0x0
#define ATF_EP_NON_SECURE 0x1
@@ -158,6 +164,40 @@ struct bl31_params {
void bl31_entry(uintptr_t bl31_entry, uintptr_t bl32_entry,
uintptr_t bl33_entry, uintptr_t fdt_addr);
+/* BL image node in the BL image execution sequence */
+struct bl_params_node {
+ unsigned int image_id;
+ struct atf_image_info *image_info;
+ struct entry_point_info *ep_info;
+ struct bl_params_node *next_params_info;
+};
+
+/*
+ * BL image head node in the BL image execution sequence
+ * It is also used to pass information to next BL image.
+ */
+struct bl_params {
+ struct param_header h;
+ struct bl_params_node *head;
+};
+
+struct bl2_to_bl31_params_mem_v2 {
+ struct bl_params bl_params;
+ struct bl_params_node bl31_params_node;
+ struct bl_params_node bl32_params_node;
+ struct bl_params_node bl33_params_node;
+ struct atf_image_info bl31_image_info;
+ struct atf_image_info bl32_image_info;
+ struct atf_image_info bl33_image_info;
+ struct entry_point_info bl31_ep_info;
+ struct entry_point_info bl32_ep_info;
+ struct entry_point_info bl33_ep_info;
+};
+
+struct bl2_to_bl31_params_mem_v2 *bl2_plat_get_bl31_params_v2(uintptr_t bl32_entry,
+ uintptr_t bl33_entry, uintptr_t fdt_addr);
+void bl31_entry_v2(uintptr_t bl31_entry, struct bl_params *params, void *fdt_addr);
+
#endif /*__ASSEMBLY__ */
#endif /* __BL_COMMON_H__ */
--
2.39.2
^ permalink raw reply [flat|nested] 25+ messages in thread* [PATCH 17/19] mci: imx-esdhc-pbl: factor out common function
2024-01-04 14:17 [PATCH 00/19] ARM: add Layerscape LS1028a support Sascha Hauer
` (15 preceding siblings ...)
2024-01-04 14:17 ` [PATCH 16/19] ARM: atf: add bl31 v2 calling method Sascha Hauer
@ 2024-01-04 14:17 ` Sascha Hauer
2024-01-04 14:17 ` [PATCH 18/19] mci: imx-esdhc-pbl: implement esdhc xload for ls1028a Sascha Hauer
2024-01-04 14:17 ` [PATCH 19/19] ARM: Layerscape: add basic support for NXP LS1028a RDB Sascha Hauer
18 siblings, 0 replies; 25+ messages in thread
From: Sascha Hauer @ 2024-01-04 14:17 UTC (permalink / raw)
To: Barebox List
Factor out some code that can be re-used by upcoming ls1028a support.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/mci/imx-esdhc-pbl.c | 66 ++++++++++++++++++++++---------------
1 file changed, 39 insertions(+), 27 deletions(-)
diff --git a/drivers/mci/imx-esdhc-pbl.c b/drivers/mci/imx-esdhc-pbl.c
index 892329de51..c13830d726 100644
--- a/drivers/mci/imx-esdhc-pbl.c
+++ b/drivers/mci/imx-esdhc-pbl.c
@@ -17,7 +17,7 @@
#include <mach/imx/imx8mm-regs.h>
#include <mach/imx/imx-header.h>
#endif
-#ifdef CONFIG_ARCH_LS1046
+#ifdef CONFIG_ARCH_LAYERSCAPE
#include <mach/layerscape/xload.h>
#endif
#include "sdhci.h"
@@ -298,7 +298,39 @@ int imx8mn_esdhc_load_image(int instance, bool start)
__alias(imx8mp_esdhc_load_image);
#endif
-#ifdef CONFIG_ARCH_LS1046
+#ifdef CONFIG_ARCH_LAYERSCAPE
+
+static int layerscape_esdhc_load_image(struct fsl_esdhc_host *host, void *adr, unsigned long size,
+ uint32_t div_val)
+{
+ uint32_t val;
+ int ret;
+
+ esdhc_populate_sdhci(host);
+ sdhci_write32(&host->sdhci, IMX_SDHCI_WML, 0);
+
+ /*
+ * The ROM leaves us here with a clock frequency of around 400kHz. Speed
+ * this up a bit. FIXME: The resulting frequency has not yet been verified
+ * to work on all cards.
+ */
+ val = sdhci_read32(&host->sdhci, SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET);
+ val &= ~0x0000fff0;
+ val |= div_val;
+ sdhci_write32(&host->sdhci, SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET, val);
+
+ sdhci_write32(&host->sdhci, ESDHC_DMA_SYSCTL, ESDHC_SYSCTL_DMA_SNOOP);
+
+ ret = esdhc_read_blocks(host, adr, size);
+ if (ret) {
+ pr_err("%s: reading blocks failed with: %d\n", __func__, ret);
+ return ret;
+ }
+
+ sync_caches_for_execution();
+
+ return 0;
+}
/*
* The image on the SD card starts at 0x1000. We reserved 128KiB for the PBL,
@@ -319,7 +351,6 @@ int imx8mn_esdhc_load_image(int instance, bool start)
int ls1046a_esdhc_start_image(unsigned long r0, unsigned long r1, unsigned long r2)
{
int ret;
- uint32_t val;
struct esdhc_soc_data data = {
.flags = ESDHC_FLAG_MULTIBLK_NO_INT | ESDHC_FLAG_BIGENDIAN,
};
@@ -327,33 +358,14 @@ int ls1046a_esdhc_start_image(unsigned long r0, unsigned long r1, unsigned long
.sdhci.base = IOMEM(0x01560000),
.socdata = &data,
};
- unsigned long sdram = 0x80000000;
+ void *sdram = (void *)0x80000000;
+ unsigned long size = ALIGN(barebox_image_size + LS1046A_SD_IMAGE_OFFSET, 512);
void (*barebox)(unsigned long, unsigned long, unsigned long) =
- (void *)(sdram + LS1046A_SD_IMAGE_OFFSET);
+ (sdram + LS1046A_SD_IMAGE_OFFSET);
- esdhc_populate_sdhci(&host);
- sdhci_write32(&host.sdhci, IMX_SDHCI_WML, 0);
-
- /*
- * The ROM leaves us here with a clock frequency of around 400kHz. Speed
- * this up a bit. FIXME: The resulting frequency has not yet been verified
- * to work on all cards.
- */
- val = sdhci_read32(&host.sdhci, SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET);
- val &= ~0x0000fff0;
- val |= (8 << 8) | (3 << 4);
- sdhci_write32(&host.sdhci, SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET, val);
-
- sdhci_write32(&host.sdhci, ESDHC_DMA_SYSCTL, ESDHC_SYSCTL_DMA_SNOOP);
-
- ret = esdhc_read_blocks(&host, (void *)sdram,
- ALIGN(barebox_image_size + LS1046A_SD_IMAGE_OFFSET, 512));
- if (ret) {
- pr_err("%s: reading blocks failed with: %d\n", __func__, ret);
+ ret = layerscape_esdhc_load_image(&host, sdram, size, (8 << 8) | (3 << 4));
+ if (ret)
return ret;
- }
-
- sync_caches_for_execution();
printf("Starting barebox\n");
--
2.39.2
^ permalink raw reply [flat|nested] 25+ messages in thread* [PATCH 18/19] mci: imx-esdhc-pbl: implement esdhc xload for ls1028a
2024-01-04 14:17 [PATCH 00/19] ARM: add Layerscape LS1028a support Sascha Hauer
` (16 preceding siblings ...)
2024-01-04 14:17 ` [PATCH 17/19] mci: imx-esdhc-pbl: factor out common function Sascha Hauer
@ 2024-01-04 14:17 ` Sascha Hauer
2024-01-29 17:36 ` Uwe Kleine-König
2024-01-04 14:17 ` [PATCH 19/19] ARM: Layerscape: add basic support for NXP LS1028a RDB Sascha Hauer
18 siblings, 1 reply; 25+ messages in thread
From: Sascha Hauer @ 2024-01-04 14:17 UTC (permalink / raw)
To: Barebox List
This implements esdhc xload support for LS1028a. Unlike LS1046a we use
TF-A rather than obsoleted PPA for EL3, so this code also starts the
TF-A.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/mci/imx-esdhc-pbl.c | 55 +++++++++++++++++++++++++++-
firmware/Kconfig | 3 ++
firmware/Makefile | 1 +
include/mach/layerscape/layerscape.h | 12 ++++++
include/mach/layerscape/xload.h | 4 ++
5 files changed, 74 insertions(+), 1 deletion(-)
diff --git a/drivers/mci/imx-esdhc-pbl.c b/drivers/mci/imx-esdhc-pbl.c
index c13830d726..2c74d101e4 100644
--- a/drivers/mci/imx-esdhc-pbl.c
+++ b/drivers/mci/imx-esdhc-pbl.c
@@ -9,6 +9,8 @@
#include <asm/sections.h>
#include <asm/cache.h>
#include <mach/imx/xload.h>
+#include <firmware.h>
+#include <asm/atf_common.h>
#ifdef CONFIG_ARCH_IMX
#include <mach/imx/atf.h>
#include <mach/imx/imx6-regs.h>
@@ -319,7 +321,8 @@ static int layerscape_esdhc_load_image(struct fsl_esdhc_host *host, void *adr, u
val |= div_val;
sdhci_write32(&host->sdhci, SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET, val);
- sdhci_write32(&host->sdhci, ESDHC_DMA_SYSCTL, ESDHC_SYSCTL_DMA_SNOOP);
+ sdhci_write32(&host->sdhci, ESDHC_DMA_SYSCTL,
+ ESDHC_SYSCTL_DMA_SNOOP | ESDHC_SYSCTL_PERIPHERAL_CLK_SEL);
ret = esdhc_read_blocks(host, adr, size);
if (ret) {
@@ -373,4 +376,54 @@ int ls1046a_esdhc_start_image(unsigned long r0, unsigned long r1, unsigned long
return -EINVAL;
}
+
+static int ls1028a_esdhc_start_image(void __iomem *base, struct dram_regions_info *dram_info)
+{
+ struct esdhc_soc_data data = {
+ .flags = ESDHC_FLAG_MULTIBLK_NO_INT,
+ };
+ struct fsl_esdhc_host host = {
+ .sdhci.base = base,
+ .socdata = &data,
+ };
+ void *sdram = (void *)0x80000000;
+ void (*bl31)(void) = (void *)0xfbe00000;
+ size_t bl31_size;
+ void *bl31_image;
+ struct bl2_to_bl31_params_mem_v2 *params;
+ unsigned long size = ALIGN(barebox_image_size + LS1046A_SD_IMAGE_OFFSET, 512);
+ void (*barebox)(unsigned long, unsigned long, unsigned long) =
+ (sdram + LS1046A_SD_IMAGE_OFFSET);
+ int ret;
+
+ ret = layerscape_esdhc_load_image(&host, sdram, size, 8 << 4);
+ if (ret)
+ return ret;
+
+ get_builtin_firmware_ext(ls1028a_bl31_bin, barebox, &bl31_image, &bl31_size);
+ memcpy(bl31, bl31_image, bl31_size);
+
+ /* Setup an initial stack for EL2 */
+ asm volatile("msr sp_el2, %0" : : "r" ((unsigned long)barebox - 16) : "cc");
+
+ params = bl2_plat_get_bl31_params_v2(0, (uintptr_t)barebox, 0);
+ params->bl31_ep_info.args.arg3 = (unsigned long)dram_info;
+
+ printf("Starting bl31\n");
+
+ bl31_entry_v2((uintptr_t)bl31, ¶ms->bl_params, NULL);
+
+ return -EINVAL;
+}
+
+int ls1028a_esdhc1_start_image(struct dram_regions_info *dram_info)
+{
+ return ls1028a_esdhc_start_image(IOMEM(0x2140000), dram_info);
+}
+
+int ls1028a_esdhc2_start_image(struct dram_regions_info *dram_info)
+{
+ return ls1028a_esdhc_start_image(IOMEM(0x2150000), dram_info);
+}
+
#endif
diff --git a/firmware/Kconfig b/firmware/Kconfig
index 38fbf85555..2785c4aabe 100644
--- a/firmware/Kconfig
+++ b/firmware/Kconfig
@@ -58,4 +58,7 @@ config FIRMWARE_CCBV2_OPTEE
depends on MACH_WEBASTO_CCBV2 && PBL_OPTEE
default y
+config FIRMWARE_LS1028A_ATF
+ bool
+
endmenu
diff --git a/firmware/Makefile b/firmware/Makefile
index 51d98d54bf..9c3ffa4289 100644
--- a/firmware/Makefile
+++ b/firmware/Makefile
@@ -29,6 +29,7 @@ pbl-firmware-$(CONFIG_ARCH_RK3399_OPTEE) += rk3399-op-tee.bin
firmware-$(CONFIG_DRIVER_NET_FSL_FMAN) += fsl_fman_ucode_ls1046_r1.0_106_4_18.bin
firmware-$(CONFIG_ARCH_LAYERSCAPE_PPA) += ppa-ls1046a.bin
+fw-external-$(CONFIG_FIRMWARE_LS1028A_ATF) += ls1028a-bl31.bin
pbl-firmware-$(CONFIG_FIRMWARE_CCBV2_OPTEE) += ccbv2_optee.bin
diff --git a/include/mach/layerscape/layerscape.h b/include/mach/layerscape/layerscape.h
index 95c230b8f3..ceb7b983f6 100644
--- a/include/mach/layerscape/layerscape.h
+++ b/include/mach/layerscape/layerscape.h
@@ -29,4 +29,16 @@ static inline int ls1046a_ppa_init(resource_size_t ppa_start,
}
#endif
+struct dram_region_info {
+ uint64_t addr;
+ uint64_t size;
+};
+#define NUM_DRAM_REGIONS 3
+
+struct dram_regions_info {
+ uint64_t num_dram_regions;
+ int64_t total_dram_size;
+ struct dram_region_info region[NUM_DRAM_REGIONS];
+};
+
#endif /* __MACH_LAYERSCAPE_H */
diff --git a/include/mach/layerscape/xload.h b/include/mach/layerscape/xload.h
index 0aeedc2834..86327c63e6 100644
--- a/include/mach/layerscape/xload.h
+++ b/include/mach/layerscape/xload.h
@@ -3,7 +3,11 @@
#ifndef __MACH_LAYERSCAPE_XLOAD_H
#define __MACH_LAYERSCAPE_XLOAD_H
+struct dram_regions_info;
+
int ls1046a_esdhc_start_image(unsigned long r0, unsigned long r1, unsigned long r2);
+int ls1028a_esdhc1_start_image(struct dram_regions_info *dram_info);
+int ls1028a_esdhc2_start_image(struct dram_regions_info *dram_info);
int ls1046a_qspi_start_image(unsigned long r0, unsigned long r1,
unsigned long r2);
int ls1021a_qspi_start_image(unsigned long r0, unsigned long r1,
--
2.39.2
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [PATCH 18/19] mci: imx-esdhc-pbl: implement esdhc xload for ls1028a
2024-01-04 14:17 ` [PATCH 18/19] mci: imx-esdhc-pbl: implement esdhc xload for ls1028a Sascha Hauer
@ 2024-01-29 17:36 ` Uwe Kleine-König
2024-01-30 7:11 ` Sascha Hauer
0 siblings, 1 reply; 25+ messages in thread
From: Uwe Kleine-König @ 2024-01-29 17:36 UTC (permalink / raw)
To: Sascha Hauer; +Cc: Barebox List
[-- Attachment #1: Type: text/plain, Size: 1239 bytes --]
Hello Sascha,
On Thu, Jan 04, 2024 at 03:17:45PM +0100, Sascha Hauer wrote:
> diff --git a/drivers/mci/imx-esdhc-pbl.c b/drivers/mci/imx-esdhc-pbl.c
> index c13830d726..2c74d101e4 100644
> --- a/drivers/mci/imx-esdhc-pbl.c
> +++ b/drivers/mci/imx-esdhc-pbl.c
> @@ -9,6 +9,8 @@
> #include <asm/sections.h>
> #include <asm/cache.h>
> #include <mach/imx/xload.h>
> +#include <firmware.h>
> +#include <asm/atf_common.h>
> #ifdef CONFIG_ARCH_IMX
> #include <mach/imx/atf.h>
> #include <mach/imx/imx6-regs.h>
> @@ -319,7 +321,8 @@ static int layerscape_esdhc_load_image(struct fsl_esdhc_host *host, void *adr, u
> val |= div_val;
> sdhci_write32(&host->sdhci, SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET, val);
>
> - sdhci_write32(&host->sdhci, ESDHC_DMA_SYSCTL, ESDHC_SYSCTL_DMA_SNOOP);
> + sdhci_write32(&host->sdhci, ESDHC_DMA_SYSCTL,
> + ESDHC_SYSCTL_DMA_SNOOP | ESDHC_SYSCTL_PERIPHERAL_CLK_SEL);
This affects ls1046, too. Is this intended?
Best regards
Uwe
> ret = esdhc_read_blocks(host, adr, size);
> if (ret) {
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | https://www.pengutronix.de/ |
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [PATCH 18/19] mci: imx-esdhc-pbl: implement esdhc xload for ls1028a
2024-01-29 17:36 ` Uwe Kleine-König
@ 2024-01-30 7:11 ` Sascha Hauer
0 siblings, 0 replies; 25+ messages in thread
From: Sascha Hauer @ 2024-01-30 7:11 UTC (permalink / raw)
To: Uwe Kleine-König; +Cc: Barebox List
On Mon, Jan 29, 2024 at 06:36:29PM +0100, Uwe Kleine-König wrote:
> Hello Sascha,
>
> On Thu, Jan 04, 2024 at 03:17:45PM +0100, Sascha Hauer wrote:
> > diff --git a/drivers/mci/imx-esdhc-pbl.c b/drivers/mci/imx-esdhc-pbl.c
> > index c13830d726..2c74d101e4 100644
> > --- a/drivers/mci/imx-esdhc-pbl.c
> > +++ b/drivers/mci/imx-esdhc-pbl.c
> > @@ -9,6 +9,8 @@
> > #include <asm/sections.h>
> > #include <asm/cache.h>
> > #include <mach/imx/xload.h>
> > +#include <firmware.h>
> > +#include <asm/atf_common.h>
> > #ifdef CONFIG_ARCH_IMX
> > #include <mach/imx/atf.h>
> > #include <mach/imx/imx6-regs.h>
> > @@ -319,7 +321,8 @@ static int layerscape_esdhc_load_image(struct fsl_esdhc_host *host, void *adr, u
> > val |= div_val;
> > sdhci_write32(&host->sdhci, SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET, val);
> >
> > - sdhci_write32(&host->sdhci, ESDHC_DMA_SYSCTL, ESDHC_SYSCTL_DMA_SNOOP);
> > + sdhci_write32(&host->sdhci, ESDHC_DMA_SYSCTL,
> > + ESDHC_SYSCTL_DMA_SNOOP | ESDHC_SYSCTL_PERIPHERAL_CLK_SEL);
>
> This affects ls1046, too. Is this intended?
It's not intended to do this in this patch, nevertheless I beliebe it's
the right thing to do also for LS1046a
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH 19/19] ARM: Layerscape: add basic support for NXP LS1028a RDB
2024-01-04 14:17 [PATCH 00/19] ARM: add Layerscape LS1028a support Sascha Hauer
` (17 preceding siblings ...)
2024-01-04 14:17 ` [PATCH 18/19] mci: imx-esdhc-pbl: implement esdhc xload for ls1028a Sascha Hauer
@ 2024-01-04 14:17 ` Sascha Hauer
2024-01-04 16:32 ` Uwe Kleine-König
18 siblings, 1 reply; 25+ messages in thread
From: Sascha Hauer @ 2024-01-04 14:17 UTC (permalink / raw)
To: Barebox List; +Cc: Uwe Kleine-König
From: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
The NXP LS1028a RDB is a LS1028a Eval board. Currently supported are
SD/MMC, ethernet and SD image generation.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/Makefile | 1 +
arch/arm/boards/ls1028ardb/Makefile | 5 +
arch/arm/boards/ls1028ardb/board.c | 30 ++++
arch/arm/boards/ls1028ardb/lowlevel.c | 142 ++++++++++++++++++
arch/arm/boards/ls1028ardb/ls1028ardb_pbi.cfg | 14 ++
.../boards/ls1028ardb/ls1028ardb_rcw_sd.cfg | 14 ++
arch/arm/boards/ls1028ardb/start.S | 19 +++
arch/arm/configs/layerscape_defconfig | 5 +-
arch/arm/dts/Makefile | 1 +
arch/arm/dts/fsl-ls1028a-rdb.dts | 12 ++
arch/arm/mach-layerscape/Kconfig | 15 +-
images/Makefile.layerscape | 9 ++
12 files changed, 264 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/boards/ls1028ardb/Makefile
create mode 100644 arch/arm/boards/ls1028ardb/board.c
create mode 100644 arch/arm/boards/ls1028ardb/lowlevel.c
create mode 100644 arch/arm/boards/ls1028ardb/ls1028ardb_pbi.cfg
create mode 100644 arch/arm/boards/ls1028ardb/ls1028ardb_rcw_sd.cfg
create mode 100644 arch/arm/boards/ls1028ardb/start.S
create mode 100644 arch/arm/dts/fsl-ls1028a-rdb.dts
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index d27252c4a7..875d011573 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -187,6 +187,7 @@ obj-$(CONFIG_MACH_ZII_IMX8MQ_DEV) += zii-imx8mq-dev/
obj-$(CONFIG_MACH_ZII_VF610_DEV) += zii-vf610-dev/
obj-$(CONFIG_MACH_ZII_IMX7D_DEV) += zii-imx7d-dev/
obj-$(CONFIG_MACH_WAGO_PFC_AM35XX) += wago-pfc-am35xx/
+obj-$(CONFIG_MACH_LS1028ARDB) += ls1028ardb/
obj-$(CONFIG_MACH_LS1046ARDB) += ls1046ardb/
obj-$(CONFIG_MACH_TQMLS1046A) += tqmls1046a/
obj-$(CONFIG_MACH_LS1021AIOT) += ls1021aiot/
diff --git a/arch/arm/boards/ls1028ardb/Makefile b/arch/arm/boards/ls1028ardb/Makefile
new file mode 100644
index 0000000000..df60a21844
--- /dev/null
+++ b/arch/arm/boards/ls1028ardb/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+lwl-y += lowlevel.o
+lwl-y += start.o
+obj-y += board.o
diff --git a/arch/arm/boards/ls1028ardb/board.c b/arch/arm/boards/ls1028ardb/board.c
new file mode 100644
index 0000000000..137f5753ca
--- /dev/null
+++ b/arch/arm/boards/ls1028ardb/board.c
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <deep-probe.h>
+#include <bootsource.h>
+#include <driver.h>
+#include <init.h>
+#include <of.h>
+#include <asm/memory.h>
+#include <mach/layerscape/layerscape.h>
+#include <linux/sizes.h>
+
+static int ls1028ardb_probe(struct device *dev)
+{
+ arm_add_mem_device("ram1", LS1028A_DDR_SDRAM_HIGHMEM_BASE, SZ_2G);
+
+ return 0;
+}
+
+static const struct of_device_id ls1028a_of_match[] = {
+ { .compatible = "fsl,ls1028a-rdb" },
+ { /* sentinel */ },
+};
+BAREBOX_DEEP_PROBE_ENABLE(ls1028a_of_match);
+
+static struct driver ls1028ardb_board_driver = {
+ .name = "ls1028a-rdb",
+ .probe = ls1028ardb_probe,
+ .of_compatible = ls1028a_of_match,
+};
+device_platform_driver(ls1028ardb_board_driver);
diff --git a/arch/arm/boards/ls1028ardb/lowlevel.c b/arch/arm/boards/ls1028ardb/lowlevel.c
new file mode 100644
index 0000000000..77b5a78852
--- /dev/null
+++ b/arch/arm/boards/ls1028ardb/lowlevel.c
@@ -0,0 +1,142 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <debug_ll.h>
+#include <ddr_spd.h>
+#include <image-metadata.h>
+#include <platform_data/mmc-esdhc-imx.h>
+#include <soc/fsl/fsl_ddr_sdram.h>
+#include <soc/fsl/immap_lsch2.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+#include <asm/syscounter.h>
+#include <asm/cache.h>
+#include <mach/layerscape/lowlevel.h>
+#include <mach/layerscape/xload.h>
+#include <mach/layerscape/errata.h>
+#include <mach/layerscape/layerscape.h>
+#include <linux/bitfield.h>
+
+static struct fsl_ddr_controller ddrc = {
+ .memctl_opts.ddrtype = SDRAM_TYPE_DDR4,
+ .base = IOMEM(LSCH2_DDR_ADDR),
+ .ddr_freq = 1600000000,
+ .erratum_A009942 = 1,
+ .erratum_A009663 = 1,
+ .chip_selects_per_ctrl = 4,
+ .fsl_ddr_config_reg = {
+ .cs[0].bnds = 0x000000ff,
+ .cs[0].config = 0x80040422,
+ .cs[0].config_2 = 0,
+ .cs[1].bnds = 0,
+ .cs[1].config = 0,
+ .cs[1].config_2 = 0,
+
+ .timing_cfg_3 = 0x01111000,
+ .timing_cfg_0 = 0xd0550018,
+ .timing_cfg_1 = 0xFAFC0C42,
+ .timing_cfg_2 = 0x0048c114,
+ .ddr_sdram_cfg = 0xe50c000c,
+ .ddr_sdram_cfg_2 = 0x00401110,
+ .ddr_sdram_mode = 0x01010230,
+ .ddr_sdram_mode_2 = 0x0,
+
+ .ddr_sdram_md_cntl = 0x0600001f,
+ .ddr_sdram_interval = 0x18600618,
+ .ddr_data_init = 0xdeadbeef,
+
+ .ddr_sdram_clk_cntl = 0x02000000,
+ .ddr_init_addr = 0,
+ .ddr_init_ext_addr = 0,
+
+ .timing_cfg_4 = 0x00000002,
+ .timing_cfg_5 = 0x07401400,
+ .timing_cfg_6 = 0x0,
+ .timing_cfg_7 = 0x23300000,
+
+ .ddr_zq_cntl = 0x8A090705,
+ .ddr_wrlvl_cntl = 0x86550607,
+ .ddr_sr_cntr = 0,
+ .ddr_sdram_rcw_1 = 0,
+ .ddr_sdram_rcw_2 = 0,
+ .ddr_wrlvl_cntl_2 = 0x0708080A,
+ .ddr_wrlvl_cntl_3 = 0x0A0B0C09,
+
+ .ddr_sdram_mode_9 = 0x00000400,
+ .ddr_sdram_mode_10 = 0x04000000,
+
+ .timing_cfg_8 = 0x06115600,
+
+ .dq_map_0 = 0x5b65b658,
+ .dq_map_1 = 0xd96d8000,
+ .dq_map_2 = 0,
+ .dq_map_3 = 0x01600000,
+
+ .ddr_cdr1 = 0x80040000,
+ .ddr_cdr2 = 0x000000C1
+ },
+};
+
+extern char __dtb_z_fsl_ls1028a_rdb_start[];
+
+#define MEM_PLL_RAT GENMASK(15, 10)
+
+static unsigned long get_ddr_freq(void)
+{
+ unsigned long freq = 100000000;
+ u32 rcwsr1 = readl(0x1e00100);
+ u32 mult;
+
+ mult = FIELD_GET(MEM_PLL_RAT, rcwsr1);
+
+ return freq * mult;
+}
+
+struct dram_regions_info dram_info = {
+ .num_dram_regions = 2,
+ .total_dram_size = SZ_4G,
+ .region = {
+ {
+ .addr = LS1028A_DDR_SDRAM_BASE,
+ .size = SZ_2G,
+ }, {
+ .addr = LS1028A_DDR_SDRAM_HIGHMEM_BASE,
+ .size = SZ_2G,
+ },
+ },
+};
+
+static noinline __noreturn void ls1028ardb_r_entry(unsigned long memsize)
+{
+ unsigned long membase = LS1028A_DDR_SDRAM_BASE;
+
+ if (get_pc() >= membase)
+ barebox_arm_entry(membase, SZ_2G - SZ_64M - SZ_2M,
+ __dtb_z_fsl_ls1028a_rdb_start);
+
+ arm_cpu_lowlevel_init();
+ ls1028a_init_lowlevel();
+ ddrc.ddr_freq = get_ddr_freq();
+
+ fsl_ddr_set_memctl_regs(&ddrc, 0, true);
+
+ ls1028a_tzc400_init(SZ_4G);
+
+ ls1028a_errata_post_ddr();
+
+ ls1028a_esdhc1_start_image(&dram_info);
+
+ hang();
+}
+
+void ls1028ardb_entry(unsigned long r0, unsigned long r1, unsigned long r2);
+
+__noreturn void ls1028ardb_entry(unsigned long r0, unsigned long r1, unsigned long r2)
+{
+ ls1028a_uart_setup(IOMEM(LSCH2_NS16550_COM1));
+
+ relocate_to_current_adr();
+ setup_c();
+
+ ls1028ardb_r_entry(r0);
+}
diff --git a/arch/arm/boards/ls1028ardb/ls1028ardb_pbi.cfg b/arch/arm/boards/ls1028ardb/ls1028ardb_pbi.cfg
new file mode 100644
index 0000000000..53cfb20327
--- /dev/null
+++ b/arch/arm/boards/ls1028ardb/ls1028ardb_pbi.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+31e00400 18010000
+31e00404 00000000
+33400890 00800401
+33500890 00800401
+334008bc 00000001
+33400154 47474747
+33400158 47474747
+335008bc 00000001
+33500154 47474747
+33500158 47474747
+334008bc 00000000
+335008bc 00000000
diff --git a/arch/arm/boards/ls1028ardb/ls1028ardb_rcw_sd.cfg b/arch/arm/boards/ls1028ardb/ls1028ardb_rcw_sd.cfg
new file mode 100644
index 0000000000..2183991112
--- /dev/null
+++ b/arch/arm/boards/ls1028ardb/ls1028ardb_rcw_sd.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+#PBL preamble and RCW header
+aa55aa55 80100000
+# RCW
+34004010 00000030 00000000 00000000
+00000000 00bf0000 0030c000 00000000
+01e03150 00002580 00000000 00003496
+00000000 00000010 00000000 00000000
+00000000 00000000 00000000 00000000
+00000000 00000000 00000000 00000000
+00000000 00000000 200e705a 00000000
+bb580000 00000000 00000000 00000000
+
diff --git a/arch/arm/boards/ls1028ardb/start.S b/arch/arm/boards/ls1028ardb/start.S
new file mode 100644
index 0000000000..fd410b744a
--- /dev/null
+++ b/arch/arm/boards/ls1028ardb/start.S
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#include <linux/linkage.h>
+#include <asm/barebox-arm64.h>
+#include <asm/assembler64.h>
+
+#define STACK_TOP 0x18040000
+
+ENTRY_PROC(start_ls1028ardb)
+ switch_el x3, 3f, 2f, 1f
+3:
+ mov x3, #STACK_TOP
+ mov sp, x3
+ b ls1028ardb_entry
+2:
+1:
+ mov x3, 0x90000000
+ mov sp, x3
+ b ls1028ardb_entry
+ENTRY_PROC_END(start_ls1028ardb)
diff --git a/arch/arm/configs/layerscape_defconfig b/arch/arm/configs/layerscape_defconfig
index 35b254f139..b26eca66c3 100644
--- a/arch/arm/configs/layerscape_defconfig
+++ b/arch/arm/configs/layerscape_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARCH_LAYERSCAPE=y
CONFIG_ARCH_LAYERSCAPE_PPA=y
+CONFIG_MACH_LS1028ARDB=y
CONFIG_MACH_LS1046ARDB=y
CONFIG_MACH_TQMLS1046A=y
CONFIG_64BIT=y
@@ -82,6 +83,7 @@ CONFIG_NET=y
CONFIG_NET_NETCONSOLE=y
CONFIG_OF_BAREBOX_DRIVERS=y
CONFIG_DRIVER_SERIAL_NS16550=y
+CONFIG_DRIVER_NET_FSL_ENETC=y
CONFIG_DRIVER_NET_FSL_FMAN=y
CONFIG_DP83867_PHY=y
CONFIG_REALTEK_PHY=y
@@ -111,12 +113,13 @@ CONFIG_WATCHDOG_IMX=y
CONFIG_GPIO_PCA953X=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED=y
+CONFIG_PCI_LAYERSCAPE=y
+CONFIG_PCI_ECAM_GENERIC=y
CONFIG_FS_EXT4=y
CONFIG_FS_TFTP=y
CONFIG_FS_NFS=y
CONFIG_FS_FAT=y
CONFIG_FS_FAT_WRITE=y
-CONFIG_FS_FAT_LFN=y
CONFIG_FS_UBIFS=y
CONFIG_FS_UBIFS_COMPRESSION_LZO=y
CONFIG_ZLIB=y
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 04af3bd646..301014eaff 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -214,6 +214,7 @@ lwl-$(CONFIG_MACH_XILINX_ZCU106) += zynqmp-zcu106-revA.dtb.o
lwl-$(CONFIG_MACH_ZII_IMX7D_DEV) += imx7d-zii-rpu2.dtb.o imx7d-zii-rmu2.dtb.o
lwl-$(CONFIG_MACH_WAGO_PFC_AM35XX) += am35xx-pfc-750_820x.dtb.o
+lwl-$(CONFIG_MACH_LS1028ARDB) += fsl-ls1028a-rdb.dtb.o
lwl-$(CONFIG_MACH_LS1046ARDB) += fsl-ls1046a-rdb.dtb.o
lwl-$(CONFIG_MACH_TQMLS1046A) += fsl-tqmls1046a-mbls10xxa.dtb.o
lwl-$(CONFIG_MACH_LS1021AIOT) += fsl-ls1021a-iot.dtb.o
diff --git a/arch/arm/dts/fsl-ls1028a-rdb.dts b/arch/arm/dts/fsl-ls1028a-rdb.dts
new file mode 100644
index 0000000000..1667a42e45
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1028a-rdb.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <arm64/freescale/fsl-ls1028a-rdb.dts>
+
+/ {
+ memory@80000000 {
+ /* Upstream dts has size 4GiB here which is wrong */
+ reg = <0x0 0x80000000 0x0 0x80000000>;
+ };
+};
diff --git a/arch/arm/mach-layerscape/Kconfig b/arch/arm/mach-layerscape/Kconfig
index 52527f0c15..5658a63b33 100644
--- a/arch/arm/mach-layerscape/Kconfig
+++ b/arch/arm/mach-layerscape/Kconfig
@@ -7,7 +7,6 @@ config ARCH_LAYERSCAPE_PPA
select ARM_PSCI_OF
select ARM_SMCCC
select FITIMAGE
- bool
help
The "Primary Protected Application" (PPA) is a PSCI compliant firmware
distributed by NXP. It is needed to start the secondary cores on
@@ -15,12 +14,24 @@ config ARCH_LAYERSCAPE_PPA
work properly. The precompiled firmware images can be found here:
https://github.com/NXP/qoriq-ppa-binary
-config ARCH_LS1046
+config ARCH_LS1028
+ bool
select CPU_V8
+ select SYS_SUPPORTS_64BIT_KERNEL
+ select ARM_ATF
+ select FIRMWARE_LS1028A_ATF
+
+config ARCH_LS1046
bool
+ select CPU_V8
+ select SYS_SUPPORTS_64BIT_KERNEL
if 64BIT
+config MACH_LS1028ARDB
+ bool "QorIQ LS1028A Reference Design Board"
+ select ARCH_LS1028
+
config MACH_LS1046ARDB
bool "QorIQ LS1046A Reference Design Board"
select ARCH_LS1046
diff --git a/images/Makefile.layerscape b/images/Makefile.layerscape
index e36dc5000a..9cb88270d7 100644
--- a/images/Makefile.layerscape
+++ b/images/Makefile.layerscape
@@ -21,6 +21,15 @@ quiet_cmd_lspbl_spi_image = LSPBL-SPI-IMG $@
$(objtree)/scripts/pblimage -o $@ -r $(lspbl-rcw-tmp) -s \
-c $(2) -m $($(patsubst $(obj)/%.pblb,PBL_CODE_SIZE_%,$<)) -p $(lspbl-pbi-tmp) -i $<
+pbl-$(CONFIG_MACH_LS1028ARDB) += start_ls1028ardb.pbl
+
+$(obj)/barebox-ls1028ardb-sd.image: $(obj)/start_ls1028ardb.pblb \
+ $(board)/ls1028ardb/ls1028ardb_rcw_sd.cfg \
+ $(board)/ls1028ardb/ls1028ardb_pbi.cfg
+ $(call if_changed,lspbl_image,ls1028a)
+
+image-$(CONFIG_MACH_LS1028ARDB) += barebox-ls1028ardb-sd.image
+
pbl-$(CONFIG_MACH_LS1046ARDB) += start_ls1046ardb.pbl
$(obj)/barebox-ls1046ardb-sd.image: $(obj)/start_ls1046ardb.pblb \
--
2.39.2
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