* [PATCH 01/10] ARM: Layerscape: consolidate initcalls into one
2024-01-09 9:15 [PATCH 00/10] Add more Layerscape LS1028a stuff Sascha Hauer
@ 2024-01-09 9:15 ` Sascha Hauer
2024-01-09 9:15 ` [PATCH 02/10] ARM: Layerscape: LS1028a: reserve DDR region for TF-A Sascha Hauer
` (8 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: Sascha Hauer @ 2024-01-09 9:15 UTC (permalink / raw)
To: Barebox List
For Layerscape we have multiple initcalls in the arch directory.
Consolidate these into one initcall which detects the SoC type once
and calls the appropriate init functions. This makes it easier to
add future init steps and also we reduce the number of string
comparisons.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-layerscape/boot.c | 13 ++--
arch/arm/mach-layerscape/icid.c | 9 +--
arch/arm/mach-layerscape/ls102xa_stream_id.c | 8 +-
arch/arm/mach-layerscape/pblimage.c | 6 +-
arch/arm/mach-layerscape/restart.c | 8 +-
arch/arm/mach-layerscape/soc.c | 77 ++++++++++++++++++++
include/mach/layerscape/layerscape.h | 11 +++
7 files changed, 100 insertions(+), 32 deletions(-)
diff --git a/arch/arm/mach-layerscape/boot.c b/arch/arm/mach-layerscape/boot.c
index da61763bd5..26a7a1434a 100644
--- a/arch/arm/mach-layerscape/boot.c
+++ b/arch/arm/mach-layerscape/boot.c
@@ -32,13 +32,12 @@ enum bootsource ls1021a_bootsource_get(void)
return ls1046a_bootsource_get();
}
-static int layerscape_bootsource_init(void)
+void ls1021a_bootsource_init(void)
{
- if (of_machine_is_compatible("fsl,ls1046a"))
- bootsource_set_raw(ls1046a_bootsource_get(), BOOTSOURCE_INSTANCE_UNKNOWN);
- if (of_machine_is_compatible("fsl,ls1021a"))
- bootsource_set_raw(ls1021a_bootsource_get(), BOOTSOURCE_INSTANCE_UNKNOWN);
+ bootsource_set_raw(ls1021a_bootsource_get(), BOOTSOURCE_INSTANCE_UNKNOWN);
+}
- return 0;
+void ls1046a_bootsource_init(void)
+{
+ bootsource_set_raw(ls1046a_bootsource_get(), BOOTSOURCE_INSTANCE_UNKNOWN);
}
-coredevice_initcall(layerscape_bootsource_init);
diff --git a/arch/arm/mach-layerscape/icid.c b/arch/arm/mach-layerscape/icid.c
index d1d623416a..f5188fc91e 100644
--- a/arch/arm/mach-layerscape/icid.c
+++ b/arch/arm/mach-layerscape/icid.c
@@ -7,6 +7,7 @@
#include <soc/fsl/immap_lsch2.h>
#include <soc/fsl/fsl_qbman.h>
#include <soc/fsl/fsl_fman.h>
+#include <mach/layerscape/layerscape.h>
/*
* Stream IDs on Chassis-2 (for example ls1043a, ls1046a, ls1012) devices
@@ -530,14 +531,11 @@ static int icid_of_fixup(struct device_node *root, void *context)
return 0;
}
-static int layerscape_setup_icids(void)
+void ls1046a_setup_icids(void)
{
int i;
struct ccsr_fman *fm = (void *)LSCH2_FM1_ADDR;
- if (!of_machine_is_compatible("fsl,ls1046a"))
- return 0;
-
/* setup general icid offsets */
for (i = 0; i < ARRAY_SIZE(icid_tbl_ls1046a); i++) {
struct icid_id_table *icid = &icid_tbl_ls1046a[i];
@@ -556,7 +554,4 @@ static int layerscape_setup_icids(void)
setup_qbman_portals();
of_register_fixup(icid_of_fixup, NULL);
-
- return 0;
}
-coredevice_initcall(layerscape_setup_icids);
diff --git a/arch/arm/mach-layerscape/ls102xa_stream_id.c b/arch/arm/mach-layerscape/ls102xa_stream_id.c
index c47c463b48..60723ce2e7 100644
--- a/arch/arm/mach-layerscape/ls102xa_stream_id.c
+++ b/arch/arm/mach-layerscape/ls102xa_stream_id.c
@@ -43,13 +43,7 @@ ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num)
}
}
-static int ls102xa_smmu_stream_id_init(void)
+void ls102xa_smmu_stream_id_init(void)
{
- if (!of_machine_is_compatible("fsl,ls1021a"))
- return 0;
-
ls102xa_config_smmu_stream_id(dev_stream_id, ARRAY_SIZE(dev_stream_id));
-
- return 0;
}
-mmu_initcall(ls102xa_smmu_stream_id_init);
diff --git a/arch/arm/mach-layerscape/pblimage.c b/arch/arm/mach-layerscape/pblimage.c
index 26345af276..5a525f0933 100644
--- a/arch/arm/mach-layerscape/pblimage.c
+++ b/arch/arm/mach-layerscape/pblimage.c
@@ -7,6 +7,7 @@
#include <init.h>
#include <memory.h>
#include <linux/sizes.h>
+#include <mach/layerscape/layerscape.h>
#define BAREBOX_STAGE2_OFFSET SZ_128K
@@ -50,11 +51,8 @@ static struct image_handler image_handler_layerscape_qspi_pbl_image = {
.filetype = filetype_layerscape_qspi_image,
};
-static int layerscape_register_pbl_image_handler(void)
+void layerscape_register_pbl_image_handler(void)
{
register_image_handler(&image_handler_layerscape_pbl_image);
register_image_handler(&image_handler_layerscape_qspi_pbl_image);
-
- return 0;
}
-late_initcall(layerscape_register_pbl_image_handler);
diff --git a/arch/arm/mach-layerscape/restart.c b/arch/arm/mach-layerscape/restart.c
index e8bd041ebf..a6daa9b677 100644
--- a/arch/arm/mach-layerscape/restart.c
+++ b/arch/arm/mach-layerscape/restart.c
@@ -18,13 +18,7 @@ static void ls102xa_restart(struct restart_handler *rst)
hang();
}
-static int restart_register_feature(void)
+void ls1021a_restart_register_feature(void)
{
- if (!of_machine_is_compatible("fsl,ls1021a"))
- return 0;
-
restart_handler_register_fn("soc-reset", ls102xa_restart);
-
- return 0;
}
-coredevice_initcall(restart_register_feature);
diff --git a/arch/arm/mach-layerscape/soc.c b/arch/arm/mach-layerscape/soc.c
index 2d9a2b4629..4d4ef05d4b 100644
--- a/arch/arm/mach-layerscape/soc.c
+++ b/arch/arm/mach-layerscape/soc.c
@@ -1,7 +1,11 @@
// SPDX-License-Identifier: GPL-2.0-only
#include <soc/fsl/scfg.h>
#include <io.h>
+#include <init.h>
+#include <memory.h>
#include <linux/bug.h>
+#include <mach/layerscape/layerscape.h>
+#include <of.h>
static enum scfg_endianess scfg_endianess = SCFG_ENDIANESS_INVALID;
@@ -54,3 +58,76 @@ void scfg_init(enum scfg_endianess endianess)
{
scfg_endianess = endianess;
}
+
+static int layerscape_soc_from_dt(void)
+{
+ if (of_machine_is_compatible("fsl,ls1021a"))
+ return LAYERSCAPE_SOC_LS1021A;
+ if (of_machine_is_compatible("fsl,ls1028a"))
+ return LAYERSCAPE_SOC_LS1028A;
+ if (of_machine_is_compatible("fsl,ls1046a"))
+ return LAYERSCAPE_SOC_LS1046A;
+
+ return 0;
+}
+
+static int ls1021a_init(void)
+{
+ if (!IS_ENABLED(CONFIG_ARCH_LS1021))
+ return -EINVAL;
+
+ ls1021a_bootsource_init();
+ ls102xa_smmu_stream_id_init();
+ layerscape_register_pbl_image_handler();
+ ls1021a_restart_register_feature();
+
+ return 0;
+}
+
+static int ls1028a_init(void)
+{
+ if (!IS_ENABLED(CONFIG_ARCH_LS1028))
+ return -EINVAL;
+
+ layerscape_register_pbl_image_handler();
+
+ return 0;
+}
+
+static int ls1046a_init(void)
+{
+ if (!IS_ENABLED(CONFIG_ARCH_LS1046))
+ return -EINVAL;
+
+ ls1046a_bootsource_init();
+ ls1046a_setup_icids();
+ layerscape_register_pbl_image_handler();
+
+ return 0;
+}
+
+static int __layerscape_soc_type;
+
+static int layerscape_init(void)
+{
+ struct device_node *root;
+
+ root = of_get_root_node();
+ if (root) {
+ __layerscape_soc_type = layerscape_soc_from_dt();
+ if (!__layerscape_soc_type)
+ return 0;
+ }
+
+ switch (__layerscape_soc_type) {
+ case LAYERSCAPE_SOC_LS1021A:
+ return ls1021a_init();
+ case LAYERSCAPE_SOC_LS1028A:
+ return ls1028a_init();
+ case LAYERSCAPE_SOC_LS1046A:
+ return ls1046a_init();
+ }
+
+ return 0;
+}
+postcore_initcall(layerscape_init);
diff --git a/include/mach/layerscape/layerscape.h b/include/mach/layerscape/layerscape.h
index ceb7b983f6..a048b7ef9e 100644
--- a/include/mach/layerscape/layerscape.h
+++ b/include/mach/layerscape/layerscape.h
@@ -19,6 +19,10 @@
enum bootsource ls1046a_bootsource_get(void);
enum bootsource ls1021a_bootsource_get(void);
+#define LAYERSCAPE_SOC_LS1021A 1021
+#define LAYERSCAPE_SOC_LS1028A 1028
+#define LAYERSCAPE_SOC_LS1046A 1046
+
#ifdef CONFIG_ARCH_LAYERSCAPE_PPA
int ls1046a_ppa_init(resource_size_t ppa_start, resource_size_t ppa_size);
#else
@@ -41,4 +45,11 @@ struct dram_regions_info {
struct dram_region_info region[NUM_DRAM_REGIONS];
};
+void ls1021a_bootsource_init(void);
+void ls1046a_bootsource_init(void);
+void layerscape_register_pbl_image_handler(void);
+void ls102xa_smmu_stream_id_init(void);
+void ls1021a_restart_register_feature(void);
+void ls1046a_setup_icids(void);
+
#endif /* __MACH_LAYERSCAPE_H */
--
2.39.2
^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH 02/10] ARM: Layerscape: LS1028a: reserve DDR region for TF-A
2024-01-09 9:15 [PATCH 00/10] Add more Layerscape LS1028a stuff Sascha Hauer
2024-01-09 9:15 ` [PATCH 01/10] ARM: Layerscape: consolidate initcalls into one Sascha Hauer
@ 2024-01-09 9:15 ` Sascha Hauer
2024-01-09 9:37 ` Ahmad Fatoum
2024-01-09 9:15 ` [PATCH 03/10] ARM: Layerscape: icid: make readonly arrays const Sascha Hauer
` (7 subsequent siblings)
9 siblings, 1 reply; 18+ messages in thread
From: Sascha Hauer @ 2024-01-09 9:15 UTC (permalink / raw)
To: Barebox List
On LS1028a the TF-A is placed in DDR, so we have to reserve the region
in order to keep Linux away from it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-layerscape/soc.c | 2 ++
drivers/mci/imx-esdhc-pbl.c | 3 ++-
include/mach/layerscape/layerscape.h | 8 ++++++++
3 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-layerscape/soc.c b/arch/arm/mach-layerscape/soc.c
index 4d4ef05d4b..5f9d0d5171 100644
--- a/arch/arm/mach-layerscape/soc.c
+++ b/arch/arm/mach-layerscape/soc.c
@@ -91,6 +91,8 @@ static int ls1028a_init(void)
layerscape_register_pbl_image_handler();
+ reserve_sdram_region("tfa", LS1028A_TFA_RESERVED_START, LS1028A_TFA_RESERVED_SIZE);
+
return 0;
}
diff --git a/drivers/mci/imx-esdhc-pbl.c b/drivers/mci/imx-esdhc-pbl.c
index 2c74d101e4..2d071eaca8 100644
--- a/drivers/mci/imx-esdhc-pbl.c
+++ b/drivers/mci/imx-esdhc-pbl.c
@@ -21,6 +21,7 @@
#endif
#ifdef CONFIG_ARCH_LAYERSCAPE
#include <mach/layerscape/xload.h>
+#include <mach/layerscape/layerscape.h>
#endif
#include "sdhci.h"
#include "imx-esdhc.h"
@@ -387,7 +388,7 @@ static int ls1028a_esdhc_start_image(void __iomem *base, struct dram_regions_inf
.socdata = &data,
};
void *sdram = (void *)0x80000000;
- void (*bl31)(void) = (void *)0xfbe00000;
+ void (*bl31)(void) = (void *)LS1028A_TFA_RESERVED_START;
size_t bl31_size;
void *bl31_image;
struct bl2_to_bl31_params_mem_v2 *params;
diff --git a/include/mach/layerscape/layerscape.h b/include/mach/layerscape/layerscape.h
index a048b7ef9e..6f420dd4f4 100644
--- a/include/mach/layerscape/layerscape.h
+++ b/include/mach/layerscape/layerscape.h
@@ -3,6 +3,8 @@
#ifndef __MACH_LAYERSCAPE_H
#define __MACH_LAYERSCAPE_H
+#include <linux/sizes.h>
+
#define LS1046A_DDR_SDRAM_BASE 0x80000000
#define LS1046A_DDR_FREQ 2100000000
@@ -16,6 +18,12 @@
#define LS1028A_SP_SHARED_DRAM_SIZE SZ_2M
#define LS1028A_TZC400_BASE 0x01100000
+#define LS1028A_TFA_SIZE SZ_64M
+#define LS1028A_TFA_SHRD SZ_2M
+#define LS1028A_TFA_RESERVED_SIZE (LS1028A_TFA_SIZE + LS1028A_TFA_SHRD)
+#define LS1028A_TFA_RESERVED_START (0x100000000 - LS1028A_TFA_RESERVED_SIZE)
+#define LS1028A_TFA_START (0x100000000 - LS1028A_TFA_SIZE)
+
enum bootsource ls1046a_bootsource_get(void);
enum bootsource ls1021a_bootsource_get(void);
--
2.39.2
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH 02/10] ARM: Layerscape: LS1028a: reserve DDR region for TF-A
2024-01-09 9:15 ` [PATCH 02/10] ARM: Layerscape: LS1028a: reserve DDR region for TF-A Sascha Hauer
@ 2024-01-09 9:37 ` Ahmad Fatoum
2024-01-09 10:25 ` Sascha Hauer
0 siblings, 1 reply; 18+ messages in thread
From: Ahmad Fatoum @ 2024-01-09 9:37 UTC (permalink / raw)
To: Sascha Hauer, Barebox List
On 09.01.24 10:15, Sascha Hauer wrote:
> On LS1028a the TF-A is placed in DDR, so we have to reserve the region
> in order to keep Linux away from it.
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> arch/arm/mach-layerscape/soc.c | 2 ++
> drivers/mci/imx-esdhc-pbl.c | 3 ++-
> include/mach/layerscape/layerscape.h | 8 ++++++++
> 3 files changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-layerscape/soc.c b/arch/arm/mach-layerscape/soc.c
> index 4d4ef05d4b..5f9d0d5171 100644
> --- a/arch/arm/mach-layerscape/soc.c
> +++ b/arch/arm/mach-layerscape/soc.c
> @@ -91,6 +91,8 @@ static int ls1028a_init(void)
>
> layerscape_register_pbl_image_handler();
>
> + reserve_sdram_region("tfa", LS1028A_TFA_RESERVED_START, LS1028A_TFA_RESERVED_SIZE);
Does this mean that the TF-A region is mapped executable (and therefore prefetchable)
from early MMU setup time until this line has finished executing?
> +
> return 0;
> }
>
> diff --git a/drivers/mci/imx-esdhc-pbl.c b/drivers/mci/imx-esdhc-pbl.c
> index 2c74d101e4..2d071eaca8 100644
> --- a/drivers/mci/imx-esdhc-pbl.c
> +++ b/drivers/mci/imx-esdhc-pbl.c
> @@ -21,6 +21,7 @@
> #endif
> #ifdef CONFIG_ARCH_LAYERSCAPE
> #include <mach/layerscape/xload.h>
> +#include <mach/layerscape/layerscape.h>
> #endif
> #include "sdhci.h"
> #include "imx-esdhc.h"
> @@ -387,7 +388,7 @@ static int ls1028a_esdhc_start_image(void __iomem *base, struct dram_regions_inf
> .socdata = &data,
> };
> void *sdram = (void *)0x80000000;
> - void (*bl31)(void) = (void *)0xfbe00000;
> + void (*bl31)(void) = (void *)LS1028A_TFA_RESERVED_START;
> size_t bl31_size;
> void *bl31_image;
> struct bl2_to_bl31_params_mem_v2 *params;
> diff --git a/include/mach/layerscape/layerscape.h b/include/mach/layerscape/layerscape.h
> index a048b7ef9e..6f420dd4f4 100644
> --- a/include/mach/layerscape/layerscape.h
> +++ b/include/mach/layerscape/layerscape.h
> @@ -3,6 +3,8 @@
> #ifndef __MACH_LAYERSCAPE_H
> #define __MACH_LAYERSCAPE_H
>
> +#include <linux/sizes.h>
> +
> #define LS1046A_DDR_SDRAM_BASE 0x80000000
> #define LS1046A_DDR_FREQ 2100000000
>
> @@ -16,6 +18,12 @@
> #define LS1028A_SP_SHARED_DRAM_SIZE SZ_2M
> #define LS1028A_TZC400_BASE 0x01100000
>
> +#define LS1028A_TFA_SIZE SZ_64M
> +#define LS1028A_TFA_SHRD SZ_2M
> +#define LS1028A_TFA_RESERVED_SIZE (LS1028A_TFA_SIZE + LS1028A_TFA_SHRD)
> +#define LS1028A_TFA_RESERVED_START (0x100000000 - LS1028A_TFA_RESERVED_SIZE)
> +#define LS1028A_TFA_START (0x100000000 - LS1028A_TFA_SIZE)
> +
> enum bootsource ls1046a_bootsource_get(void);
> enum bootsource ls1021a_bootsource_get(void);
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH 02/10] ARM: Layerscape: LS1028a: reserve DDR region for TF-A
2024-01-09 9:37 ` Ahmad Fatoum
@ 2024-01-09 10:25 ` Sascha Hauer
0 siblings, 0 replies; 18+ messages in thread
From: Sascha Hauer @ 2024-01-09 10:25 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: Barebox List
On Tue, Jan 09, 2024 at 10:37:15AM +0100, Ahmad Fatoum wrote:
> On 09.01.24 10:15, Sascha Hauer wrote:
> > On LS1028a the TF-A is placed in DDR, so we have to reserve the region
> > in order to keep Linux away from it.
> >
> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > ---
> > arch/arm/mach-layerscape/soc.c | 2 ++
> > drivers/mci/imx-esdhc-pbl.c | 3 ++-
> > include/mach/layerscape/layerscape.h | 8 ++++++++
> > 3 files changed, 12 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/mach-layerscape/soc.c b/arch/arm/mach-layerscape/soc.c
> > index 4d4ef05d4b..5f9d0d5171 100644
> > --- a/arch/arm/mach-layerscape/soc.c
> > +++ b/arch/arm/mach-layerscape/soc.c
> > @@ -91,6 +91,8 @@ static int ls1028a_init(void)
> >
> > layerscape_register_pbl_image_handler();
> >
> > + reserve_sdram_region("tfa", LS1028A_TFA_RESERVED_START, LS1028A_TFA_RESERVED_SIZE);
>
> Does this mean that the TF-A region is mapped executable (and therefore prefetchable)
> from early MMU setup time until this line has finished executing?
No, it doesn't. The TFA is placed at the end of lowmem and
barebox_arm_entry() is called with the real memory size
minus the space occupied by the TFA.
Nevertheless this patch needs a fixup. reserve_sdram_region() is called
before the full DDR is registered, so there's nothing to reserve from at
this point. I'll have to create a mmu_initcall() from it.
Sascha
>
> > +
> > return 0;
> > }
> >
> > diff --git a/drivers/mci/imx-esdhc-pbl.c b/drivers/mci/imx-esdhc-pbl.c
> > index 2c74d101e4..2d071eaca8 100644
> > --- a/drivers/mci/imx-esdhc-pbl.c
> > +++ b/drivers/mci/imx-esdhc-pbl.c
> > @@ -21,6 +21,7 @@
> > #endif
> > #ifdef CONFIG_ARCH_LAYERSCAPE
> > #include <mach/layerscape/xload.h>
> > +#include <mach/layerscape/layerscape.h>
> > #endif
> > #include "sdhci.h"
> > #include "imx-esdhc.h"
> > @@ -387,7 +388,7 @@ static int ls1028a_esdhc_start_image(void __iomem *base, struct dram_regions_inf
> > .socdata = &data,
> > };
> > void *sdram = (void *)0x80000000;
> > - void (*bl31)(void) = (void *)0xfbe00000;
> > + void (*bl31)(void) = (void *)LS1028A_TFA_RESERVED_START;
> > size_t bl31_size;
> > void *bl31_image;
> > struct bl2_to_bl31_params_mem_v2 *params;
> > diff --git a/include/mach/layerscape/layerscape.h b/include/mach/layerscape/layerscape.h
> > index a048b7ef9e..6f420dd4f4 100644
> > --- a/include/mach/layerscape/layerscape.h
> > +++ b/include/mach/layerscape/layerscape.h
> > @@ -3,6 +3,8 @@
> > #ifndef __MACH_LAYERSCAPE_H
> > #define __MACH_LAYERSCAPE_H
> >
> > +#include <linux/sizes.h>
> > +
> > #define LS1046A_DDR_SDRAM_BASE 0x80000000
> > #define LS1046A_DDR_FREQ 2100000000
> >
> > @@ -16,6 +18,12 @@
> > #define LS1028A_SP_SHARED_DRAM_SIZE SZ_2M
> > #define LS1028A_TZC400_BASE 0x01100000
> >
> > +#define LS1028A_TFA_SIZE SZ_64M
> > +#define LS1028A_TFA_SHRD SZ_2M
> > +#define LS1028A_TFA_RESERVED_SIZE (LS1028A_TFA_SIZE + LS1028A_TFA_SHRD)
> > +#define LS1028A_TFA_RESERVED_START (0x100000000 - LS1028A_TFA_RESERVED_SIZE)
> > +#define LS1028A_TFA_START (0x100000000 - LS1028A_TFA_SIZE)
> > +
> > enum bootsource ls1046a_bootsource_get(void);
> > enum bootsource ls1021a_bootsource_get(void);
> >
>
> --
> Pengutronix e.K. | |
> Steuerwalder Str. 21 | http://www.pengutronix.de/ |
> 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
>
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 03/10] ARM: Layerscape: icid: make readonly arrays const
2024-01-09 9:15 [PATCH 00/10] Add more Layerscape LS1028a stuff Sascha Hauer
2024-01-09 9:15 ` [PATCH 01/10] ARM: Layerscape: consolidate initcalls into one Sascha Hauer
2024-01-09 9:15 ` [PATCH 02/10] ARM: Layerscape: LS1028a: reserve DDR region for TF-A Sascha Hauer
@ 2024-01-09 9:15 ` Sascha Hauer
2024-01-09 9:15 ` [PATCH 04/10] ARM: Layerscape: icid: rename functions Sascha Hauer
` (6 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: Sascha Hauer @ 2024-01-09 9:15 UTC (permalink / raw)
To: Barebox List
Several arrays used in icid.c are statically initialised and not
modified during runtime. Also they are only used locally, so make
them static const.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-layerscape/icid.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-layerscape/icid.c b/arch/arm/mach-layerscape/icid.c
index f5188fc91e..11fab9c3b9 100644
--- a/arch/arm/mach-layerscape/icid.c
+++ b/arch/arm/mach-layerscape/icid.c
@@ -81,7 +81,7 @@ struct fman_icid_id_table {
#define SEC_QIIC_LS 0x70024
#define SEC_IRBAR_JRn(n) (0x10000 * ((n) + 1))
-struct icid_id_table icid_tbl_ls1046a[] = {
+static const struct icid_id_table icid_tbl_ls1046a[] = {
{
.compat = "fsl,qman",
.id = DPAA1_SID_START,
@@ -209,7 +209,7 @@ struct icid_id_table icid_tbl_ls1046a[] = {
},
};
-struct fman_icid_id_table fman_icid_tbl_ls1046a[] = {
+static const struct fman_icid_id_table fman_icid_tbl_ls1046a[] = {
{
.port_id = 0x02,
.icid = DPAA1_SID_END,
@@ -279,7 +279,7 @@ struct fman_icid_id_table fman_icid_tbl_ls1046a[] = {
},
};
-static int get_fman_port_icid(int port_id, struct fman_icid_id_table *tbl,
+static int get_fman_port_icid(int port_id, const struct fman_icid_id_table *tbl,
const int size)
{
int i;
@@ -348,7 +348,7 @@ struct qportal_info {
u8 sdest;
};
-struct qportal_info qp_info[] = {
+static const struct qportal_info qp_info[] = {
{
.dicid = DPAA1_SID_END,
.ficid = DPAA1_SID_END,
@@ -440,7 +440,7 @@ static void setup_qbman_portals(void)
out_be32(&qman->qcsp_bar, (u32)QMAN_MEM_PHYS);
for (i = 0; i < ARRAY_SIZE(qp_info); i++) {
- struct qportal_info *qi = &qp_info[i];
+ const struct qportal_info *qi = &qp_info[i];
out_be32(&qman->qcsp[i].qcsp_lio_cfg, (qi->icid << 16) | qi->dicid);
/* set frame icid */
@@ -453,7 +453,7 @@ static void setup_qbman_portals(void)
}
static void fdt_set_qportal_iommu_prop(struct device_node *np, phandle iommu_handle,
- struct qportal_info *qp_info)
+ const struct qportal_info *qp_info)
{
u32 prop[6];
@@ -506,7 +506,7 @@ static int icid_of_fixup(struct device_node *root, void *context)
iommu_handle = of_node_create_phandle(iommu);
for (i = 0; i < ARRAY_SIZE(icid_tbl_ls1046a); i++) {
- struct icid_id_table *icid = &icid_tbl_ls1046a[i];
+ const struct icid_id_table *icid = &icid_tbl_ls1046a[i];
struct device_node *np;
if (!icid->compat)
@@ -538,14 +538,14 @@ void ls1046a_setup_icids(void)
/* setup general icid offsets */
for (i = 0; i < ARRAY_SIZE(icid_tbl_ls1046a); i++) {
- struct icid_id_table *icid = &icid_tbl_ls1046a[i];
+ const struct icid_id_table *icid = &icid_tbl_ls1046a[i];
out_be32((u32 *)(icid->reg_addr), icid->reg);
}
/* setup fman icids */
for (i = 0; i < ARRAY_SIZE(fman_icid_tbl_ls1046a); i++) {
- struct fman_icid_id_table *icid = &fman_icid_tbl_ls1046a[i];
+ const struct fman_icid_id_table *icid = &fman_icid_tbl_ls1046a[i];
out_be32(&fm->fm_bmi_common.fmbm_ppid[icid->port_id - 1],
icid->icid);
--
2.39.2
^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH 04/10] ARM: Layerscape: icid: rename functions
2024-01-09 9:15 [PATCH 00/10] Add more Layerscape LS1028a stuff Sascha Hauer
` (2 preceding siblings ...)
2024-01-09 9:15 ` [PATCH 03/10] ARM: Layerscape: icid: make readonly arrays const Sascha Hauer
@ 2024-01-09 9:15 ` Sascha Hauer
2024-01-09 9:15 ` [PATCH 05/10] ARM: Layerscape: icid: move re-usable code to separate functions Sascha Hauer
` (5 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: Sascha Hauer @ 2024-01-09 9:15 UTC (permalink / raw)
To: Barebox List
We are working on unflattened trees, so use the more appropriate
function prefix "of_" rather than "fdt_"
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-layerscape/icid.c | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/arch/arm/mach-layerscape/icid.c b/arch/arm/mach-layerscape/icid.c
index 11fab9c3b9..f0a9dc8063 100644
--- a/arch/arm/mach-layerscape/icid.c
+++ b/arch/arm/mach-layerscape/icid.c
@@ -292,7 +292,7 @@ static int get_fman_port_icid(int port_id, const struct fman_icid_id_table *tbl,
return -ENODEV;
}
-static void fdt_set_iommu_prop(struct device_node *np, phandle iommu_handle,
+static void of_set_iommu_prop(struct device_node *np, phandle iommu_handle,
int stream_id)
{
u32 prop[2];
@@ -303,7 +303,7 @@ static void fdt_set_iommu_prop(struct device_node *np, phandle iommu_handle,
of_set_property(np, "iommus", prop, sizeof(prop), 1);
}
-static void fdt_fixup_fman_port_icid_by_compat(struct device_node *root,
+static void of_fixup_fman_port_icid_by_compat(struct device_node *root,
phandle iommu_handle,
const char *compat)
{
@@ -324,11 +324,11 @@ static void fdt_fixup_fman_port_icid_by_compat(struct device_node *root,
continue;
}
- fdt_set_iommu_prop(np, iommu_handle, icid);
+ of_set_iommu_prop(np, iommu_handle, icid);
}
}
-static void fdt_fixup_fman_icids(struct device_node *root, phandle iommu_handle)
+static void of_fixup_fman_icids(struct device_node *root, phandle iommu_handle)
{
static const char * const compats[] = {
"fsl,fman-v3-port-oh",
@@ -338,7 +338,7 @@ static void fdt_fixup_fman_icids(struct device_node *root, phandle iommu_handle)
int i;
for (i = 0; i < ARRAY_SIZE(compats); i++)
- fdt_fixup_fman_port_icid_by_compat(root, iommu_handle, compats[i]);
+ of_fixup_fman_port_icid_by_compat(root, iommu_handle, compats[i]);
}
struct qportal_info {
@@ -452,7 +452,7 @@ static void setup_qbman_portals(void)
inhibit_portals(qpaddr, ARRAY_SIZE(qp_info), QMAN_SP_CINH_SIZE);
}
-static void fdt_set_qportal_iommu_prop(struct device_node *np, phandle iommu_handle,
+static void of_set_qportal_iommu_prop(struct device_node *np, phandle iommu_handle,
const struct qportal_info *qp_info)
{
u32 prop[6];
@@ -467,7 +467,7 @@ static void fdt_set_qportal_iommu_prop(struct device_node *np, phandle iommu_han
of_set_property(np, "iommus", prop, sizeof(prop), 1);
}
-static void fdt_fixup_qportals(struct device_node *root, phandle iommu_handle)
+static void of_fixup_qportals(struct device_node *root, phandle iommu_handle)
{
struct device_node *np;
unsigned int maj, min;
@@ -487,7 +487,7 @@ static void fdt_fixup_qportals(struct device_node *root, phandle iommu_handle)
if (ret)
continue;
- fdt_set_qportal_iommu_prop(np, iommu_handle, &qp_info[cell_index]);
+ of_set_qportal_iommu_prop(np, iommu_handle, &qp_info[cell_index]);
}
}
@@ -519,14 +519,14 @@ static int icid_of_fixup(struct device_node *root, void *context)
continue;
if (res.start == icid->compat_addr) {
- fdt_set_iommu_prop(np, iommu_handle, icid->id);
+ of_set_iommu_prop(np, iommu_handle, icid->id);
break;
}
}
}
- fdt_fixup_fman_icids(root, iommu_handle);
- fdt_fixup_qportals(root, iommu_handle);
+ of_fixup_fman_icids(root, iommu_handle);
+ of_fixup_qportals(root, iommu_handle);
return 0;
}
--
2.39.2
^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH 05/10] ARM: Layerscape: icid: move re-usable code to separate functions
2024-01-09 9:15 [PATCH 00/10] Add more Layerscape LS1028a stuff Sascha Hauer
` (3 preceding siblings ...)
2024-01-09 9:15 ` [PATCH 04/10] ARM: Layerscape: icid: rename functions Sascha Hauer
@ 2024-01-09 9:15 ` Sascha Hauer
2024-01-09 9:34 ` Ahmad Fatoum
2024-01-09 9:15 ` [PATCH 06/10] ARM: Layerscape: icids: factor out setup_icid_offsets() Sascha Hauer
` (4 subsequent siblings)
9 siblings, 1 reply; 18+ messages in thread
From: Sascha Hauer @ 2024-01-09 9:15 UTC (permalink / raw)
To: Barebox List
Create separate functions from code that can be re-used by upcoming
LS1028a support.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-layerscape/icid.c | 98 +++++++++++++++++++--------------
1 file changed, 57 insertions(+), 41 deletions(-)
diff --git a/arch/arm/mach-layerscape/icid.c b/arch/arm/mach-layerscape/icid.c
index f0a9dc8063..dd0e160bde 100644
--- a/arch/arm/mach-layerscape/icid.c
+++ b/arch/arm/mach-layerscape/icid.c
@@ -68,6 +68,58 @@ struct icid_id_table {
phys_addr_t reg_addr;
};
+static void of_set_iommu_prop(struct device_node *np, phandle iommu_handle,
+ int stream_id)
+{
+ u32 prop[2];
+
+ prop[0] = cpu_to_fdt32(iommu_handle);
+ prop[1] = cpu_to_fdt32(stream_id);
+
+ of_set_property(np, "iommus", prop, sizeof(prop), 1);
+}
+
+static phandle of_get_iommu_handle(struct device_node *root)
+{
+ struct device_node *iommu;
+
+ iommu = of_find_compatible_node(root, NULL, "arm,mmu-500");
+ if (!iommu) {
+ pr_info("No \"arm,mmu-500\" node found, won't fixup\n");
+ return 0;
+ }
+
+ return of_node_create_phandle(iommu);
+}
+
+static int of_fixup_icid(struct device_node *root, phandle iommu_handle,
+ const struct icid_id_table *icid_table, int num_icid)
+{
+ int i;
+
+ for (i = 0; i < num_icid; i++) {
+ const struct icid_id_table *icid = &icid_table[i];
+ struct device_node *np;
+
+ if (!icid->compat)
+ continue;
+
+ for_each_compatible_node_from(np, root, NULL, icid->compat) {
+ struct resource res;
+
+ if (of_address_to_resource(np, 0, &res))
+ continue;
+
+ if (res.start == icid->compat_addr) {
+ of_set_iommu_prop(np, iommu_handle, icid->id);
+ break;
+ }
+ }
+ }
+
+ return 0;
+}
+
struct fman_icid_id_table {
u32 port_id;
u32 icid;
@@ -292,17 +344,6 @@ static int get_fman_port_icid(int port_id, const struct fman_icid_id_table *tbl,
return -ENODEV;
}
-static void of_set_iommu_prop(struct device_node *np, phandle iommu_handle,
- int stream_id)
-{
- u32 prop[2];
-
- prop[0] = cpu_to_fdt32(iommu_handle);
- prop[1] = cpu_to_fdt32(stream_id);
-
- of_set_property(np, "iommus", prop, sizeof(prop), 1);
-}
-
static void of_fixup_fman_port_icid_by_compat(struct device_node *root,
phandle iommu_handle,
const char *compat)
@@ -491,40 +532,15 @@ static void of_fixup_qportals(struct device_node *root, phandle iommu_handle)
}
}
-static int icid_of_fixup(struct device_node *root, void *context)
+static int of_fixup_ls1046a(struct device_node *root, void *context)
{
- int i;
- struct device_node *iommu;
phandle iommu_handle;
- iommu = of_find_compatible_node(root, NULL, "arm,mmu-500");
- if (!iommu) {
- pr_info("No \"arm,mmu-500\" node found, won't fixup\n");
+ iommu_handle = of_get_iommu_handle(root);
+ if (!iommu_handle)
return 0;
- }
-
- iommu_handle = of_node_create_phandle(iommu);
-
- for (i = 0; i < ARRAY_SIZE(icid_tbl_ls1046a); i++) {
- const struct icid_id_table *icid = &icid_tbl_ls1046a[i];
- struct device_node *np;
-
- if (!icid->compat)
- continue;
-
- for_each_compatible_node_from(np, root, NULL, icid->compat) {
- struct resource res;
-
- if (of_address_to_resource(np, 0, &res))
- continue;
-
- if (res.start == icid->compat_addr) {
- of_set_iommu_prop(np, iommu_handle, icid->id);
- break;
- }
- }
- }
+ of_fixup_icid(root, iommu_handle, icid_tbl_ls1046a, ARRAY_SIZE(icid_tbl_ls1046a));
of_fixup_fman_icids(root, iommu_handle);
of_fixup_qportals(root, iommu_handle);
@@ -553,5 +569,5 @@ void ls1046a_setup_icids(void)
setup_qbman_portals();
- of_register_fixup(icid_of_fixup, NULL);
+ of_register_fixup(of_fixup_ls1046a, NULL);
}
--
2.39.2
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH 05/10] ARM: Layerscape: icid: move re-usable code to separate functions
2024-01-09 9:15 ` [PATCH 05/10] ARM: Layerscape: icid: move re-usable code to separate functions Sascha Hauer
@ 2024-01-09 9:34 ` Ahmad Fatoum
0 siblings, 0 replies; 18+ messages in thread
From: Ahmad Fatoum @ 2024-01-09 9:34 UTC (permalink / raw)
To: Sascha Hauer, Barebox List
On 09.01.24 10:15, Sascha Hauer wrote:
> Create separate functions from code that can be re-used by upcoming
> LS1028a support.
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> arch/arm/mach-layerscape/icid.c | 98 +++++++++++++++++++--------------
> 1 file changed, 57 insertions(+), 41 deletions(-)
>
> diff --git a/arch/arm/mach-layerscape/icid.c b/arch/arm/mach-layerscape/icid.c
> index f0a9dc8063..dd0e160bde 100644
> --- a/arch/arm/mach-layerscape/icid.c
> +++ b/arch/arm/mach-layerscape/icid.c
> @@ -68,6 +68,58 @@ struct icid_id_table {
> phys_addr_t reg_addr;
> };
>
> +static void of_set_iommu_prop(struct device_node *np, phandle iommu_handle,
> + int stream_id)
> +{
> + u32 prop[2];
> +
> + prop[0] = cpu_to_fdt32(iommu_handle);
> + prop[1] = cpu_to_fdt32(stream_id);
> +
> + of_set_property(np, "iommus", prop, sizeof(prop), 1);
I know the code is only moved around, but changing this to
of_property_write_u32_array() would make the intent clearer.
> +}
> +
> +static phandle of_get_iommu_handle(struct device_node *root)
> +{
> + struct device_node *iommu;
> +
> + iommu = of_find_compatible_node(root, NULL, "arm,mmu-500");
> + if (!iommu) {
> + pr_info("No \"arm,mmu-500\" node found, won't fixup\n");
> + return 0;
> + }
> +
> + return of_node_create_phandle(iommu);
> +}
> +
> +static int of_fixup_icid(struct device_node *root, phandle iommu_handle,
> + const struct icid_id_table *icid_table, int num_icid)
> +{
> + int i;
> +
> + for (i = 0; i < num_icid; i++) {
> + const struct icid_id_table *icid = &icid_table[i];
> + struct device_node *np;
> +
> + if (!icid->compat)
> + continue;
> +
> + for_each_compatible_node_from(np, root, NULL, icid->compat) {
> + struct resource res;
> +
> + if (of_address_to_resource(np, 0, &res))
> + continue;
> +
> + if (res.start == icid->compat_addr) {
> + of_set_iommu_prop(np, iommu_handle, icid->id);
> + break;
> + }
> + }
> + }
> +
> + return 0;
> +}
> +
> struct fman_icid_id_table {
> u32 port_id;
> u32 icid;
> @@ -292,17 +344,6 @@ static int get_fman_port_icid(int port_id, const struct fman_icid_id_table *tbl,
> return -ENODEV;
> }
>
> -static void of_set_iommu_prop(struct device_node *np, phandle iommu_handle,
> - int stream_id)
> -{
> - u32 prop[2];
> -
> - prop[0] = cpu_to_fdt32(iommu_handle);
> - prop[1] = cpu_to_fdt32(stream_id);
> -
> - of_set_property(np, "iommus", prop, sizeof(prop), 1);
> -}
> -
> static void of_fixup_fman_port_icid_by_compat(struct device_node *root,
> phandle iommu_handle,
> const char *compat)
> @@ -491,40 +532,15 @@ static void of_fixup_qportals(struct device_node *root, phandle iommu_handle)
> }
> }
>
> -static int icid_of_fixup(struct device_node *root, void *context)
> +static int of_fixup_ls1046a(struct device_node *root, void *context)
> {
> - int i;
> - struct device_node *iommu;
> phandle iommu_handle;
>
> - iommu = of_find_compatible_node(root, NULL, "arm,mmu-500");
> - if (!iommu) {
> - pr_info("No \"arm,mmu-500\" node found, won't fixup\n");
> + iommu_handle = of_get_iommu_handle(root);
> + if (!iommu_handle)
> return 0;
> - }
> -
> - iommu_handle = of_node_create_phandle(iommu);
> -
> - for (i = 0; i < ARRAY_SIZE(icid_tbl_ls1046a); i++) {
> - const struct icid_id_table *icid = &icid_tbl_ls1046a[i];
> - struct device_node *np;
> -
> - if (!icid->compat)
> - continue;
> -
> - for_each_compatible_node_from(np, root, NULL, icid->compat) {
> - struct resource res;
> -
> - if (of_address_to_resource(np, 0, &res))
> - continue;
> -
> - if (res.start == icid->compat_addr) {
> - of_set_iommu_prop(np, iommu_handle, icid->id);
> - break;
> - }
> - }
> - }
>
> + of_fixup_icid(root, iommu_handle, icid_tbl_ls1046a, ARRAY_SIZE(icid_tbl_ls1046a));
> of_fixup_fman_icids(root, iommu_handle);
> of_fixup_qportals(root, iommu_handle);
>
> @@ -553,5 +569,5 @@ void ls1046a_setup_icids(void)
>
> setup_qbman_portals();
>
> - of_register_fixup(icid_of_fixup, NULL);
> + of_register_fixup(of_fixup_ls1046a, NULL);
> }
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 06/10] ARM: Layerscape: icids: factor out setup_icid_offsets()
2024-01-09 9:15 [PATCH 00/10] Add more Layerscape LS1028a stuff Sascha Hauer
` (4 preceding siblings ...)
2024-01-09 9:15 ` [PATCH 05/10] ARM: Layerscape: icid: move re-usable code to separate functions Sascha Hauer
@ 2024-01-09 9:15 ` Sascha Hauer
2024-01-09 9:16 ` [PATCH 07/10] immap_lsch3: Add more stuff Sascha Hauer
` (3 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: Sascha Hauer @ 2024-01-09 9:15 UTC (permalink / raw)
To: Barebox List
The code to iterate over the icid table writing register values can be
re-used for upcomin LS1028a support, so move the code to a separate
function.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-layerscape/icid.c | 23 ++++++++++++++++-------
1 file changed, 16 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-layerscape/icid.c b/arch/arm/mach-layerscape/icid.c
index dd0e160bde..f916ec7baf 100644
--- a/arch/arm/mach-layerscape/icid.c
+++ b/arch/arm/mach-layerscape/icid.c
@@ -120,6 +120,20 @@ static int of_fixup_icid(struct device_node *root, phandle iommu_handle,
return 0;
}
+static void setup_icid_offsets(const struct icid_id_table *icid_table, int num_icids, bool le)
+{
+ int i;
+
+ for (i = 0; i < num_icids; i++) {
+ const struct icid_id_table *icid = &icid_table[i];
+
+ if (le)
+ out_le32((u32 *)(icid->reg_addr), icid->reg);
+ else
+ out_be32((u32 *)(icid->reg_addr), icid->reg);
+ }
+}
+
struct fman_icid_id_table {
u32 port_id;
u32 icid;
@@ -549,15 +563,10 @@ static int of_fixup_ls1046a(struct device_node *root, void *context)
void ls1046a_setup_icids(void)
{
- int i;
struct ccsr_fman *fm = (void *)LSCH2_FM1_ADDR;
+ int i;
- /* setup general icid offsets */
- for (i = 0; i < ARRAY_SIZE(icid_tbl_ls1046a); i++) {
- const struct icid_id_table *icid = &icid_tbl_ls1046a[i];
-
- out_be32((u32 *)(icid->reg_addr), icid->reg);
- }
+ setup_icid_offsets(icid_tbl_ls1046a, ARRAY_SIZE(icid_tbl_ls1046a), false);
/* setup fman icids */
for (i = 0; i < ARRAY_SIZE(fman_icid_tbl_ls1046a); i++) {
--
2.39.2
^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH 07/10] immap_lsch3: Add more stuff
2024-01-09 9:15 [PATCH 00/10] Add more Layerscape LS1028a stuff Sascha Hauer
` (5 preceding siblings ...)
2024-01-09 9:15 ` [PATCH 06/10] ARM: Layerscape: icids: factor out setup_icid_offsets() Sascha Hauer
@ 2024-01-09 9:16 ` Sascha Hauer
2024-01-09 9:16 ` [PATCH 08/10] ARM: Layerscape: LS1028a: fixup icids Sascha Hauer
` (2 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: Sascha Hauer @ 2024-01-09 9:16 UTC (permalink / raw)
To: Barebox List
arch/arm/mach-layerscape/icid.c pokes on several peripheral base
addresses. Let's add some more stuff from the corresponding U-Boot
file for upcoming LS1028a support.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
include/soc/fsl/immap_lsch3.h | 119 ++++++++++++++++++++++++++++++++++
1 file changed, 119 insertions(+)
diff --git a/include/soc/fsl/immap_lsch3.h b/include/soc/fsl/immap_lsch3.h
index f2fdb7dfb3..f25a6e46be 100644
--- a/include/soc/fsl/immap_lsch3.h
+++ b/include/soc/fsl/immap_lsch3.h
@@ -29,8 +29,23 @@
#define LSCH3_IFC_ADDR (LSCH3_IMMR + 0x01240000)
#define LSCH3_NS16550_COM1 (LSCH3_IMMR + 0x011C0500)
#define LSCH3_NS16550_COM2 (LSCH3_IMMR + 0x011C0600)
+#define LSCH3_EDMA_ADDR (LSCH3_IMMR + 0x012c0000)
#define LSCH3_TIMER_ADDR (LSCH3_IMMR + 0x013e0000)
+#define LSCH3_XHCI_USB1_ADDR (LSCH3_IMMR + 0x02100000)
+#define LSCH3_XHCI_USB2_ADDR (LSCH3_IMMR + 0x02110000)
+#define LSCH3_AHCI1_ADDR (LSCH3_IMMR + 0x02200000)
+#define LSCH3_AHCI2_ADDR (LSCH3_IMMR + 0x02210000)
+#define LSCH3_AHCI3_ADDR (LSCH3_IMMR + 0x02220000)
+#define LSCH3_AHCI4_ADDR (LSCH3_IMMR + 0x02230000)
#define LSCH3_CCI400_ADDR (LSCH3_IMMR + 0x03090000)
+#define LSCH3_SEC_ADDR (LSCH3_IMMR + 0x07000000)
+#define LSCH3_SEC_JR0_ADDR (LSCH3_IMMR + 0x07010000)
+#define LSCH3_SEC_JR1_ADDR (LSCH3_IMMR + 0x07020000)
+#define LSCH3_SEC_JR2_ADDR (LSCH3_IMMR + 0x07030000)
+#define LSCH3_SEC_JR3_ADDR (LSCH3_IMMR + 0x07040000)
+#define LSCH3_QDMA_ADDR (LSCH3_IMMR + 0x07380000)
+#define LSCH3_DISPLAY_ADDR (LSCH3_IMMR + 0x0e080000)
+#define LSCH3_GPU_ADDR (LSCH3_IMMR + 0x0e0c0000)
#define LSCH3_PMU_CLTBENR (LSCH3_PMU_ADDR + 0x18A0)
#define LSCH3_PCTBENR_OFFSET (LSCH3_PMU_ADDR + 0x8A0)
#define LSCH3_SVR (LSCH3_GUTS_ADDR + 0xA4)
@@ -183,5 +198,109 @@ struct lsch3_ccsr_gur {
u8 res_858[0x1000-0xc00];
};
+struct rng4tst {
+ u32 rtmctl; /* misc. control register */
+ u32 rtscmisc; /* statistical check misc. register */
+ u32 rtpkrrng; /* poker range register */
+ union {
+ u32 rtpkrmax; /* PRGM=1: poker max. limit register */
+ u32 rtpkrsq; /* PRGM=0: poker square calc. result register */
+ };
+ u32 rtsdctl; /* seed control register */
+ union {
+ u32 rtsblim; /* PRGM=1: sparse bit limit register */
+ u32 rttotsam; /* PRGM=0: total samples register */
+ };
+ u32 rtfreqmin; /* frequency count min. limit register */
+ union {
+ u32 rtfreqmax; /* PRGM=1: freq. count max. limit register */
+ u32 rtfreqcnt; /* PRGM=0: freq. count register */
+ };
+ u32 rsvd1[40];
+ u32 rdsta; /*RNG DRNG Status Register*/
+ u32 rsvd2[15];
+};
+
+struct version_regs {
+ u32 crca; /* CRCA_VERSION */
+ u32 afha; /* AFHA_VERSION */
+ u32 kfha; /* KFHA_VERSION */
+ u32 pkha; /* PKHA_VERSION */
+ u32 aesa; /* AESA_VERSION */
+ u32 mdha; /* MDHA_VERSION */
+ u32 desa; /* DESA_VERSION */
+ u32 snw8a; /* SNW8A_VERSION */
+ u32 snw9a; /* SNW9A_VERSION */
+ u32 zuce; /* ZUCE_VERSION */
+ u32 zuca; /* ZUCA_VERSION */
+ u32 ccha; /* CCHA_VERSION */
+ u32 ptha; /* PTHA_VERSION */
+ u32 rng; /* RNG_VERSION */
+ u32 trng; /* TRNG_VERSION */
+ u32 aaha; /* AAHA_VERSION */
+ u32 rsvd[10];
+ u32 sr; /* SR_VERSION */
+ u32 dma; /* DMA_VERSION */
+ u32 ai; /* AI_VERSION */
+ u32 qi; /* QI_VERSION */
+ u32 jr; /* JR_VERSION */
+ u32 deco; /* DECO_VERSION */
+};
+
+struct ccsr_sec {
+ u32 res0;
+ u32 mcfgr; /* Master CFG Register */
+ u8 res1[0x4];
+ u32 scfgr;
+ struct {
+ u32 ms; /* Job Ring LIODN Register, MS */
+ u32 ls; /* Job Ring LIODN Register, LS */
+ } jrliodnr[4];
+ u8 res2[0x2c];
+ u32 jrstartr; /* Job Ring Start Register */
+ struct {
+ u32 ms; /* RTIC LIODN Register, MS */
+ u32 ls; /* RTIC LIODN Register, LS */
+ } rticliodnr[4];
+ u8 res3[0x1c];
+ u32 decorr; /* DECO Request Register */
+ struct {
+ u32 ms; /* DECO LIODN Register, MS */
+ u32 ls; /* DECO LIODN Register, LS */
+ } decoliodnr[16];
+ u32 dar; /* DECO Avail Register */
+ u32 drr; /* DECO Reset Register */
+ u8 res5[0x4d8];
+ struct rng4tst rng; /* RNG Registers */
+ u8 res6[0x780];
+ struct version_regs vreg; /* version registers since era 10 */
+ u8 res7[0xa0];
+ u32 crnr_ms; /* CHA Revision Number Register, MS */
+ u32 crnr_ls; /* CHA Revision Number Register, LS */
+ u32 ctpr_ms; /* Compile Time Parameters Register, MS */
+ u32 ctpr_ls; /* Compile Time Parameters Register, LS */
+ u8 res8[0x10];
+ u32 far_ms; /* Fault Address Register, MS */
+ u32 far_ls; /* Fault Address Register, LS */
+ u32 falr; /* Fault Address LIODN Register */
+ u32 fadr; /* Fault Address Detail Register */
+ u8 res9[0x4];
+ u32 csta; /* CAAM Status Register */
+ u32 smpart; /* Secure Memory Partition Parameters */
+ u32 smvid; /* Secure Memory Version ID */
+ u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/
+ u32 ccbvid; /* CHA Cluster Block Version ID Register */
+ u32 chavid_ms; /* CHA Version ID Register, MS */
+ u32 chavid_ls; /* CHA Version ID Register, LS */
+ u32 chanum_ms; /* CHA Number Register, MS */
+ u32 chanum_ls; /* CHA Number Register, LS */
+ u32 secvid_ms; /* SEC Version ID Register, MS */
+ u32 secvid_ls; /* SEC Version ID Register, LS */
+ u8 res10[0x6f020];
+ u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */
+ u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */
+ u8 res11[0x8ffd8];
+};
+
#endif /*__ASSEMBLY__ */
#endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */
--
2.39.2
^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH 08/10] ARM: Layerscape: LS1028a: fixup icids
2024-01-09 9:15 [PATCH 00/10] Add more Layerscape LS1028a stuff Sascha Hauer
` (6 preceding siblings ...)
2024-01-09 9:16 ` [PATCH 07/10] immap_lsch3: Add more stuff Sascha Hauer
@ 2024-01-09 9:16 ` Sascha Hauer
2024-01-09 9:28 ` Ahmad Fatoum
2024-01-09 9:16 ` [PATCH 09/10] ARM: psci: make header self contained Sascha Hauer
2024-01-09 9:16 ` [PATCH 10/10] ARM: Layerscape: LS1028a: fixup psci node Sascha Hauer
9 siblings, 1 reply; 18+ messages in thread
From: Sascha Hauer @ 2024-01-09 9:16 UTC (permalink / raw)
To: Barebox List
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-layerscape/icid.c | 213 +++++++++++++++++++++++++++
arch/arm/mach-layerscape/soc.c | 1 +
include/mach/layerscape/layerscape.h | 1 +
3 files changed, 215 insertions(+)
diff --git a/arch/arm/mach-layerscape/icid.c b/arch/arm/mach-layerscape/icid.c
index f916ec7baf..93fec286c6 100644
--- a/arch/arm/mach-layerscape/icid.c
+++ b/arch/arm/mach-layerscape/icid.c
@@ -5,6 +5,7 @@
#include <init.h>
#include <of_address.h>
#include <soc/fsl/immap_lsch2.h>
+#include <soc/fsl/immap_lsch3.h>
#include <soc/fsl/fsl_qbman.h>
#include <soc/fsl/fsl_fman.h>
#include <mach/layerscape/layerscape.h>
@@ -580,3 +581,215 @@ void ls1046a_setup_icids(void)
of_register_fixup(of_fixup_ls1046a, NULL);
}
+
+static const struct icid_id_table icid_tbl_ls1028a[] = {
+ {
+ .compat = "snps,dwc3",
+ .id = 1,
+ .reg = 1,
+ .compat_addr = LSCH3_XHCI_USB1_ADDR,
+ .reg_addr = offsetof(struct lsch3_ccsr_gur, usb1_amqr) + LSCH3_GUTS_ADDR,
+ }, {
+ .compat = "snps,dwc3",
+ .id = 2,
+ .reg = 2,
+ .compat_addr = LSCH3_XHCI_USB2_ADDR,
+ .reg_addr = offsetof(struct lsch3_ccsr_gur, usb2_amqr) + LSCH3_GUTS_ADDR,
+ }, {
+ .compat = "fsl,esdhc",
+ .id = 3,
+ .reg = 3,
+ .compat_addr = LSCH3_ESDHC1_BASE_ADDR,
+ .reg_addr = offsetof(struct lsch3_ccsr_gur, sdmm1_amqr) + LSCH3_GUTS_ADDR,
+ }, {
+ .compat = "fsl,esdhc",
+ .id = 3,
+ .reg = 3,
+ .compat_addr = LSCH3_ESDHC2_BASE_ADDR,
+ .reg_addr = offsetof(struct lsch3_ccsr_gur, sdmm2_amqr) + LSCH3_GUTS_ADDR,
+ }, {
+ .compat = "fsl,ls1028a-ahci",
+ .id = 4,
+ .reg = 4,
+ .compat_addr = LSCH3_AHCI1_ADDR,
+ .reg_addr = offsetof(struct lsch3_ccsr_gur, sata1_amqr) + LSCH3_GUTS_ADDR,
+ }, {
+ .compat = "fsl,vf610-edma",
+ .id = 40,
+ .reg = 40,
+ .compat_addr = LSCH3_EDMA_ADDR,
+ .reg_addr = offsetof(struct lsch3_ccsr_gur, spare3_amqr) + LSCH3_GUTS_ADDR,
+ }, {
+ .compat = "fsl,ls1028a-qdma",
+ .id = 5,
+ .reg = (1 << 31) | 5,
+ .compat_addr = LSCH3_QDMA_ADDR,
+ .reg_addr = LSCH3_QDMA_ADDR + QMAN_CQSIDR_REG,
+ }, {
+ .compat = NULL,
+ .id = 5,
+ .reg = (1 << 31) | 5,
+ .compat_addr = LSCH3_QDMA_ADDR,
+ .reg_addr = LSCH3_QDMA_ADDR + QMAN_CQSIDR_REG + 4,
+ }, {
+ .compat = "vivante,gc",
+ .id = 71,
+ .reg = 71,
+ .compat_addr = LSCH3_GPU_ADDR,
+ .reg_addr = offsetof(struct lsch3_ccsr_gur, misc1_amqr) + LSCH3_GUTS_ADDR,
+ }, {
+ .compat = "arm,mali-dp500",
+ .id = 72,
+ .reg = 72,
+ .compat_addr = LSCH3_DISPLAY_ADDR,
+ .reg_addr = offsetof(struct lsch3_ccsr_gur, spare2_amqr) + LSCH3_GUTS_ADDR,
+ }, {
+ .compat = "fsl,sec-v4.0-job-ring",
+ .id = 65,
+ .reg = 65,
+ .compat_addr = LSCH3_SEC_JR0_ADDR,
+ .reg_addr = offsetof(struct ccsr_sec, jrliodnr[0].ls) + LSCH3_SEC_ADDR,
+ }, {
+ .compat = "fsl,sec-v4.0-job-ring",
+ .id = 66,
+ .reg = 66,
+ .compat_addr = LSCH3_SEC_JR1_ADDR,
+ .reg_addr = offsetof(struct ccsr_sec, jrliodnr[1].ls) + LSCH3_SEC_ADDR,
+ }, {
+ .id = 67,
+ .reg = 67,
+ .compat_addr = LSCH3_SEC_JR2_ADDR,
+ .reg_addr = offsetof(struct ccsr_sec, jrliodnr[2].ls) + LSCH3_SEC_ADDR,
+ }, {
+ .compat = "fsl,sec-v4.0-job-ring",
+ .id = 68,
+ .reg = 68,
+ .compat_addr = LSCH3_SEC_JR3_ADDR,
+ .reg_addr = offsetof(struct ccsr_sec, jrliodnr[3].ls) + LSCH3_SEC_ADDR,
+ }, {
+ .id = 64,
+ .reg = 64,
+ .compat_addr = 0,
+ .reg_addr = offsetof(struct ccsr_sec, rticliodnr[0].ls) + LSCH3_SEC_ADDR,
+ }, {
+ .id = 64,
+ .reg = 64,
+ .compat_addr = 0,
+ .reg_addr = offsetof(struct ccsr_sec, rticliodnr[1].ls) + LSCH3_SEC_ADDR,
+ }, {
+ .id = 64,
+ .reg = 64,
+ .compat_addr = 0,
+ .reg_addr = offsetof(struct ccsr_sec, rticliodnr[2].ls) + LSCH3_SEC_ADDR,
+ }, {
+ .id = 64,
+ .reg = 64,
+ .compat_addr = 0,
+ .reg_addr = offsetof(struct ccsr_sec, rticliodnr[3].ls) + LSCH3_SEC_ADDR,
+ }, {
+ .id = 64,
+ .reg = 64,
+ .compat_addr = 0,
+ .reg_addr = offsetof(struct ccsr_sec, decoliodnr[0].ls) + LSCH3_SEC_ADDR,
+ }, {
+ .id = 64,
+ .reg = 64,
+ .compat_addr = 0,
+ .reg_addr = offsetof(struct ccsr_sec, decoliodnr[1].ls) + LSCH3_SEC_ADDR,
+ }
+};
+
+static int of_fixup_icid_ls1028a(struct device_node *root, void *context)
+{
+ phandle iommu_handle;
+
+ iommu_handle = of_get_iommu_handle(root);
+ if (!iommu_handle)
+ return 0;
+
+ of_fixup_icid(root, iommu_handle, icid_tbl_ls1028a, ARRAY_SIZE(icid_tbl_ls1028a));
+
+ return 0;
+}
+
+/* offset of IERB config register per PCI function */
+static const int ierb_offset[] = {
+ 0x0800,
+ 0x1800,
+ 0x2800,
+ 0x3800,
+ 0x4800,
+ 0x5800,
+ 0x6800,
+ -1,
+ 0x0804,
+ 0x0808,
+ 0x1804,
+ 0x1808,
+};
+
+#define ECAM_IERB_BASE 0x1f0800000ULL
+#define ECAM_IERB_MSICAR (ECAM_IERB_BASE + 0xa400)
+#define ECAM_IERB_MSICAR_VALUE 0x30
+#define FSL_ECAM_STREAM_ID_START 41
+
+/*
+ * Use a custom function for LS1028A, for now this is the only SoC with IERB
+ * and we're currently considering reorganizing IERB for future SoCs.
+ */
+static void ls1028a_set_ecam_icids(void)
+{
+ int i;
+
+ out_le32(ECAM_IERB_MSICAR, ECAM_IERB_MSICAR_VALUE);
+
+ for (i = 0; i < ARRAY_SIZE(ierb_offset); i++) {
+ if (ierb_offset[i] < 0)
+ continue;
+
+ out_le32(ECAM_IERB_BASE + ierb_offset[i],
+ FSL_ECAM_STREAM_ID_START + i);
+ }
+}
+
+static int of_fixup_ecam_ls1028a(struct device_node *root, void *context)
+{
+ struct device_node *np;
+ int i, ret;
+ const char *props[] = { "msi-map", "iommu-map" };
+ uint32_t map[4];
+
+ np = of_find_compatible_node(root, NULL, "pci-host-ecam-generic");
+ if (!np) {
+ pr_info("No \"pci-host-ecam-generic\" node found, won't fixup\n");
+ return 0;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(props); i++) {
+ ret = of_property_read_u32_array(np, props[i], map, 4);
+ if (ret) {
+ pr_err("Cannot read \"%s\" property: %pe", props[i], ERR_PTR(ret));
+ return ret;
+ }
+
+ map[2] = FSL_ECAM_STREAM_ID_START;
+ map[3] = ARRAY_SIZE(ierb_offset);
+ ret = of_property_write_u32_array(np, props[i], map, 4);
+ if (ret) {
+ pr_err("Cannot write \"%s\" property: %pe", props[i], ERR_PTR(ret));
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+void ls1028a_setup_icids(void)
+{
+ setup_icid_offsets(icid_tbl_ls1028a, ARRAY_SIZE(icid_tbl_ls1028a), true);
+
+ ls1028a_set_ecam_icids();
+
+ of_register_fixup(of_fixup_icid_ls1028a, NULL);
+ of_register_fixup(of_fixup_ecam_ls1028a, NULL);
+}
diff --git a/arch/arm/mach-layerscape/soc.c b/arch/arm/mach-layerscape/soc.c
index 5f9d0d5171..70c1dedb46 100644
--- a/arch/arm/mach-layerscape/soc.c
+++ b/arch/arm/mach-layerscape/soc.c
@@ -90,6 +90,7 @@ static int ls1028a_init(void)
return -EINVAL;
layerscape_register_pbl_image_handler();
+ ls1028a_setup_icids();
reserve_sdram_region("tfa", LS1028A_TFA_RESERVED_START, LS1028A_TFA_RESERVED_SIZE);
diff --git a/include/mach/layerscape/layerscape.h b/include/mach/layerscape/layerscape.h
index 6f420dd4f4..2905360c29 100644
--- a/include/mach/layerscape/layerscape.h
+++ b/include/mach/layerscape/layerscape.h
@@ -58,6 +58,7 @@ void ls1046a_bootsource_init(void);
void layerscape_register_pbl_image_handler(void);
void ls102xa_smmu_stream_id_init(void);
void ls1021a_restart_register_feature(void);
+void ls1028a_setup_icids(void);
void ls1046a_setup_icids(void);
#endif /* __MACH_LAYERSCAPE_H */
--
2.39.2
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH 08/10] ARM: Layerscape: LS1028a: fixup icids
2024-01-09 9:16 ` [PATCH 08/10] ARM: Layerscape: LS1028a: fixup icids Sascha Hauer
@ 2024-01-09 9:28 ` Ahmad Fatoum
0 siblings, 0 replies; 18+ messages in thread
From: Ahmad Fatoum @ 2024-01-09 9:28 UTC (permalink / raw)
To: Sascha Hauer, Barebox List
On 09.01.24 10:16, Sascha Hauer wrote:
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
A short message on what ICIDs are would be nice.
Cheers,
Ahmad
> ---
> arch/arm/mach-layerscape/icid.c | 213 +++++++++++++++++++++++++++
> arch/arm/mach-layerscape/soc.c | 1 +
> include/mach/layerscape/layerscape.h | 1 +
> 3 files changed, 215 insertions(+)
>
> diff --git a/arch/arm/mach-layerscape/icid.c b/arch/arm/mach-layerscape/icid.c
> index f916ec7baf..93fec286c6 100644
> --- a/arch/arm/mach-layerscape/icid.c
> +++ b/arch/arm/mach-layerscape/icid.c
> @@ -5,6 +5,7 @@
> #include <init.h>
> #include <of_address.h>
> #include <soc/fsl/immap_lsch2.h>
> +#include <soc/fsl/immap_lsch3.h>
> #include <soc/fsl/fsl_qbman.h>
> #include <soc/fsl/fsl_fman.h>
> #include <mach/layerscape/layerscape.h>
> @@ -580,3 +581,215 @@ void ls1046a_setup_icids(void)
>
> of_register_fixup(of_fixup_ls1046a, NULL);
> }
> +
> +static const struct icid_id_table icid_tbl_ls1028a[] = {
> + {
> + .compat = "snps,dwc3",
> + .id = 1,
> + .reg = 1,
> + .compat_addr = LSCH3_XHCI_USB1_ADDR,
> + .reg_addr = offsetof(struct lsch3_ccsr_gur, usb1_amqr) + LSCH3_GUTS_ADDR,
> + }, {
> + .compat = "snps,dwc3",
> + .id = 2,
> + .reg = 2,
> + .compat_addr = LSCH3_XHCI_USB2_ADDR,
> + .reg_addr = offsetof(struct lsch3_ccsr_gur, usb2_amqr) + LSCH3_GUTS_ADDR,
> + }, {
> + .compat = "fsl,esdhc",
> + .id = 3,
> + .reg = 3,
> + .compat_addr = LSCH3_ESDHC1_BASE_ADDR,
> + .reg_addr = offsetof(struct lsch3_ccsr_gur, sdmm1_amqr) + LSCH3_GUTS_ADDR,
> + }, {
> + .compat = "fsl,esdhc",
> + .id = 3,
> + .reg = 3,
> + .compat_addr = LSCH3_ESDHC2_BASE_ADDR,
> + .reg_addr = offsetof(struct lsch3_ccsr_gur, sdmm2_amqr) + LSCH3_GUTS_ADDR,
> + }, {
> + .compat = "fsl,ls1028a-ahci",
> + .id = 4,
> + .reg = 4,
> + .compat_addr = LSCH3_AHCI1_ADDR,
> + .reg_addr = offsetof(struct lsch3_ccsr_gur, sata1_amqr) + LSCH3_GUTS_ADDR,
> + }, {
> + .compat = "fsl,vf610-edma",
> + .id = 40,
> + .reg = 40,
> + .compat_addr = LSCH3_EDMA_ADDR,
> + .reg_addr = offsetof(struct lsch3_ccsr_gur, spare3_amqr) + LSCH3_GUTS_ADDR,
> + }, {
> + .compat = "fsl,ls1028a-qdma",
> + .id = 5,
> + .reg = (1 << 31) | 5,
> + .compat_addr = LSCH3_QDMA_ADDR,
> + .reg_addr = LSCH3_QDMA_ADDR + QMAN_CQSIDR_REG,
> + }, {
> + .compat = NULL,
> + .id = 5,
> + .reg = (1 << 31) | 5,
> + .compat_addr = LSCH3_QDMA_ADDR,
> + .reg_addr = LSCH3_QDMA_ADDR + QMAN_CQSIDR_REG + 4,
> + }, {
> + .compat = "vivante,gc",
> + .id = 71,
> + .reg = 71,
> + .compat_addr = LSCH3_GPU_ADDR,
> + .reg_addr = offsetof(struct lsch3_ccsr_gur, misc1_amqr) + LSCH3_GUTS_ADDR,
> + }, {
> + .compat = "arm,mali-dp500",
> + .id = 72,
> + .reg = 72,
> + .compat_addr = LSCH3_DISPLAY_ADDR,
> + .reg_addr = offsetof(struct lsch3_ccsr_gur, spare2_amqr) + LSCH3_GUTS_ADDR,
> + }, {
> + .compat = "fsl,sec-v4.0-job-ring",
> + .id = 65,
> + .reg = 65,
> + .compat_addr = LSCH3_SEC_JR0_ADDR,
> + .reg_addr = offsetof(struct ccsr_sec, jrliodnr[0].ls) + LSCH3_SEC_ADDR,
> + }, {
> + .compat = "fsl,sec-v4.0-job-ring",
> + .id = 66,
> + .reg = 66,
> + .compat_addr = LSCH3_SEC_JR1_ADDR,
> + .reg_addr = offsetof(struct ccsr_sec, jrliodnr[1].ls) + LSCH3_SEC_ADDR,
> + }, {
> + .id = 67,
> + .reg = 67,
> + .compat_addr = LSCH3_SEC_JR2_ADDR,
> + .reg_addr = offsetof(struct ccsr_sec, jrliodnr[2].ls) + LSCH3_SEC_ADDR,
> + }, {
> + .compat = "fsl,sec-v4.0-job-ring",
> + .id = 68,
> + .reg = 68,
> + .compat_addr = LSCH3_SEC_JR3_ADDR,
> + .reg_addr = offsetof(struct ccsr_sec, jrliodnr[3].ls) + LSCH3_SEC_ADDR,
> + }, {
> + .id = 64,
> + .reg = 64,
> + .compat_addr = 0,
> + .reg_addr = offsetof(struct ccsr_sec, rticliodnr[0].ls) + LSCH3_SEC_ADDR,
> + }, {
> + .id = 64,
> + .reg = 64,
> + .compat_addr = 0,
> + .reg_addr = offsetof(struct ccsr_sec, rticliodnr[1].ls) + LSCH3_SEC_ADDR,
> + }, {
> + .id = 64,
> + .reg = 64,
> + .compat_addr = 0,
> + .reg_addr = offsetof(struct ccsr_sec, rticliodnr[2].ls) + LSCH3_SEC_ADDR,
> + }, {
> + .id = 64,
> + .reg = 64,
> + .compat_addr = 0,
> + .reg_addr = offsetof(struct ccsr_sec, rticliodnr[3].ls) + LSCH3_SEC_ADDR,
> + }, {
> + .id = 64,
> + .reg = 64,
> + .compat_addr = 0,
> + .reg_addr = offsetof(struct ccsr_sec, decoliodnr[0].ls) + LSCH3_SEC_ADDR,
> + }, {
> + .id = 64,
> + .reg = 64,
> + .compat_addr = 0,
> + .reg_addr = offsetof(struct ccsr_sec, decoliodnr[1].ls) + LSCH3_SEC_ADDR,
> + }
> +};
> +
> +static int of_fixup_icid_ls1028a(struct device_node *root, void *context)
> +{
> + phandle iommu_handle;
> +
> + iommu_handle = of_get_iommu_handle(root);
> + if (!iommu_handle)
> + return 0;
> +
> + of_fixup_icid(root, iommu_handle, icid_tbl_ls1028a, ARRAY_SIZE(icid_tbl_ls1028a));
> +
> + return 0;
> +}
> +
> +/* offset of IERB config register per PCI function */
> +static const int ierb_offset[] = {
> + 0x0800,
> + 0x1800,
> + 0x2800,
> + 0x3800,
> + 0x4800,
> + 0x5800,
> + 0x6800,
> + -1,
> + 0x0804,
> + 0x0808,
> + 0x1804,
> + 0x1808,
> +};
> +
> +#define ECAM_IERB_BASE 0x1f0800000ULL
> +#define ECAM_IERB_MSICAR (ECAM_IERB_BASE + 0xa400)
> +#define ECAM_IERB_MSICAR_VALUE 0x30
> +#define FSL_ECAM_STREAM_ID_START 41
> +
> +/*
> + * Use a custom function for LS1028A, for now this is the only SoC with IERB
> + * and we're currently considering reorganizing IERB for future SoCs.
> + */
> +static void ls1028a_set_ecam_icids(void)
> +{
> + int i;
> +
> + out_le32(ECAM_IERB_MSICAR, ECAM_IERB_MSICAR_VALUE);
> +
> + for (i = 0; i < ARRAY_SIZE(ierb_offset); i++) {
> + if (ierb_offset[i] < 0)
> + continue;
> +
> + out_le32(ECAM_IERB_BASE + ierb_offset[i],
> + FSL_ECAM_STREAM_ID_START + i);
> + }
> +}
> +
> +static int of_fixup_ecam_ls1028a(struct device_node *root, void *context)
> +{
> + struct device_node *np;
> + int i, ret;
> + const char *props[] = { "msi-map", "iommu-map" };
> + uint32_t map[4];
> +
> + np = of_find_compatible_node(root, NULL, "pci-host-ecam-generic");
> + if (!np) {
> + pr_info("No \"pci-host-ecam-generic\" node found, won't fixup\n");
> + return 0;
> + }
> +
> + for (i = 0; i < ARRAY_SIZE(props); i++) {
> + ret = of_property_read_u32_array(np, props[i], map, 4);
> + if (ret) {
> + pr_err("Cannot read \"%s\" property: %pe", props[i], ERR_PTR(ret));
> + return ret;
> + }
> +
> + map[2] = FSL_ECAM_STREAM_ID_START;
> + map[3] = ARRAY_SIZE(ierb_offset);
> + ret = of_property_write_u32_array(np, props[i], map, 4);
> + if (ret) {
> + pr_err("Cannot write \"%s\" property: %pe", props[i], ERR_PTR(ret));
> + return ret;
> + }
> + }
> +
> + return 0;
> +}
> +
> +void ls1028a_setup_icids(void)
> +{
> + setup_icid_offsets(icid_tbl_ls1028a, ARRAY_SIZE(icid_tbl_ls1028a), true);
> +
> + ls1028a_set_ecam_icids();
> +
> + of_register_fixup(of_fixup_icid_ls1028a, NULL);
> + of_register_fixup(of_fixup_ecam_ls1028a, NULL);
> +}
> diff --git a/arch/arm/mach-layerscape/soc.c b/arch/arm/mach-layerscape/soc.c
> index 5f9d0d5171..70c1dedb46 100644
> --- a/arch/arm/mach-layerscape/soc.c
> +++ b/arch/arm/mach-layerscape/soc.c
> @@ -90,6 +90,7 @@ static int ls1028a_init(void)
> return -EINVAL;
>
> layerscape_register_pbl_image_handler();
> + ls1028a_setup_icids();
>
> reserve_sdram_region("tfa", LS1028A_TFA_RESERVED_START, LS1028A_TFA_RESERVED_SIZE);
>
> diff --git a/include/mach/layerscape/layerscape.h b/include/mach/layerscape/layerscape.h
> index 6f420dd4f4..2905360c29 100644
> --- a/include/mach/layerscape/layerscape.h
> +++ b/include/mach/layerscape/layerscape.h
> @@ -58,6 +58,7 @@ void ls1046a_bootsource_init(void);
> void layerscape_register_pbl_image_handler(void);
> void ls102xa_smmu_stream_id_init(void);
> void ls1021a_restart_register_feature(void);
> +void ls1028a_setup_icids(void);
> void ls1046a_setup_icids(void);
>
> #endif /* __MACH_LAYERSCAPE_H */
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 09/10] ARM: psci: make header self contained
2024-01-09 9:15 [PATCH 00/10] Add more Layerscape LS1028a stuff Sascha Hauer
` (7 preceding siblings ...)
2024-01-09 9:16 ` [PATCH 08/10] ARM: Layerscape: LS1028a: fixup icids Sascha Hauer
@ 2024-01-09 9:16 ` Sascha Hauer
2024-01-09 9:27 ` Ahmad Fatoum
2024-01-09 9:16 ` [PATCH 10/10] ARM: Layerscape: LS1028a: fixup psci node Sascha Hauer
9 siblings, 1 reply; 18+ messages in thread
From: Sascha Hauer @ 2024-01-09 9:16 UTC (permalink / raw)
To: Barebox List
arch/arm/include/asm/psci.h uses struct device_node, so include of.h
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/include/asm/psci.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index dbb9adfc3e..f8fc2a8471 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -6,6 +6,8 @@
#ifndef __ARM_PSCI_H__
#define __ARM_PSCI_H__
+#include <of.h>
+
#define ARM_PSCI_VER(major, minor) (((major) << 16) | (minor))
#define ARM_PSCI_VER_1_0 ARM_PSCI_VER(1,0)
#define ARM_PSCI_VER_0_2 ARM_PSCI_VER(0,2)
--
2.39.2
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH 09/10] ARM: psci: make header self contained
2024-01-09 9:16 ` [PATCH 09/10] ARM: psci: make header self contained Sascha Hauer
@ 2024-01-09 9:27 ` Ahmad Fatoum
0 siblings, 0 replies; 18+ messages in thread
From: Ahmad Fatoum @ 2024-01-09 9:27 UTC (permalink / raw)
To: Sascha Hauer, Barebox List
On 09.01.24 10:16, Sascha Hauer wrote:
> arch/arm/include/asm/psci.h uses struct device_node, so include of.h
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> arch/arm/include/asm/psci.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
> index dbb9adfc3e..f8fc2a8471 100644
> --- a/arch/arm/include/asm/psci.h
> +++ b/arch/arm/include/asm/psci.h
> @@ -6,6 +6,8 @@
> #ifndef __ARM_PSCI_H__
> #define __ARM_PSCI_H__
>
> +#include <of.h>
Only a pointer is used, so please just forward declare struct device_node.
Cheers,
Ahmad
> +
> #define ARM_PSCI_VER(major, minor) (((major) << 16) | (minor))
> #define ARM_PSCI_VER_1_0 ARM_PSCI_VER(1,0)
> #define ARM_PSCI_VER_0_2 ARM_PSCI_VER(0,2)
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 10/10] ARM: Layerscape: LS1028a: fixup psci node
2024-01-09 9:15 [PATCH 00/10] Add more Layerscape LS1028a stuff Sascha Hauer
` (8 preceding siblings ...)
2024-01-09 9:16 ` [PATCH 09/10] ARM: psci: make header self contained Sascha Hauer
@ 2024-01-09 9:16 ` Sascha Hauer
2024-01-09 9:26 ` Ahmad Fatoum
9 siblings, 1 reply; 18+ messages in thread
From: Sascha Hauer @ 2024-01-09 9:16 UTC (permalink / raw)
To: Barebox List
The upstream LS1028a dtsi files do not have a psci node, so add one
in a fixup. This is necessary to bring up the secondary CPU core.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-layerscape/Kconfig | 1 +
arch/arm/mach-layerscape/soc.c | 16 ++++++++++++++++
2 files changed, 17 insertions(+)
diff --git a/arch/arm/mach-layerscape/Kconfig b/arch/arm/mach-layerscape/Kconfig
index 5658a63b33..97f2061eee 100644
--- a/arch/arm/mach-layerscape/Kconfig
+++ b/arch/arm/mach-layerscape/Kconfig
@@ -20,6 +20,7 @@ config ARCH_LS1028
select SYS_SUPPORTS_64BIT_KERNEL
select ARM_ATF
select FIRMWARE_LS1028A_ATF
+ select ARM_PSCI_OF
config ARCH_LS1046
bool
diff --git a/arch/arm/mach-layerscape/soc.c b/arch/arm/mach-layerscape/soc.c
index 70c1dedb46..30fbb5d1bf 100644
--- a/arch/arm/mach-layerscape/soc.c
+++ b/arch/arm/mach-layerscape/soc.c
@@ -3,7 +3,9 @@
#include <io.h>
#include <init.h>
#include <memory.h>
+#include <linux/arm-smccc.h>
#include <linux/bug.h>
+#include <asm/psci.h>
#include <mach/layerscape/layerscape.h>
#include <of.h>
@@ -84,6 +86,19 @@ static int ls1021a_init(void)
return 0;
}
+static int ls1028a_psci_fixup(struct device_node *root, void *unused)
+{
+ unsigned long psci_version;
+ struct arm_smccc_res res = {};
+
+ arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
+ psci_version = res.a0;
+
+ of_psci_fixup(root, psci_version, "smc");
+
+ return 0;
+}
+
static int ls1028a_init(void)
{
if (!IS_ENABLED(CONFIG_ARCH_LS1028))
@@ -91,6 +106,7 @@ static int ls1028a_init(void)
layerscape_register_pbl_image_handler();
ls1028a_setup_icids();
+ of_register_fixup(ls1028a_psci_fixup, NULL);
reserve_sdram_region("tfa", LS1028A_TFA_RESERVED_START, LS1028A_TFA_RESERVED_SIZE);
--
2.39.2
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH 10/10] ARM: Layerscape: LS1028a: fixup psci node
2024-01-09 9:16 ` [PATCH 10/10] ARM: Layerscape: LS1028a: fixup psci node Sascha Hauer
@ 2024-01-09 9:26 ` Ahmad Fatoum
2024-01-09 9:37 ` Sascha Hauer
0 siblings, 1 reply; 18+ messages in thread
From: Ahmad Fatoum @ 2024-01-09 9:26 UTC (permalink / raw)
To: Sascha Hauer, Barebox List
Hello Sascha,
On 09.01.24 10:16, Sascha Hauer wrote:
> The upstream LS1028a dtsi files do not have a psci node, so add one
> in a fixup. This is necessary to bring up the secondary CPU core.
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> arch/arm/mach-layerscape/Kconfig | 1 +
> arch/arm/mach-layerscape/soc.c | 16 ++++++++++++++++
> 2 files changed, 17 insertions(+)
>
> diff --git a/arch/arm/mach-layerscape/Kconfig b/arch/arm/mach-layerscape/Kconfig
> index 5658a63b33..97f2061eee 100644
> --- a/arch/arm/mach-layerscape/Kconfig
> +++ b/arch/arm/mach-layerscape/Kconfig
> @@ -20,6 +20,7 @@ config ARCH_LS1028
> select SYS_SUPPORTS_64BIT_KERNEL
> select ARM_ATF
> select FIRMWARE_LS1028A_ATF
> + select ARM_PSCI_OF
>
> config ARCH_LS1046
> bool
> diff --git a/arch/arm/mach-layerscape/soc.c b/arch/arm/mach-layerscape/soc.c
> index 70c1dedb46..30fbb5d1bf 100644
> --- a/arch/arm/mach-layerscape/soc.c
> +++ b/arch/arm/mach-layerscape/soc.c
> @@ -3,7 +3,9 @@
> #include <io.h>
> #include <init.h>
> #include <memory.h>
> +#include <linux/arm-smccc.h>
> #include <linux/bug.h>
> +#include <asm/psci.h>
> #include <mach/layerscape/layerscape.h>
> #include <of.h>
>
> @@ -84,6 +86,19 @@ static int ls1021a_init(void)
> return 0;
> }
>
> +static int ls1028a_psci_fixup(struct device_node *root, void *unused)
> +{
> + unsigned long psci_version;
> + struct arm_smccc_res res = {};
> +
> + arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
> + psci_version = res.a0;
> +
> + of_psci_fixup(root, psci_version, "smc");
Do you have a restart handler registered for LS1028A? If not, you may consider
adding the same node to the barebox device tree node too, so it can use PSCI
to reset the system.
Cheers,
Ahmad
> +
> + return 0;
> +}
> +
> static int ls1028a_init(void)
> {
> if (!IS_ENABLED(CONFIG_ARCH_LS1028))
> @@ -91,6 +106,7 @@ static int ls1028a_init(void)
>
> layerscape_register_pbl_image_handler();
> ls1028a_setup_icids();
> + of_register_fixup(ls1028a_psci_fixup, NULL);
>
> reserve_sdram_region("tfa", LS1028A_TFA_RESERVED_START, LS1028A_TFA_RESERVED_SIZE);
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH 10/10] ARM: Layerscape: LS1028a: fixup psci node
2024-01-09 9:26 ` Ahmad Fatoum
@ 2024-01-09 9:37 ` Sascha Hauer
0 siblings, 0 replies; 18+ messages in thread
From: Sascha Hauer @ 2024-01-09 9:37 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: Barebox List
On Tue, Jan 09, 2024 at 10:26:28AM +0100, Ahmad Fatoum wrote:
> Hello Sascha,
>
> On 09.01.24 10:16, Sascha Hauer wrote:
> > The upstream LS1028a dtsi files do not have a psci node, so add one
> > in a fixup. This is necessary to bring up the secondary CPU core.
> >
> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > ---
> > arch/arm/mach-layerscape/Kconfig | 1 +
> > arch/arm/mach-layerscape/soc.c | 16 ++++++++++++++++
> > 2 files changed, 17 insertions(+)
> >
> > diff --git a/arch/arm/mach-layerscape/Kconfig b/arch/arm/mach-layerscape/Kconfig
> > index 5658a63b33..97f2061eee 100644
> > --- a/arch/arm/mach-layerscape/Kconfig
> > +++ b/arch/arm/mach-layerscape/Kconfig
> > @@ -20,6 +20,7 @@ config ARCH_LS1028
> > select SYS_SUPPORTS_64BIT_KERNEL
> > select ARM_ATF
> > select FIRMWARE_LS1028A_ATF
> > + select ARM_PSCI_OF
> >
> > config ARCH_LS1046
> > bool
> > diff --git a/arch/arm/mach-layerscape/soc.c b/arch/arm/mach-layerscape/soc.c
> > index 70c1dedb46..30fbb5d1bf 100644
> > --- a/arch/arm/mach-layerscape/soc.c
> > +++ b/arch/arm/mach-layerscape/soc.c
> > @@ -3,7 +3,9 @@
> > #include <io.h>
> > #include <init.h>
> > #include <memory.h>
> > +#include <linux/arm-smccc.h>
> > #include <linux/bug.h>
> > +#include <asm/psci.h>
> > #include <mach/layerscape/layerscape.h>
> > #include <of.h>
> >
> > @@ -84,6 +86,19 @@ static int ls1021a_init(void)
> > return 0;
> > }
> >
> > +static int ls1028a_psci_fixup(struct device_node *root, void *unused)
> > +{
> > + unsigned long psci_version;
> > + struct arm_smccc_res res = {};
> > +
> > + arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
> > + psci_version = res.a0;
> > +
> > + of_psci_fixup(root, psci_version, "smc");
>
> Do you have a restart handler registered for LS1028A? If not, you may consider
> adding the same node to the barebox device tree node too, so it can use PSCI
> to reset the system.
Will do. This makes this patch unnecessary as the existing PSCI client
support will automatically add a PSCI node to the dtb the Kernel is
started with.
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 18+ messages in thread