* [PATCH v2 01/21] memory: Fix reserve_sdram_region() return value
2024-01-09 16:15 [PATCH v2 00/21] Add more Layerscape LS1028a stuff Sascha Hauer
@ 2024-01-09 16:15 ` Sascha Hauer
2024-01-09 16:15 ` [PATCH v2 02/21] ARM: Layerscape: consolidate initcalls into one Sascha Hauer
` (19 subsequent siblings)
20 siblings, 0 replies; 22+ messages in thread
From: Sascha Hauer @ 2024-01-09 16:15 UTC (permalink / raw)
To: Barebox List
__request_sdram_region() returns NULL on failure, so test for this value
and not for an error pointer. Also all callers of reserve_sdram_region()
expect NULL on failure, so return that value in case of failure.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
common/memory.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/common/memory.c b/common/memory.c
index 300320f853..583843cc34 100644
--- a/common/memory.c
+++ b/common/memory.c
@@ -229,8 +229,8 @@ struct resource *reserve_sdram_region(const char *name, resource_size_t start,
}
res = __request_sdram_region(name, IORESOURCE_BUSY, start, size);
- if (IS_ERR(res))
- return ERR_CAST(res);
+ if (!res)
+ return NULL;
remap_range((void *)start, size, MAP_UNCACHED);
--
2.39.2
^ permalink raw reply [flat|nested] 22+ messages in thread* [PATCH v2 02/21] ARM: Layerscape: consolidate initcalls into one
2024-01-09 16:15 [PATCH v2 00/21] Add more Layerscape LS1028a stuff Sascha Hauer
2024-01-09 16:15 ` [PATCH v2 01/21] memory: Fix reserve_sdram_region() return value Sascha Hauer
@ 2024-01-09 16:15 ` Sascha Hauer
2024-01-09 16:15 ` [PATCH v2 03/21] ARM: Layerscape: LS1028a: reserve DDR region for TF-A Sascha Hauer
` (18 subsequent siblings)
20 siblings, 0 replies; 22+ messages in thread
From: Sascha Hauer @ 2024-01-09 16:15 UTC (permalink / raw)
To: Barebox List
For Layerscape we have multiple initcalls in the arch directory.
Consolidate these into one initcall which detects the SoC type once
and calls the appropriate init functions. This makes it easier to
add future init steps and also we reduce the number of string
comparisons.
For added value also cpu_is_ls10xx() functions are added which might
become in handy later.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-layerscape/boot.c | 13 ++--
arch/arm/mach-layerscape/icid.c | 9 +--
arch/arm/mach-layerscape/ls102xa_stream_id.c | 8 +-
arch/arm/mach-layerscape/pblimage.c | 6 +-
arch/arm/mach-layerscape/restart.c | 8 +-
arch/arm/mach-layerscape/soc.c | 77 ++++++++++++++++++++
include/mach/layerscape/layerscape.h | 31 ++++++++
7 files changed, 120 insertions(+), 32 deletions(-)
diff --git a/arch/arm/mach-layerscape/boot.c b/arch/arm/mach-layerscape/boot.c
index da61763bd5..26a7a1434a 100644
--- a/arch/arm/mach-layerscape/boot.c
+++ b/arch/arm/mach-layerscape/boot.c
@@ -32,13 +32,12 @@ enum bootsource ls1021a_bootsource_get(void)
return ls1046a_bootsource_get();
}
-static int layerscape_bootsource_init(void)
+void ls1021a_bootsource_init(void)
{
- if (of_machine_is_compatible("fsl,ls1046a"))
- bootsource_set_raw(ls1046a_bootsource_get(), BOOTSOURCE_INSTANCE_UNKNOWN);
- if (of_machine_is_compatible("fsl,ls1021a"))
- bootsource_set_raw(ls1021a_bootsource_get(), BOOTSOURCE_INSTANCE_UNKNOWN);
+ bootsource_set_raw(ls1021a_bootsource_get(), BOOTSOURCE_INSTANCE_UNKNOWN);
+}
- return 0;
+void ls1046a_bootsource_init(void)
+{
+ bootsource_set_raw(ls1046a_bootsource_get(), BOOTSOURCE_INSTANCE_UNKNOWN);
}
-coredevice_initcall(layerscape_bootsource_init);
diff --git a/arch/arm/mach-layerscape/icid.c b/arch/arm/mach-layerscape/icid.c
index d1d623416a..f5188fc91e 100644
--- a/arch/arm/mach-layerscape/icid.c
+++ b/arch/arm/mach-layerscape/icid.c
@@ -7,6 +7,7 @@
#include <soc/fsl/immap_lsch2.h>
#include <soc/fsl/fsl_qbman.h>
#include <soc/fsl/fsl_fman.h>
+#include <mach/layerscape/layerscape.h>
/*
* Stream IDs on Chassis-2 (for example ls1043a, ls1046a, ls1012) devices
@@ -530,14 +531,11 @@ static int icid_of_fixup(struct device_node *root, void *context)
return 0;
}
-static int layerscape_setup_icids(void)
+void ls1046a_setup_icids(void)
{
int i;
struct ccsr_fman *fm = (void *)LSCH2_FM1_ADDR;
- if (!of_machine_is_compatible("fsl,ls1046a"))
- return 0;
-
/* setup general icid offsets */
for (i = 0; i < ARRAY_SIZE(icid_tbl_ls1046a); i++) {
struct icid_id_table *icid = &icid_tbl_ls1046a[i];
@@ -556,7 +554,4 @@ static int layerscape_setup_icids(void)
setup_qbman_portals();
of_register_fixup(icid_of_fixup, NULL);
-
- return 0;
}
-coredevice_initcall(layerscape_setup_icids);
diff --git a/arch/arm/mach-layerscape/ls102xa_stream_id.c b/arch/arm/mach-layerscape/ls102xa_stream_id.c
index c47c463b48..60723ce2e7 100644
--- a/arch/arm/mach-layerscape/ls102xa_stream_id.c
+++ b/arch/arm/mach-layerscape/ls102xa_stream_id.c
@@ -43,13 +43,7 @@ ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num)
}
}
-static int ls102xa_smmu_stream_id_init(void)
+void ls102xa_smmu_stream_id_init(void)
{
- if (!of_machine_is_compatible("fsl,ls1021a"))
- return 0;
-
ls102xa_config_smmu_stream_id(dev_stream_id, ARRAY_SIZE(dev_stream_id));
-
- return 0;
}
-mmu_initcall(ls102xa_smmu_stream_id_init);
diff --git a/arch/arm/mach-layerscape/pblimage.c b/arch/arm/mach-layerscape/pblimage.c
index 26345af276..5a525f0933 100644
--- a/arch/arm/mach-layerscape/pblimage.c
+++ b/arch/arm/mach-layerscape/pblimage.c
@@ -7,6 +7,7 @@
#include <init.h>
#include <memory.h>
#include <linux/sizes.h>
+#include <mach/layerscape/layerscape.h>
#define BAREBOX_STAGE2_OFFSET SZ_128K
@@ -50,11 +51,8 @@ static struct image_handler image_handler_layerscape_qspi_pbl_image = {
.filetype = filetype_layerscape_qspi_image,
};
-static int layerscape_register_pbl_image_handler(void)
+void layerscape_register_pbl_image_handler(void)
{
register_image_handler(&image_handler_layerscape_pbl_image);
register_image_handler(&image_handler_layerscape_qspi_pbl_image);
-
- return 0;
}
-late_initcall(layerscape_register_pbl_image_handler);
diff --git a/arch/arm/mach-layerscape/restart.c b/arch/arm/mach-layerscape/restart.c
index e8bd041ebf..a6daa9b677 100644
--- a/arch/arm/mach-layerscape/restart.c
+++ b/arch/arm/mach-layerscape/restart.c
@@ -18,13 +18,7 @@ static void ls102xa_restart(struct restart_handler *rst)
hang();
}
-static int restart_register_feature(void)
+void ls1021a_restart_register_feature(void)
{
- if (!of_machine_is_compatible("fsl,ls1021a"))
- return 0;
-
restart_handler_register_fn("soc-reset", ls102xa_restart);
-
- return 0;
}
-coredevice_initcall(restart_register_feature);
diff --git a/arch/arm/mach-layerscape/soc.c b/arch/arm/mach-layerscape/soc.c
index 2d9a2b4629..b4c9dd5828 100644
--- a/arch/arm/mach-layerscape/soc.c
+++ b/arch/arm/mach-layerscape/soc.c
@@ -1,7 +1,13 @@
// SPDX-License-Identifier: GPL-2.0-only
#include <soc/fsl/scfg.h>
#include <io.h>
+#include <init.h>
+#include <memory.h>
#include <linux/bug.h>
+#include <mach/layerscape/layerscape.h>
+#include <of.h>
+
+int __layerscape_soc_type;
static enum scfg_endianess scfg_endianess = SCFG_ENDIANESS_INVALID;
@@ -54,3 +60,74 @@ void scfg_init(enum scfg_endianess endianess)
{
scfg_endianess = endianess;
}
+
+static int layerscape_soc_from_dt(void)
+{
+ if (of_machine_is_compatible("fsl,ls1021a"))
+ return LAYERSCAPE_SOC_LS1021A;
+ if (of_machine_is_compatible("fsl,ls1028a"))
+ return LAYERSCAPE_SOC_LS1028A;
+ if (of_machine_is_compatible("fsl,ls1046a"))
+ return LAYERSCAPE_SOC_LS1046A;
+
+ return 0;
+}
+
+static int ls1021a_init(void)
+{
+ if (!cpu_is_ls1021a())
+ return -EINVAL;
+
+ ls1021a_bootsource_init();
+ ls102xa_smmu_stream_id_init();
+ layerscape_register_pbl_image_handler();
+ ls1021a_restart_register_feature();
+
+ return 0;
+}
+
+static int ls1028a_init(void)
+{
+ if (!cpu_is_ls1028a())
+ return -EINVAL;
+
+ layerscape_register_pbl_image_handler();
+
+ return 0;
+}
+
+static int ls1046a_init(void)
+{
+ if (!cpu_is_ls1046a())
+ return -EINVAL;
+
+ ls1046a_bootsource_init();
+ ls1046a_setup_icids();
+ layerscape_register_pbl_image_handler();
+
+ return 0;
+}
+
+static int layerscape_init(void)
+{
+ struct device_node *root;
+
+ root = of_get_root_node();
+ if (root) {
+ __layerscape_soc_type = layerscape_soc_from_dt();
+ if (!__layerscape_soc_type)
+ return 0;
+ }
+
+ switch (__layerscape_soc_type) {
+ case LAYERSCAPE_SOC_LS1021A:
+ return ls1021a_init();
+ case LAYERSCAPE_SOC_LS1028A:
+ return ls1028a_init();
+ case LAYERSCAPE_SOC_LS1046A:
+ return ls1046a_init();
+ }
+
+ return 0;
+}
+postcore_initcall(layerscape_init);
diff --git a/include/mach/layerscape/layerscape.h b/include/mach/layerscape/layerscape.h
index ceb7b983f6..ca1710d7bc 100644
--- a/include/mach/layerscape/layerscape.h
+++ b/include/mach/layerscape/layerscape.h
@@ -19,6 +19,10 @@
enum bootsource ls1046a_bootsource_get(void);
enum bootsource ls1021a_bootsource_get(void);
+#define LAYERSCAPE_SOC_LS1021A 1021
+#define LAYERSCAPE_SOC_LS1028A 1028
+#define LAYERSCAPE_SOC_LS1046A 1046
+
#ifdef CONFIG_ARCH_LAYERSCAPE_PPA
int ls1046a_ppa_init(resource_size_t ppa_start, resource_size_t ppa_size);
#else
@@ -41,4 +45,31 @@ struct dram_regions_info {
struct dram_region_info region[NUM_DRAM_REGIONS];
};
+void ls1021a_bootsource_init(void);
+void ls1046a_bootsource_init(void);
+void layerscape_register_pbl_image_handler(void);
+void ls102xa_smmu_stream_id_init(void);
+void ls1021a_restart_register_feature(void);
+void ls1046a_setup_icids(void);
+
+extern int __layerscape_soc_type;
+
+static inline bool cpu_is_ls1021a(void)
+{
+ return IS_ENABLED(CONFIG_ARCH_LS1021) &&
+ __layerscape_soc_type == LAYERSCAPE_SOC_LS1021A;
+}
+
+static inline bool cpu_is_ls1028a(void)
+{
+ return IS_ENABLED(CONFIG_ARCH_LS1028) &&
+ __layerscape_soc_type == LAYERSCAPE_SOC_LS1028A;
+}
+
+static inline bool cpu_is_ls1046a(void)
+{
+ return IS_ENABLED(CONFIG_ARCH_LS1046) &&
+ __layerscape_soc_type == LAYERSCAPE_SOC_LS1046A;
+}
+
#endif /* __MACH_LAYERSCAPE_H */
--
2.39.2
^ permalink raw reply [flat|nested] 22+ messages in thread* [PATCH v2 03/21] ARM: Layerscape: LS1028a: reserve DDR region for TF-A
2024-01-09 16:15 [PATCH v2 00/21] Add more Layerscape LS1028a stuff Sascha Hauer
2024-01-09 16:15 ` [PATCH v2 01/21] memory: Fix reserve_sdram_region() return value Sascha Hauer
2024-01-09 16:15 ` [PATCH v2 02/21] ARM: Layerscape: consolidate initcalls into one Sascha Hauer
@ 2024-01-09 16:15 ` Sascha Hauer
2024-01-09 16:15 ` [PATCH v2 04/21] ARM: Layerscape: icid: make readonly arrays const Sascha Hauer
` (17 subsequent siblings)
20 siblings, 0 replies; 22+ messages in thread
From: Sascha Hauer @ 2024-01-09 16:15 UTC (permalink / raw)
To: Barebox List
On LS1028a the TF-A is placed in DDR, so we have to reserve the region
in order to keep Linux away from it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-layerscape/soc.c | 22 ++++++++++++++++++++++
drivers/mci/imx-esdhc-pbl.c | 3 ++-
include/mach/layerscape/layerscape.h | 8 ++++++++
3 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-layerscape/soc.c b/arch/arm/mach-layerscape/soc.c
index b4c9dd5828..8507a66ff6 100644
--- a/arch/arm/mach-layerscape/soc.c
+++ b/arch/arm/mach-layerscape/soc.c
@@ -4,6 +4,7 @@
#include <init.h>
#include <memory.h>
#include <linux/bug.h>
+#include <linux/printk.h>
#include <mach/layerscape/layerscape.h>
#include <of.h>
@@ -96,6 +97,27 @@ static int ls1028a_init(void)
return 0;
}
+static int ls1028a_reserve_tfa(void)
+{
+ resource_size_t tfa_start = LS1028A_TFA_RESERVED_START;
+ resource_size_t tfa_size = LS1028A_TFA_RESERVED_SIZE;
+ struct resource *res;
+
+ if (!cpu_is_ls1028a())
+ return 0;
+
+ res = reserve_sdram_region("tfa", tfa_start, tfa_size);
+ if (!res) {
+ pr_err("Cannot request SDRAM region %pa - %pa\n", &tfa_start, &tfa_size);
+ return -EINVAL;
+ }
+
+ of_register_fixup(of_fixup_reserved_memory, res);
+
+ return 0;
+}
+mmu_initcall(ls1028a_reserve_tfa);
+
static int ls1046a_init(void)
{
if (!cpu_is_ls1046a())
diff --git a/drivers/mci/imx-esdhc-pbl.c b/drivers/mci/imx-esdhc-pbl.c
index 2c74d101e4..2d071eaca8 100644
--- a/drivers/mci/imx-esdhc-pbl.c
+++ b/drivers/mci/imx-esdhc-pbl.c
@@ -21,6 +21,7 @@
#endif
#ifdef CONFIG_ARCH_LAYERSCAPE
#include <mach/layerscape/xload.h>
+#include <mach/layerscape/layerscape.h>
#endif
#include "sdhci.h"
#include "imx-esdhc.h"
@@ -387,7 +388,7 @@ static int ls1028a_esdhc_start_image(void __iomem *base, struct dram_regions_inf
.socdata = &data,
};
void *sdram = (void *)0x80000000;
- void (*bl31)(void) = (void *)0xfbe00000;
+ void (*bl31)(void) = (void *)LS1028A_TFA_RESERVED_START;
size_t bl31_size;
void *bl31_image;
struct bl2_to_bl31_params_mem_v2 *params;
diff --git a/include/mach/layerscape/layerscape.h b/include/mach/layerscape/layerscape.h
index ca1710d7bc..3dacfcb29f 100644
--- a/include/mach/layerscape/layerscape.h
+++ b/include/mach/layerscape/layerscape.h
@@ -3,6 +3,8 @@
#ifndef __MACH_LAYERSCAPE_H
#define __MACH_LAYERSCAPE_H
+#include <linux/sizes.h>
+
#define LS1046A_DDR_SDRAM_BASE 0x80000000
#define LS1046A_DDR_FREQ 2100000000
@@ -16,6 +18,12 @@
#define LS1028A_SP_SHARED_DRAM_SIZE SZ_2M
#define LS1028A_TZC400_BASE 0x01100000
+#define LS1028A_TFA_SIZE SZ_64M
+#define LS1028A_TFA_SHRD SZ_2M
+#define LS1028A_TFA_RESERVED_SIZE (LS1028A_TFA_SIZE + LS1028A_TFA_SHRD)
+#define LS1028A_TFA_RESERVED_START (0x100000000 - LS1028A_TFA_RESERVED_SIZE)
+#define LS1028A_TFA_START (0x100000000 - LS1028A_TFA_SIZE)
+
enum bootsource ls1046a_bootsource_get(void);
enum bootsource ls1021a_bootsource_get(void);
--
2.39.2
^ permalink raw reply [flat|nested] 22+ messages in thread* [PATCH v2 04/21] ARM: Layerscape: icid: make readonly arrays const
2024-01-09 16:15 [PATCH v2 00/21] Add more Layerscape LS1028a stuff Sascha Hauer
` (2 preceding siblings ...)
2024-01-09 16:15 ` [PATCH v2 03/21] ARM: Layerscape: LS1028a: reserve DDR region for TF-A Sascha Hauer
@ 2024-01-09 16:15 ` Sascha Hauer
2024-01-09 16:15 ` [PATCH v2 05/21] ARM: Layerscape: icid: rename functions Sascha Hauer
` (16 subsequent siblings)
20 siblings, 0 replies; 22+ messages in thread
From: Sascha Hauer @ 2024-01-09 16:15 UTC (permalink / raw)
To: Barebox List
Several arrays used in icid.c are statically initialised and not
modified during runtime. Also they are only used locally, so make
them static const.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-layerscape/icid.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-layerscape/icid.c b/arch/arm/mach-layerscape/icid.c
index f5188fc91e..11fab9c3b9 100644
--- a/arch/arm/mach-layerscape/icid.c
+++ b/arch/arm/mach-layerscape/icid.c
@@ -81,7 +81,7 @@ struct fman_icid_id_table {
#define SEC_QIIC_LS 0x70024
#define SEC_IRBAR_JRn(n) (0x10000 * ((n) + 1))
-struct icid_id_table icid_tbl_ls1046a[] = {
+static const struct icid_id_table icid_tbl_ls1046a[] = {
{
.compat = "fsl,qman",
.id = DPAA1_SID_START,
@@ -209,7 +209,7 @@ struct icid_id_table icid_tbl_ls1046a[] = {
},
};
-struct fman_icid_id_table fman_icid_tbl_ls1046a[] = {
+static const struct fman_icid_id_table fman_icid_tbl_ls1046a[] = {
{
.port_id = 0x02,
.icid = DPAA1_SID_END,
@@ -279,7 +279,7 @@ struct fman_icid_id_table fman_icid_tbl_ls1046a[] = {
},
};
-static int get_fman_port_icid(int port_id, struct fman_icid_id_table *tbl,
+static int get_fman_port_icid(int port_id, const struct fman_icid_id_table *tbl,
const int size)
{
int i;
@@ -348,7 +348,7 @@ struct qportal_info {
u8 sdest;
};
-struct qportal_info qp_info[] = {
+static const struct qportal_info qp_info[] = {
{
.dicid = DPAA1_SID_END,
.ficid = DPAA1_SID_END,
@@ -440,7 +440,7 @@ static void setup_qbman_portals(void)
out_be32(&qman->qcsp_bar, (u32)QMAN_MEM_PHYS);
for (i = 0; i < ARRAY_SIZE(qp_info); i++) {
- struct qportal_info *qi = &qp_info[i];
+ const struct qportal_info *qi = &qp_info[i];
out_be32(&qman->qcsp[i].qcsp_lio_cfg, (qi->icid << 16) | qi->dicid);
/* set frame icid */
@@ -453,7 +453,7 @@ static void setup_qbman_portals(void)
}
static void fdt_set_qportal_iommu_prop(struct device_node *np, phandle iommu_handle,
- struct qportal_info *qp_info)
+ const struct qportal_info *qp_info)
{
u32 prop[6];
@@ -506,7 +506,7 @@ static int icid_of_fixup(struct device_node *root, void *context)
iommu_handle = of_node_create_phandle(iommu);
for (i = 0; i < ARRAY_SIZE(icid_tbl_ls1046a); i++) {
- struct icid_id_table *icid = &icid_tbl_ls1046a[i];
+ const struct icid_id_table *icid = &icid_tbl_ls1046a[i];
struct device_node *np;
if (!icid->compat)
@@ -538,14 +538,14 @@ void ls1046a_setup_icids(void)
/* setup general icid offsets */
for (i = 0; i < ARRAY_SIZE(icid_tbl_ls1046a); i++) {
- struct icid_id_table *icid = &icid_tbl_ls1046a[i];
+ const struct icid_id_table *icid = &icid_tbl_ls1046a[i];
out_be32((u32 *)(icid->reg_addr), icid->reg);
}
/* setup fman icids */
for (i = 0; i < ARRAY_SIZE(fman_icid_tbl_ls1046a); i++) {
- struct fman_icid_id_table *icid = &fman_icid_tbl_ls1046a[i];
+ const struct fman_icid_id_table *icid = &fman_icid_tbl_ls1046a[i];
out_be32(&fm->fm_bmi_common.fmbm_ppid[icid->port_id - 1],
icid->icid);
--
2.39.2
^ permalink raw reply [flat|nested] 22+ messages in thread* [PATCH v2 05/21] ARM: Layerscape: icid: rename functions
2024-01-09 16:15 [PATCH v2 00/21] Add more Layerscape LS1028a stuff Sascha Hauer
` (3 preceding siblings ...)
2024-01-09 16:15 ` [PATCH v2 04/21] ARM: Layerscape: icid: make readonly arrays const Sascha Hauer
@ 2024-01-09 16:15 ` Sascha Hauer
2024-01-09 16:15 ` [PATCH v2 06/21] ARM: Layerscape: icid: move re-usable code to separate functions Sascha Hauer
` (15 subsequent siblings)
20 siblings, 0 replies; 22+ messages in thread
From: Sascha Hauer @ 2024-01-09 16:15 UTC (permalink / raw)
To: Barebox List
We are working on unflattened trees, so use the more appropriate
function prefix "of_" rather than "fdt_"
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-layerscape/icid.c | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/arch/arm/mach-layerscape/icid.c b/arch/arm/mach-layerscape/icid.c
index 11fab9c3b9..f0a9dc8063 100644
--- a/arch/arm/mach-layerscape/icid.c
+++ b/arch/arm/mach-layerscape/icid.c
@@ -292,7 +292,7 @@ static int get_fman_port_icid(int port_id, const struct fman_icid_id_table *tbl,
return -ENODEV;
}
-static void fdt_set_iommu_prop(struct device_node *np, phandle iommu_handle,
+static void of_set_iommu_prop(struct device_node *np, phandle iommu_handle,
int stream_id)
{
u32 prop[2];
@@ -303,7 +303,7 @@ static void fdt_set_iommu_prop(struct device_node *np, phandle iommu_handle,
of_set_property(np, "iommus", prop, sizeof(prop), 1);
}
-static void fdt_fixup_fman_port_icid_by_compat(struct device_node *root,
+static void of_fixup_fman_port_icid_by_compat(struct device_node *root,
phandle iommu_handle,
const char *compat)
{
@@ -324,11 +324,11 @@ static void fdt_fixup_fman_port_icid_by_compat(struct device_node *root,
continue;
}
- fdt_set_iommu_prop(np, iommu_handle, icid);
+ of_set_iommu_prop(np, iommu_handle, icid);
}
}
-static void fdt_fixup_fman_icids(struct device_node *root, phandle iommu_handle)
+static void of_fixup_fman_icids(struct device_node *root, phandle iommu_handle)
{
static const char * const compats[] = {
"fsl,fman-v3-port-oh",
@@ -338,7 +338,7 @@ static void fdt_fixup_fman_icids(struct device_node *root, phandle iommu_handle)
int i;
for (i = 0; i < ARRAY_SIZE(compats); i++)
- fdt_fixup_fman_port_icid_by_compat(root, iommu_handle, compats[i]);
+ of_fixup_fman_port_icid_by_compat(root, iommu_handle, compats[i]);
}
struct qportal_info {
@@ -452,7 +452,7 @@ static void setup_qbman_portals(void)
inhibit_portals(qpaddr, ARRAY_SIZE(qp_info), QMAN_SP_CINH_SIZE);
}
-static void fdt_set_qportal_iommu_prop(struct device_node *np, phandle iommu_handle,
+static void of_set_qportal_iommu_prop(struct device_node *np, phandle iommu_handle,
const struct qportal_info *qp_info)
{
u32 prop[6];
@@ -467,7 +467,7 @@ static void fdt_set_qportal_iommu_prop(struct device_node *np, phandle iommu_han
of_set_property(np, "iommus", prop, sizeof(prop), 1);
}
-static void fdt_fixup_qportals(struct device_node *root, phandle iommu_handle)
+static void of_fixup_qportals(struct device_node *root, phandle iommu_handle)
{
struct device_node *np;
unsigned int maj, min;
@@ -487,7 +487,7 @@ static void fdt_fixup_qportals(struct device_node *root, phandle iommu_handle)
if (ret)
continue;
- fdt_set_qportal_iommu_prop(np, iommu_handle, &qp_info[cell_index]);
+ of_set_qportal_iommu_prop(np, iommu_handle, &qp_info[cell_index]);
}
}
@@ -519,14 +519,14 @@ static int icid_of_fixup(struct device_node *root, void *context)
continue;
if (res.start == icid->compat_addr) {
- fdt_set_iommu_prop(np, iommu_handle, icid->id);
+ of_set_iommu_prop(np, iommu_handle, icid->id);
break;
}
}
}
- fdt_fixup_fman_icids(root, iommu_handle);
- fdt_fixup_qportals(root, iommu_handle);
+ of_fixup_fman_icids(root, iommu_handle);
+ of_fixup_qportals(root, iommu_handle);
return 0;
}
--
2.39.2
^ permalink raw reply [flat|nested] 22+ messages in thread* [PATCH v2 06/21] ARM: Layerscape: icid: move re-usable code to separate functions
2024-01-09 16:15 [PATCH v2 00/21] Add more Layerscape LS1028a stuff Sascha Hauer
` (4 preceding siblings ...)
2024-01-09 16:15 ` [PATCH v2 05/21] ARM: Layerscape: icid: rename functions Sascha Hauer
@ 2024-01-09 16:15 ` Sascha Hauer
2024-01-09 16:15 ` [PATCH v2 07/21] ARM: Layerscape: icid: use of_property_write_u32_array() in of_set_iommu_prop() Sascha Hauer
` (14 subsequent siblings)
20 siblings, 0 replies; 22+ messages in thread
From: Sascha Hauer @ 2024-01-09 16:15 UTC (permalink / raw)
To: Barebox List
Create separate functions from code that can be re-used by upcoming
LS1028a support.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-layerscape/icid.c | 98 +++++++++++++++++++--------------
1 file changed, 57 insertions(+), 41 deletions(-)
diff --git a/arch/arm/mach-layerscape/icid.c b/arch/arm/mach-layerscape/icid.c
index f0a9dc8063..dd0e160bde 100644
--- a/arch/arm/mach-layerscape/icid.c
+++ b/arch/arm/mach-layerscape/icid.c
@@ -68,6 +68,58 @@ struct icid_id_table {
phys_addr_t reg_addr;
};
+static void of_set_iommu_prop(struct device_node *np, phandle iommu_handle,
+ int stream_id)
+{
+ u32 prop[2];
+
+ prop[0] = cpu_to_fdt32(iommu_handle);
+ prop[1] = cpu_to_fdt32(stream_id);
+
+ of_set_property(np, "iommus", prop, sizeof(prop), 1);
+}
+
+static phandle of_get_iommu_handle(struct device_node *root)
+{
+ struct device_node *iommu;
+
+ iommu = of_find_compatible_node(root, NULL, "arm,mmu-500");
+ if (!iommu) {
+ pr_info("No \"arm,mmu-500\" node found, won't fixup\n");
+ return 0;
+ }
+
+ return of_node_create_phandle(iommu);
+}
+
+static int of_fixup_icid(struct device_node *root, phandle iommu_handle,
+ const struct icid_id_table *icid_table, int num_icid)
+{
+ int i;
+
+ for (i = 0; i < num_icid; i++) {
+ const struct icid_id_table *icid = &icid_table[i];
+ struct device_node *np;
+
+ if (!icid->compat)
+ continue;
+
+ for_each_compatible_node_from(np, root, NULL, icid->compat) {
+ struct resource res;
+
+ if (of_address_to_resource(np, 0, &res))
+ continue;
+
+ if (res.start == icid->compat_addr) {
+ of_set_iommu_prop(np, iommu_handle, icid->id);
+ break;
+ }
+ }
+ }
+
+ return 0;
+}
+
struct fman_icid_id_table {
u32 port_id;
u32 icid;
@@ -292,17 +344,6 @@ static int get_fman_port_icid(int port_id, const struct fman_icid_id_table *tbl,
return -ENODEV;
}
-static void of_set_iommu_prop(struct device_node *np, phandle iommu_handle,
- int stream_id)
-{
- u32 prop[2];
-
- prop[0] = cpu_to_fdt32(iommu_handle);
- prop[1] = cpu_to_fdt32(stream_id);
-
- of_set_property(np, "iommus", prop, sizeof(prop), 1);
-}
-
static void of_fixup_fman_port_icid_by_compat(struct device_node *root,
phandle iommu_handle,
const char *compat)
@@ -491,40 +532,15 @@ static void of_fixup_qportals(struct device_node *root, phandle iommu_handle)
}
}
-static int icid_of_fixup(struct device_node *root, void *context)
+static int of_fixup_ls1046a(struct device_node *root, void *context)
{
- int i;
- struct device_node *iommu;
phandle iommu_handle;
- iommu = of_find_compatible_node(root, NULL, "arm,mmu-500");
- if (!iommu) {
- pr_info("No \"arm,mmu-500\" node found, won't fixup\n");
+ iommu_handle = of_get_iommu_handle(root);
+ if (!iommu_handle)
return 0;
- }
-
- iommu_handle = of_node_create_phandle(iommu);
-
- for (i = 0; i < ARRAY_SIZE(icid_tbl_ls1046a); i++) {
- const struct icid_id_table *icid = &icid_tbl_ls1046a[i];
- struct device_node *np;
-
- if (!icid->compat)
- continue;
-
- for_each_compatible_node_from(np, root, NULL, icid->compat) {
- struct resource res;
-
- if (of_address_to_resource(np, 0, &res))
- continue;
-
- if (res.start == icid->compat_addr) {
- of_set_iommu_prop(np, iommu_handle, icid->id);
- break;
- }
- }
- }
+ of_fixup_icid(root, iommu_handle, icid_tbl_ls1046a, ARRAY_SIZE(icid_tbl_ls1046a));
of_fixup_fman_icids(root, iommu_handle);
of_fixup_qportals(root, iommu_handle);
@@ -553,5 +569,5 @@ void ls1046a_setup_icids(void)
setup_qbman_portals();
- of_register_fixup(icid_of_fixup, NULL);
+ of_register_fixup(of_fixup_ls1046a, NULL);
}
--
2.39.2
^ permalink raw reply [flat|nested] 22+ messages in thread* [PATCH v2 07/21] ARM: Layerscape: icid: use of_property_write_u32_array() in of_set_iommu_prop()
2024-01-09 16:15 [PATCH v2 00/21] Add more Layerscape LS1028a stuff Sascha Hauer
` (5 preceding siblings ...)
2024-01-09 16:15 ` [PATCH v2 06/21] ARM: Layerscape: icid: move re-usable code to separate functions Sascha Hauer
@ 2024-01-09 16:15 ` Sascha Hauer
2024-01-09 16:15 ` [PATCH v2 08/21] ARM: Layerscape: icid: use of_property_write_u32_array() in of_set_qportal_iommu_prop() Sascha Hauer
` (13 subsequent siblings)
20 siblings, 0 replies; 22+ messages in thread
From: Sascha Hauer @ 2024-01-09 16:15 UTC (permalink / raw)
To: Barebox List
Use of_property_write_u32_array() rather than of_set_property()
to make the code a bit clearer.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-layerscape/icid.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-layerscape/icid.c b/arch/arm/mach-layerscape/icid.c
index dd0e160bde..2e0b4a64df 100644
--- a/arch/arm/mach-layerscape/icid.c
+++ b/arch/arm/mach-layerscape/icid.c
@@ -71,12 +71,12 @@ struct icid_id_table {
static void of_set_iommu_prop(struct device_node *np, phandle iommu_handle,
int stream_id)
{
- u32 prop[2];
-
- prop[0] = cpu_to_fdt32(iommu_handle);
- prop[1] = cpu_to_fdt32(stream_id);
+ u32 prop[] = {
+ iommu_handle,
+ stream_id
+ };
- of_set_property(np, "iommus", prop, sizeof(prop), 1);
+ of_property_write_u32_array(np, "iommus", prop, ARRAY_SIZE(prop));
}
static phandle of_get_iommu_handle(struct device_node *root)
--
2.39.2
^ permalink raw reply [flat|nested] 22+ messages in thread* [PATCH v2 08/21] ARM: Layerscape: icid: use of_property_write_u32_array() in of_set_qportal_iommu_prop()
2024-01-09 16:15 [PATCH v2 00/21] Add more Layerscape LS1028a stuff Sascha Hauer
` (6 preceding siblings ...)
2024-01-09 16:15 ` [PATCH v2 07/21] ARM: Layerscape: icid: use of_property_write_u32_array() in of_set_iommu_prop() Sascha Hauer
@ 2024-01-09 16:15 ` Sascha Hauer
2024-01-09 16:15 ` [PATCH v2 09/21] ARM: Layerscape: icid: factor out setup_icid_offsets() Sascha Hauer
` (12 subsequent siblings)
20 siblings, 0 replies; 22+ messages in thread
From: Sascha Hauer @ 2024-01-09 16:15 UTC (permalink / raw)
To: Barebox List
Use of_property_write_u32_array() rather than of_set_property()
to make the code a bit clearer.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-layerscape/icid.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-layerscape/icid.c b/arch/arm/mach-layerscape/icid.c
index 2e0b4a64df..1055cf59da 100644
--- a/arch/arm/mach-layerscape/icid.c
+++ b/arch/arm/mach-layerscape/icid.c
@@ -496,16 +496,16 @@ static void setup_qbman_portals(void)
static void of_set_qportal_iommu_prop(struct device_node *np, phandle iommu_handle,
const struct qportal_info *qp_info)
{
- u32 prop[6];
-
- prop[0] = cpu_to_fdt32(iommu_handle);
- prop[1] = cpu_to_fdt32(qp_info->icid);
- prop[2] = cpu_to_fdt32(iommu_handle);
- prop[3] = cpu_to_fdt32(qp_info->dicid);
- prop[4] = cpu_to_fdt32(iommu_handle);
- prop[5] = cpu_to_fdt32(qp_info->ficid);
+ u32 prop[] = {
+ iommu_handle,
+ qp_info->icid,
+ iommu_handle,
+ qp_info->dicid,
+ iommu_handle,
+ qp_info->ficid
+ };
- of_set_property(np, "iommus", prop, sizeof(prop), 1);
+ of_property_write_u32_array(np, "iommus", prop, ARRAY_SIZE(prop));
}
static void of_fixup_qportals(struct device_node *root, phandle iommu_handle)
--
2.39.2
^ permalink raw reply [flat|nested] 22+ messages in thread* [PATCH v2 09/21] ARM: Layerscape: icid: factor out setup_icid_offsets()
2024-01-09 16:15 [PATCH v2 00/21] Add more Layerscape LS1028a stuff Sascha Hauer
` (7 preceding siblings ...)
2024-01-09 16:15 ` [PATCH v2 08/21] ARM: Layerscape: icid: use of_property_write_u32_array() in of_set_qportal_iommu_prop() Sascha Hauer
@ 2024-01-09 16:15 ` Sascha Hauer
2024-01-09 16:15 ` [PATCH v2 10/21] immap_lsch3: Add more stuff Sascha Hauer
` (11 subsequent siblings)
20 siblings, 0 replies; 22+ messages in thread
From: Sascha Hauer @ 2024-01-09 16:15 UTC (permalink / raw)
To: Barebox List
The code to iterate over the icid table writing register values can be
re-used for upcomin LS1028a support, so move the code to a separate
function.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-layerscape/icid.c | 23 ++++++++++++++++-------
1 file changed, 16 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-layerscape/icid.c b/arch/arm/mach-layerscape/icid.c
index 1055cf59da..3207d55bf0 100644
--- a/arch/arm/mach-layerscape/icid.c
+++ b/arch/arm/mach-layerscape/icid.c
@@ -120,6 +120,20 @@ static int of_fixup_icid(struct device_node *root, phandle iommu_handle,
return 0;
}
+static void setup_icid_offsets(const struct icid_id_table *icid_table, int num_icids, bool le)
+{
+ int i;
+
+ for (i = 0; i < num_icids; i++) {
+ const struct icid_id_table *icid = &icid_table[i];
+
+ if (le)
+ out_le32((u32 *)(icid->reg_addr), icid->reg);
+ else
+ out_be32((u32 *)(icid->reg_addr), icid->reg);
+ }
+}
+
struct fman_icid_id_table {
u32 port_id;
u32 icid;
@@ -549,15 +563,10 @@ static int of_fixup_ls1046a(struct device_node *root, void *context)
void ls1046a_setup_icids(void)
{
- int i;
struct ccsr_fman *fm = (void *)LSCH2_FM1_ADDR;
+ int i;
- /* setup general icid offsets */
- for (i = 0; i < ARRAY_SIZE(icid_tbl_ls1046a); i++) {
- const struct icid_id_table *icid = &icid_tbl_ls1046a[i];
-
- out_be32((u32 *)(icid->reg_addr), icid->reg);
- }
+ setup_icid_offsets(icid_tbl_ls1046a, ARRAY_SIZE(icid_tbl_ls1046a), false);
/* setup fman icids */
for (i = 0; i < ARRAY_SIZE(fman_icid_tbl_ls1046a); i++) {
--
2.39.2
^ permalink raw reply [flat|nested] 22+ messages in thread* [PATCH v2 10/21] immap_lsch3: Add more stuff
2024-01-09 16:15 [PATCH v2 00/21] Add more Layerscape LS1028a stuff Sascha Hauer
` (8 preceding siblings ...)
2024-01-09 16:15 ` [PATCH v2 09/21] ARM: Layerscape: icid: factor out setup_icid_offsets() Sascha Hauer
@ 2024-01-09 16:15 ` Sascha Hauer
2024-01-09 16:15 ` [PATCH v2 11/21] ARM: Layerscape: LS1028a: fixup icids Sascha Hauer
` (10 subsequent siblings)
20 siblings, 0 replies; 22+ messages in thread
From: Sascha Hauer @ 2024-01-09 16:15 UTC (permalink / raw)
To: Barebox List
arch/arm/mach-layerscape/icid.c pokes on several peripheral base
addresses. Let's add some more stuff from the corresponding U-Boot
file for upcoming LS1028a support.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
include/soc/fsl/immap_lsch3.h | 119 ++++++++++++++++++++++++++++++++++
1 file changed, 119 insertions(+)
diff --git a/include/soc/fsl/immap_lsch3.h b/include/soc/fsl/immap_lsch3.h
index f2fdb7dfb3..f25a6e46be 100644
--- a/include/soc/fsl/immap_lsch3.h
+++ b/include/soc/fsl/immap_lsch3.h
@@ -29,8 +29,23 @@
#define LSCH3_IFC_ADDR (LSCH3_IMMR + 0x01240000)
#define LSCH3_NS16550_COM1 (LSCH3_IMMR + 0x011C0500)
#define LSCH3_NS16550_COM2 (LSCH3_IMMR + 0x011C0600)
+#define LSCH3_EDMA_ADDR (LSCH3_IMMR + 0x012c0000)
#define LSCH3_TIMER_ADDR (LSCH3_IMMR + 0x013e0000)
+#define LSCH3_XHCI_USB1_ADDR (LSCH3_IMMR + 0x02100000)
+#define LSCH3_XHCI_USB2_ADDR (LSCH3_IMMR + 0x02110000)
+#define LSCH3_AHCI1_ADDR (LSCH3_IMMR + 0x02200000)
+#define LSCH3_AHCI2_ADDR (LSCH3_IMMR + 0x02210000)
+#define LSCH3_AHCI3_ADDR (LSCH3_IMMR + 0x02220000)
+#define LSCH3_AHCI4_ADDR (LSCH3_IMMR + 0x02230000)
#define LSCH3_CCI400_ADDR (LSCH3_IMMR + 0x03090000)
+#define LSCH3_SEC_ADDR (LSCH3_IMMR + 0x07000000)
+#define LSCH3_SEC_JR0_ADDR (LSCH3_IMMR + 0x07010000)
+#define LSCH3_SEC_JR1_ADDR (LSCH3_IMMR + 0x07020000)
+#define LSCH3_SEC_JR2_ADDR (LSCH3_IMMR + 0x07030000)
+#define LSCH3_SEC_JR3_ADDR (LSCH3_IMMR + 0x07040000)
+#define LSCH3_QDMA_ADDR (LSCH3_IMMR + 0x07380000)
+#define LSCH3_DISPLAY_ADDR (LSCH3_IMMR + 0x0e080000)
+#define LSCH3_GPU_ADDR (LSCH3_IMMR + 0x0e0c0000)
#define LSCH3_PMU_CLTBENR (LSCH3_PMU_ADDR + 0x18A0)
#define LSCH3_PCTBENR_OFFSET (LSCH3_PMU_ADDR + 0x8A0)
#define LSCH3_SVR (LSCH3_GUTS_ADDR + 0xA4)
@@ -183,5 +198,109 @@ struct lsch3_ccsr_gur {
u8 res_858[0x1000-0xc00];
};
+struct rng4tst {
+ u32 rtmctl; /* misc. control register */
+ u32 rtscmisc; /* statistical check misc. register */
+ u32 rtpkrrng; /* poker range register */
+ union {
+ u32 rtpkrmax; /* PRGM=1: poker max. limit register */
+ u32 rtpkrsq; /* PRGM=0: poker square calc. result register */
+ };
+ u32 rtsdctl; /* seed control register */
+ union {
+ u32 rtsblim; /* PRGM=1: sparse bit limit register */
+ u32 rttotsam; /* PRGM=0: total samples register */
+ };
+ u32 rtfreqmin; /* frequency count min. limit register */
+ union {
+ u32 rtfreqmax; /* PRGM=1: freq. count max. limit register */
+ u32 rtfreqcnt; /* PRGM=0: freq. count register */
+ };
+ u32 rsvd1[40];
+ u32 rdsta; /*RNG DRNG Status Register*/
+ u32 rsvd2[15];
+};
+
+struct version_regs {
+ u32 crca; /* CRCA_VERSION */
+ u32 afha; /* AFHA_VERSION */
+ u32 kfha; /* KFHA_VERSION */
+ u32 pkha; /* PKHA_VERSION */
+ u32 aesa; /* AESA_VERSION */
+ u32 mdha; /* MDHA_VERSION */
+ u32 desa; /* DESA_VERSION */
+ u32 snw8a; /* SNW8A_VERSION */
+ u32 snw9a; /* SNW9A_VERSION */
+ u32 zuce; /* ZUCE_VERSION */
+ u32 zuca; /* ZUCA_VERSION */
+ u32 ccha; /* CCHA_VERSION */
+ u32 ptha; /* PTHA_VERSION */
+ u32 rng; /* RNG_VERSION */
+ u32 trng; /* TRNG_VERSION */
+ u32 aaha; /* AAHA_VERSION */
+ u32 rsvd[10];
+ u32 sr; /* SR_VERSION */
+ u32 dma; /* DMA_VERSION */
+ u32 ai; /* AI_VERSION */
+ u32 qi; /* QI_VERSION */
+ u32 jr; /* JR_VERSION */
+ u32 deco; /* DECO_VERSION */
+};
+
+struct ccsr_sec {
+ u32 res0;
+ u32 mcfgr; /* Master CFG Register */
+ u8 res1[0x4];
+ u32 scfgr;
+ struct {
+ u32 ms; /* Job Ring LIODN Register, MS */
+ u32 ls; /* Job Ring LIODN Register, LS */
+ } jrliodnr[4];
+ u8 res2[0x2c];
+ u32 jrstartr; /* Job Ring Start Register */
+ struct {
+ u32 ms; /* RTIC LIODN Register, MS */
+ u32 ls; /* RTIC LIODN Register, LS */
+ } rticliodnr[4];
+ u8 res3[0x1c];
+ u32 decorr; /* DECO Request Register */
+ struct {
+ u32 ms; /* DECO LIODN Register, MS */
+ u32 ls; /* DECO LIODN Register, LS */
+ } decoliodnr[16];
+ u32 dar; /* DECO Avail Register */
+ u32 drr; /* DECO Reset Register */
+ u8 res5[0x4d8];
+ struct rng4tst rng; /* RNG Registers */
+ u8 res6[0x780];
+ struct version_regs vreg; /* version registers since era 10 */
+ u8 res7[0xa0];
+ u32 crnr_ms; /* CHA Revision Number Register, MS */
+ u32 crnr_ls; /* CHA Revision Number Register, LS */
+ u32 ctpr_ms; /* Compile Time Parameters Register, MS */
+ u32 ctpr_ls; /* Compile Time Parameters Register, LS */
+ u8 res8[0x10];
+ u32 far_ms; /* Fault Address Register, MS */
+ u32 far_ls; /* Fault Address Register, LS */
+ u32 falr; /* Fault Address LIODN Register */
+ u32 fadr; /* Fault Address Detail Register */
+ u8 res9[0x4];
+ u32 csta; /* CAAM Status Register */
+ u32 smpart; /* Secure Memory Partition Parameters */
+ u32 smvid; /* Secure Memory Version ID */
+ u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/
+ u32 ccbvid; /* CHA Cluster Block Version ID Register */
+ u32 chavid_ms; /* CHA Version ID Register, MS */
+ u32 chavid_ls; /* CHA Version ID Register, LS */
+ u32 chanum_ms; /* CHA Number Register, MS */
+ u32 chanum_ls; /* CHA Number Register, LS */
+ u32 secvid_ms; /* SEC Version ID Register, MS */
+ u32 secvid_ls; /* SEC Version ID Register, LS */
+ u8 res10[0x6f020];
+ u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */
+ u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */
+ u8 res11[0x8ffd8];
+};
+
#endif /*__ASSEMBLY__ */
#endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */
--
2.39.2
^ permalink raw reply [flat|nested] 22+ messages in thread* [PATCH v2 11/21] ARM: Layerscape: LS1028a: fixup icids
2024-01-09 16:15 [PATCH v2 00/21] Add more Layerscape LS1028a stuff Sascha Hauer
` (9 preceding siblings ...)
2024-01-09 16:15 ` [PATCH v2 10/21] immap_lsch3: Add more stuff Sascha Hauer
@ 2024-01-09 16:15 ` Sascha Hauer
2024-01-09 16:15 ` [PATCH v2 12/21] ARM: psci: make header self contained Sascha Hauer
` (9 subsequent siblings)
20 siblings, 0 replies; 22+ messages in thread
From: Sascha Hauer @ 2024-01-09 16:15 UTC (permalink / raw)
To: Barebox List
The DMA operations from peripherals have a stream id attached to them
which must match the stream ids configured in the IOMMU. Configure the
stream ids in the peripheral registers and fixup the Kernel device tree
with the configured stream ids.
The code is based on the corresponding U-Boot code as of
U-Boot-2023.10-rc1. The result is hard to match against the U-Boot code
though as U-Boot hides the initialisation arrays behind multiply layered
defines which are dropped here to make the code readable.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-layerscape/icid.c | 213 +++++++++++++++++++++++++++
arch/arm/mach-layerscape/soc.c | 1 +
include/mach/layerscape/layerscape.h | 1 +
3 files changed, 215 insertions(+)
diff --git a/arch/arm/mach-layerscape/icid.c b/arch/arm/mach-layerscape/icid.c
index 3207d55bf0..ebe3896075 100644
--- a/arch/arm/mach-layerscape/icid.c
+++ b/arch/arm/mach-layerscape/icid.c
@@ -5,6 +5,7 @@
#include <init.h>
#include <of_address.h>
#include <soc/fsl/immap_lsch2.h>
+#include <soc/fsl/immap_lsch3.h>
#include <soc/fsl/fsl_qbman.h>
#include <soc/fsl/fsl_fman.h>
#include <mach/layerscape/layerscape.h>
@@ -580,3 +581,215 @@ void ls1046a_setup_icids(void)
of_register_fixup(of_fixup_ls1046a, NULL);
}
+
+static const struct icid_id_table icid_tbl_ls1028a[] = {
+ {
+ .compat = "snps,dwc3",
+ .id = 1,
+ .reg = 1,
+ .compat_addr = LSCH3_XHCI_USB1_ADDR,
+ .reg_addr = offsetof(struct lsch3_ccsr_gur, usb1_amqr) + LSCH3_GUTS_ADDR,
+ }, {
+ .compat = "snps,dwc3",
+ .id = 2,
+ .reg = 2,
+ .compat_addr = LSCH3_XHCI_USB2_ADDR,
+ .reg_addr = offsetof(struct lsch3_ccsr_gur, usb2_amqr) + LSCH3_GUTS_ADDR,
+ }, {
+ .compat = "fsl,esdhc",
+ .id = 3,
+ .reg = 3,
+ .compat_addr = LSCH3_ESDHC1_BASE_ADDR,
+ .reg_addr = offsetof(struct lsch3_ccsr_gur, sdmm1_amqr) + LSCH3_GUTS_ADDR,
+ }, {
+ .compat = "fsl,esdhc",
+ .id = 69,
+ .reg = 69,
+ .compat_addr = LSCH3_ESDHC2_BASE_ADDR,
+ .reg_addr = offsetof(struct lsch3_ccsr_gur, sdmm2_amqr) + LSCH3_GUTS_ADDR,
+ }, {
+ .compat = "fsl,ls1028a-ahci",
+ .id = 4,
+ .reg = 4,
+ .compat_addr = LSCH3_AHCI1_ADDR,
+ .reg_addr = offsetof(struct lsch3_ccsr_gur, sata1_amqr) + LSCH3_GUTS_ADDR,
+ }, {
+ .compat = "fsl,vf610-edma",
+ .id = 40,
+ .reg = 40,
+ .compat_addr = LSCH3_EDMA_ADDR,
+ .reg_addr = offsetof(struct lsch3_ccsr_gur, spare3_amqr) + LSCH3_GUTS_ADDR,
+ }, {
+ .compat = "fsl,ls1028a-qdma",
+ .id = 5,
+ .reg = (1 << 31) | 5,
+ .compat_addr = LSCH3_QDMA_ADDR,
+ .reg_addr = LSCH3_QDMA_ADDR + QMAN_CQSIDR_REG,
+ }, {
+ .compat = NULL,
+ .id = 5,
+ .reg = (1 << 31) | 5,
+ .compat_addr = LSCH3_QDMA_ADDR,
+ .reg_addr = LSCH3_QDMA_ADDR + QMAN_CQSIDR_REG + 4,
+ }, {
+ .compat = "vivante,gc",
+ .id = 71,
+ .reg = 71,
+ .compat_addr = LSCH3_GPU_ADDR,
+ .reg_addr = offsetof(struct lsch3_ccsr_gur, misc1_amqr) + LSCH3_GUTS_ADDR,
+ }, {
+ .compat = "arm,mali-dp500",
+ .id = 72,
+ .reg = 72,
+ .compat_addr = LSCH3_DISPLAY_ADDR,
+ .reg_addr = offsetof(struct lsch3_ccsr_gur, spare2_amqr) + LSCH3_GUTS_ADDR,
+ }, {
+ .compat = "fsl,sec-v4.0-job-ring",
+ .id = 65,
+ .reg = 65,
+ .compat_addr = LSCH3_SEC_JR0_ADDR,
+ .reg_addr = offsetof(struct ccsr_sec, jrliodnr[0].ls) + LSCH3_SEC_ADDR,
+ }, {
+ .compat = "fsl,sec-v4.0-job-ring",
+ .id = 66,
+ .reg = 66,
+ .compat_addr = LSCH3_SEC_JR1_ADDR,
+ .reg_addr = offsetof(struct ccsr_sec, jrliodnr[1].ls) + LSCH3_SEC_ADDR,
+ }, {
+ .id = 67,
+ .reg = 67,
+ .compat_addr = LSCH3_SEC_JR2_ADDR,
+ .reg_addr = offsetof(struct ccsr_sec, jrliodnr[2].ls) + LSCH3_SEC_ADDR,
+ }, {
+ .compat = "fsl,sec-v4.0-job-ring",
+ .id = 68,
+ .reg = 68,
+ .compat_addr = LSCH3_SEC_JR3_ADDR,
+ .reg_addr = offsetof(struct ccsr_sec, jrliodnr[3].ls) + LSCH3_SEC_ADDR,
+ }, {
+ .id = 64,
+ .reg = 64,
+ .compat_addr = 0,
+ .reg_addr = offsetof(struct ccsr_sec, rticliodnr[0].ls) + LSCH3_SEC_ADDR,
+ }, {
+ .id = 64,
+ .reg = 64,
+ .compat_addr = 0,
+ .reg_addr = offsetof(struct ccsr_sec, rticliodnr[1].ls) + LSCH3_SEC_ADDR,
+ }, {
+ .id = 64,
+ .reg = 64,
+ .compat_addr = 0,
+ .reg_addr = offsetof(struct ccsr_sec, rticliodnr[2].ls) + LSCH3_SEC_ADDR,
+ }, {
+ .id = 64,
+ .reg = 64,
+ .compat_addr = 0,
+ .reg_addr = offsetof(struct ccsr_sec, rticliodnr[3].ls) + LSCH3_SEC_ADDR,
+ }, {
+ .id = 64,
+ .reg = 64,
+ .compat_addr = 0,
+ .reg_addr = offsetof(struct ccsr_sec, decoliodnr[0].ls) + LSCH3_SEC_ADDR,
+ }, {
+ .id = 64,
+ .reg = 64,
+ .compat_addr = 0,
+ .reg_addr = offsetof(struct ccsr_sec, decoliodnr[1].ls) + LSCH3_SEC_ADDR,
+ }
+};
+
+static int of_fixup_icid_ls1028a(struct device_node *root, void *context)
+{
+ phandle iommu_handle;
+
+ iommu_handle = of_get_iommu_handle(root);
+ if (!iommu_handle)
+ return 0;
+
+ of_fixup_icid(root, iommu_handle, icid_tbl_ls1028a, ARRAY_SIZE(icid_tbl_ls1028a));
+
+ return 0;
+}
+
+/* offset of IERB config register per PCI function */
+static const int ierb_offset[] = {
+ 0x0800,
+ 0x1800,
+ 0x2800,
+ 0x3800,
+ 0x4800,
+ 0x5800,
+ 0x6800,
+ -1,
+ 0x0804,
+ 0x0808,
+ 0x1804,
+ 0x1808,
+};
+
+#define ECAM_IERB_BASE 0x1f0800000ULL
+#define ECAM_IERB_MSICAR (ECAM_IERB_BASE + 0xa400)
+#define ECAM_IERB_MSICAR_VALUE 0x30
+#define FSL_ECAM_STREAM_ID_START 41
+
+/*
+ * Use a custom function for LS1028A, for now this is the only SoC with IERB
+ * and we're currently considering reorganizing IERB for future SoCs.
+ */
+static void ls1028a_set_ecam_icids(void)
+{
+ int i;
+
+ out_le32(ECAM_IERB_MSICAR, ECAM_IERB_MSICAR_VALUE);
+
+ for (i = 0; i < ARRAY_SIZE(ierb_offset); i++) {
+ if (ierb_offset[i] < 0)
+ continue;
+
+ out_le32(ECAM_IERB_BASE + ierb_offset[i],
+ FSL_ECAM_STREAM_ID_START + i);
+ }
+}
+
+static int of_fixup_ecam_ls1028a(struct device_node *root, void *context)
+{
+ struct device_node *np;
+ int i, ret;
+ const char *props[] = { "msi-map", "iommu-map" };
+ uint32_t map[4];
+
+ np = of_find_compatible_node(root, NULL, "pci-host-ecam-generic");
+ if (!np) {
+ pr_info("No \"pci-host-ecam-generic\" node found, won't fixup\n");
+ return 0;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(props); i++) {
+ ret = of_property_read_u32_array(np, props[i], map, 4);
+ if (ret) {
+ pr_err("Cannot read \"%s\" property: %pe", props[i], ERR_PTR(ret));
+ return ret;
+ }
+
+ map[2] = FSL_ECAM_STREAM_ID_START;
+ map[3] = ARRAY_SIZE(ierb_offset);
+ ret = of_property_write_u32_array(np, props[i], map, 4);
+ if (ret) {
+ pr_err("Cannot write \"%s\" property: %pe", props[i], ERR_PTR(ret));
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+void ls1028a_setup_icids(void)
+{
+ setup_icid_offsets(icid_tbl_ls1028a, ARRAY_SIZE(icid_tbl_ls1028a), true);
+
+ ls1028a_set_ecam_icids();
+
+ of_register_fixup(of_fixup_icid_ls1028a, NULL);
+ of_register_fixup(of_fixup_ecam_ls1028a, NULL);
+}
diff --git a/arch/arm/mach-layerscape/soc.c b/arch/arm/mach-layerscape/soc.c
index 8507a66ff6..a50aafc954 100644
--- a/arch/arm/mach-layerscape/soc.c
+++ b/arch/arm/mach-layerscape/soc.c
@@ -93,6 +93,7 @@ static int ls1028a_init(void)
return -EINVAL;
layerscape_register_pbl_image_handler();
+ ls1028a_setup_icids();
return 0;
}
diff --git a/include/mach/layerscape/layerscape.h b/include/mach/layerscape/layerscape.h
index 3dacfcb29f..a9037125c8 100644
--- a/include/mach/layerscape/layerscape.h
+++ b/include/mach/layerscape/layerscape.h
@@ -58,6 +58,7 @@ void ls1046a_bootsource_init(void);
void layerscape_register_pbl_image_handler(void);
void ls102xa_smmu_stream_id_init(void);
void ls1021a_restart_register_feature(void);
+void ls1028a_setup_icids(void);
void ls1046a_setup_icids(void);
extern int __layerscape_soc_type;
--
2.39.2
^ permalink raw reply [flat|nested] 22+ messages in thread* [PATCH v2 12/21] ARM: psci: make header self contained
2024-01-09 16:15 [PATCH v2 00/21] Add more Layerscape LS1028a stuff Sascha Hauer
` (10 preceding siblings ...)
2024-01-09 16:15 ` [PATCH v2 11/21] ARM: Layerscape: LS1028a: fixup icids Sascha Hauer
@ 2024-01-09 16:15 ` Sascha Hauer
2024-01-09 16:15 ` [PATCH v2 13/21] ARM: Layerscape: LS1028a: add psci node Sascha Hauer
` (8 subsequent siblings)
20 siblings, 0 replies; 22+ messages in thread
From: Sascha Hauer @ 2024-01-09 16:15 UTC (permalink / raw)
To: Barebox List
arch/arm/include/asm/psci.h uses struct device_node, so declare it
in order to make the file self contained.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/include/asm/psci.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index dbb9adfc3e..b342eb85f5 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -6,6 +6,8 @@
#ifndef __ARM_PSCI_H__
#define __ARM_PSCI_H__
+struct device_node;
+
#define ARM_PSCI_VER(major, minor) (((major) << 16) | (minor))
#define ARM_PSCI_VER_1_0 ARM_PSCI_VER(1,0)
#define ARM_PSCI_VER_0_2 ARM_PSCI_VER(0,2)
--
2.39.2
^ permalink raw reply [flat|nested] 22+ messages in thread* [PATCH v2 13/21] ARM: Layerscape: LS1028a: add psci node
2024-01-09 16:15 [PATCH v2 00/21] Add more Layerscape LS1028a stuff Sascha Hauer
` (11 preceding siblings ...)
2024-01-09 16:15 ` [PATCH v2 12/21] ARM: psci: make header self contained Sascha Hauer
@ 2024-01-09 16:15 ` Sascha Hauer
2024-01-09 16:15 ` [PATCH v2 14/21] ARM: Layerscape: move over to MULTIARCH Sascha Hauer
` (7 subsequent siblings)
20 siblings, 0 replies; 22+ messages in thread
From: Sascha Hauer @ 2024-01-09 16:15 UTC (permalink / raw)
To: Barebox List
The upstream dts files do not contain a psci node. Add one in order
to use PSCI to reset the system. This will also add a PSCI node to the
dtb the kernel is started with so that the Kernel can use PSCI to bring
up the secondary CPU core.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/configs/layerscape_defconfig | 1 +
arch/arm/dts/fsl-ls1028a.dtsi | 7 +++++++
2 files changed, 8 insertions(+)
create mode 100644 arch/arm/dts/fsl-ls1028a.dtsi
diff --git a/arch/arm/configs/layerscape_defconfig b/arch/arm/configs/layerscape_defconfig
index 35b254f139..5a5ea784e1 100644
--- a/arch/arm/configs/layerscape_defconfig
+++ b/arch/arm/configs/layerscape_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_LAYERSCAPE_PPA=y
CONFIG_MACH_LS1046ARDB=y
CONFIG_MACH_TQMLS1046A=y
CONFIG_64BIT=y
+CONFIG_ARM_PSCI_CLIENT=y
CONFIG_MMU=y
CONFIG_MALLOC_SIZE=0x0
CONFIG_MALLOC_TLSF=y
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
new file mode 100644
index 0000000000..a15a219cfa
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -0,0 +1,7 @@
+
+/ {
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+};
--
2.39.2
^ permalink raw reply [flat|nested] 22+ messages in thread* [PATCH v2 14/21] ARM: Layerscape: move over to MULTIARCH
2024-01-09 16:15 [PATCH v2 00/21] Add more Layerscape LS1028a stuff Sascha Hauer
` (12 preceding siblings ...)
2024-01-09 16:15 ` [PATCH v2 13/21] ARM: Layerscape: LS1028a: add psci node Sascha Hauer
@ 2024-01-09 16:15 ` Sascha Hauer
2024-01-09 16:15 ` [PATCH v2 15/21] ARM: enable Layerscape boards in multi_v8_defconfig Sascha Hauer
` (6 subsequent siblings)
20 siblings, 0 replies; 22+ messages in thread
From: Sascha Hauer @ 2024-01-09 16:15 UTC (permalink / raw)
To: Barebox List
Layerscape doesn't contain any unprotected initcalls anymore, so we can
safely move it over to MULTIARCH.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/Kconfig | 27 ++++++++++++++-------------
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ee3914620e..0557567a59 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -90,19 +90,6 @@ config ARCH_EP93XX
select CPU_ARM920T
select GENERIC_GPIO
-config ARCH_LAYERSCAPE
- bool "NXP Layerscape based"
- select GPIOLIB
- select HAS_DEBUG_LL
- select HAVE_PBL_MULTI_IMAGES
- select COMMON_CLK
- select CLKDEV_LOOKUP
- select COMMON_CLK_OF_PROVIDER
- select HW_HAS_PCI
- select OFTREE
- select OFDEVICE
- select ARM_USE_COMPRESSED_DTB
-
config ARCH_MVEBU
bool "Marvell EBU platforms"
depends on 32BIT
@@ -246,6 +233,20 @@ config ARCH_K3
select COMMON_CLK_OF_PROVIDER
select PM_GENERIC_DOMAINS
+config ARCH_LAYERSCAPE
+ bool "NXP Layerscape based"
+ depends on ARCH_MULTIARCH
+ select GPIOLIB
+ select HAS_DEBUG_LL
+ select HAVE_PBL_MULTI_IMAGES
+ select COMMON_CLK
+ select CLKDEV_LOOKUP
+ select COMMON_CLK_OF_PROVIDER
+ select HW_HAS_PCI
+ select OFTREE
+ select OFDEVICE
+ select ARM_USE_COMPRESSED_DTB
+
config ARCH_OMAP_MULTI
bool "TI OMAP"
depends on 32BIT
--
2.39.2
^ permalink raw reply [flat|nested] 22+ messages in thread* [PATCH v2 15/21] ARM: enable Layerscape boards in multi_v8_defconfig
2024-01-09 16:15 [PATCH v2 00/21] Add more Layerscape LS1028a stuff Sascha Hauer
` (13 preceding siblings ...)
2024-01-09 16:15 ` [PATCH v2 14/21] ARM: Layerscape: move over to MULTIARCH Sascha Hauer
@ 2024-01-09 16:15 ` Sascha Hauer
2024-01-09 16:15 ` [PATCH v2 16/21] ARM: multi_v8_defconfig: disable CONFIG_MCI_STARTUP Sascha Hauer
` (5 subsequent siblings)
20 siblings, 0 replies; 22+ messages in thread
From: Sascha Hauer @ 2024-01-09 16:15 UTC (permalink / raw)
To: Barebox List
Now that Layerscape can do MULTIARCH enable the Layerscape boards
in multi_v8_defconfig.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/configs/multi_v8_defconfig | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm/configs/multi_v8_defconfig b/arch/arm/configs/multi_v8_defconfig
index 1851735eec..35fceabfd4 100644
--- a/arch/arm/configs/multi_v8_defconfig
+++ b/arch/arm/configs/multi_v8_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARCH_ARM64_VIRT=y
CONFIG_ARCH_IMX=y
CONFIG_ARCH_K3=y
+CONFIG_ARCH_LAYERSCAPE=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_ARCH_ZYNQMP=y
CONFIG_MACH_INNOCOMM_WB15=y
@@ -19,6 +20,10 @@ CONFIG_MACH_VARISCITE_DT8MCUSTOMBOARD_IMX8MP=y
CONFIG_MACH_ZII_IMX8MQ_DEV=y
CONFIG_MACH_TQ_MBA9XXXCA=y
CONFIG_IMX_IIM=y
+CONFIG_ARCH_LAYERSCAPE_PPA=y
+CONFIG_MACH_LS1028ARDB=y
+CONFIG_MACH_LS1046ARDB=y
+CONFIG_MACH_TQMLS1046A=y
CONFIG_MACH_BEAGLEPLAY=y
CONFIG_MACH_RK3568_EVB=y
CONFIG_MACH_RK3568_BPI_R2PRO=y
@@ -149,6 +154,8 @@ CONFIG_VIRTIO_CONSOLE=y
CONFIG_DRIVER_NET_DESIGNWARE_IMX8=y
CONFIG_DRIVER_NET_DESIGNWARE_ROCKCHIP=y
CONFIG_DRIVER_NET_FEC_IMX=y
+CONFIG_DRIVER_NET_FSL_ENETC=y
+CONFIG_DRIVER_NET_FSL_FMAN=y
CONFIG_DRIVER_NET_MACB=y
CONFIG_DRIVER_NET_VIRTIO=y
CONFIG_DP83867_PHY=y
@@ -164,6 +171,7 @@ CONFIG_NET_USB_ASIX=y
CONFIG_USB_NET_AX88179_178A=y
CONFIG_NET_USB_SMSC95XX=y
CONFIG_NET_USB_RTL8152=y
+CONFIG_DRIVER_SPI_FSL_QUADSPI=y
CONFIG_DRIVER_SPI_IMX=y
CONFIG_SPI_NXP_FLEXSPI=y
CONFIG_I2C=y
@@ -171,6 +179,8 @@ CONFIG_I2C_GPIO=y
CONFIG_I2C_IMX=y
CONFIG_I2C_IMX_LPI2C=y
CONFIG_I2C_RK3X=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
CONFIG_MTD=y
CONFIG_MTD_CONCAT=y
CONFIG_MTD_M25P80=y
@@ -208,6 +218,8 @@ CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_LED_GPIO_OF=y
CONFIG_LED_TRIGGERS=y
+CONFIG_LED_PCA955X=y
+CONFIG_EEPROM_AT25=y
CONFIG_EEPROM_AT24=y
CONFIG_VIRTIO_INPUT=y
CONFIG_WATCHDOG=y
@@ -228,6 +240,7 @@ CONFIG_REGULATOR_FIXED=y
CONFIG_REGULATOR_ARM_SCMI=y
CONFIG_REGULATOR_RK808=y
CONFIG_RESET_IMX7=y
+CONFIG_PCI_LAYERSCAPE=y
CONFIG_PCI_ECAM_GENERIC=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_DS1307=y
--
2.39.2
^ permalink raw reply [flat|nested] 22+ messages in thread* [PATCH v2 16/21] ARM: multi_v8_defconfig: disable CONFIG_MCI_STARTUP
2024-01-09 16:15 [PATCH v2 00/21] Add more Layerscape LS1028a stuff Sascha Hauer
` (14 preceding siblings ...)
2024-01-09 16:15 ` [PATCH v2 15/21] ARM: enable Layerscape boards in multi_v8_defconfig Sascha Hauer
@ 2024-01-09 16:15 ` Sascha Hauer
2024-01-09 16:15 ` [PATCH v2 17/21] clk: layerscape: increase PLL divider array Sascha Hauer
` (4 subsequent siblings)
20 siblings, 0 replies; 22+ messages in thread
From: Sascha Hauer @ 2024-01-09 16:15 UTC (permalink / raw)
To: Barebox List
SD/eMMC cards are detected automatically when needed for environment
or barebox_update, so do not probe them during registration.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/configs/multi_v8_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/configs/multi_v8_defconfig b/arch/arm/configs/multi_v8_defconfig
index 35fceabfd4..677395b1f9 100644
--- a/arch/arm/configs/multi_v8_defconfig
+++ b/arch/arm/configs/multi_v8_defconfig
@@ -203,7 +203,6 @@ CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_DRIVER_VIDEO_BOCHS_PCI=y
CONFIG_SOUND=y
CONFIG_MCI=y
-CONFIG_MCI_STARTUP=y
CONFIG_MCI_MMC_BOOT_PARTITIONS=y
CONFIG_MCI_DW=y
CONFIG_MCI_ROCKCHIP_DWCMSHC=y
--
2.39.2
^ permalink raw reply [flat|nested] 22+ messages in thread* [PATCH v2 17/21] clk: layerscape: increase PLL divider array
2024-01-09 16:15 [PATCH v2 00/21] Add more Layerscape LS1028a stuff Sascha Hauer
` (15 preceding siblings ...)
2024-01-09 16:15 ` [PATCH v2 16/21] ARM: multi_v8_defconfig: disable CONFIG_MCI_STARTUP Sascha Hauer
@ 2024-01-09 16:15 ` Sascha Hauer
2024-01-09 16:15 ` [PATCH v2 18/21] ARM: Layerscape: LS1028a: implement bootsource detection Sascha Hauer
` (3 subsequent siblings)
20 siblings, 0 replies; 22+ messages in thread
From: Sascha Hauer @ 2024-01-09 16:15 UTC (permalink / raw)
To: Barebox List
Newer Layerscape SoCs like the LS1028a have more PLL dividers,
increase the divider array to accomodate this.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/clk/clk-qoric.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-qoric.c b/drivers/clk/clk-qoric.c
index 6c69b5b3f3..44155692a8 100644
--- a/drivers/clk/clk-qoric.c
+++ b/drivers/clk/clk-qoric.c
@@ -27,6 +27,7 @@
#define CGA_PLL4 4 /* only on clockgen-1.0, which lacks CGB */
#define CGB_PLL1 4
#define CGB_PLL2 5
+#define MAX_PLL_DIV 32
struct clockgen_pll_div {
struct clk_hw *hw;
@@ -34,7 +35,7 @@ struct clockgen_pll_div {
};
struct clockgen_pll {
- struct clockgen_pll_div div[8];
+ struct clockgen_pll_div div[MAX_PLL_DIV];
};
#define CLKSEL_VALID 1
--
2.39.2
^ permalink raw reply [flat|nested] 22+ messages in thread* [PATCH v2 18/21] ARM: Layerscape: LS1028a: implement bootsource detection
2024-01-09 16:15 [PATCH v2 00/21] Add more Layerscape LS1028a stuff Sascha Hauer
` (16 preceding siblings ...)
2024-01-09 16:15 ` [PATCH v2 17/21] clk: layerscape: increase PLL divider array Sascha Hauer
@ 2024-01-09 16:15 ` Sascha Hauer
2024-01-09 16:15 ` [PATCH v2 19/21] ARM: Layerscape: LS1028a: extend layerscape image filetype detection for LS1028a Sascha Hauer
` (2 subsequent siblings)
20 siblings, 0 replies; 22+ messages in thread
From: Sascha Hauer @ 2024-01-09 16:15 UTC (permalink / raw)
To: Barebox List
Detecting the bootsource is just a matter of decoding the porsr1
register. Implement it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-layerscape/boot.c | 40 ++++++++++++++++++++++++++++
arch/arm/mach-layerscape/soc.c | 1 +
include/mach/layerscape/layerscape.h | 1 +
3 files changed, 42 insertions(+)
diff --git a/arch/arm/mach-layerscape/boot.c b/arch/arm/mach-layerscape/boot.c
index 26a7a1434a..4d074205cc 100644
--- a/arch/arm/mach-layerscape/boot.c
+++ b/arch/arm/mach-layerscape/boot.c
@@ -3,8 +3,10 @@
#include <common.h>
#include <init.h>
#include <bootsource.h>
+#include <linux/bitfield.h>
#include <mach/layerscape/layerscape.h>
#include <soc/fsl/immap_lsch2.h>
+#include <soc/fsl/immap_lsch3.h>
enum bootsource ls1046a_bootsource_get(void)
{
@@ -41,3 +43,41 @@ void ls1046a_bootsource_init(void)
{
bootsource_set_raw(ls1046a_bootsource_get(), BOOTSOURCE_INSTANCE_UNKNOWN);
}
+
+#define PORSR1_RCW_SRC GENMASK(26, 23)
+
+static enum bootsource ls1028a_bootsource_get(int *instance)
+{
+ void __iomem *porsr1 = IOMEM(LSCH3_DCFG_BASE);
+ uint32_t rcw_src;
+
+ rcw_src = FIELD_GET(PORSR1_RCW_SRC, readl(porsr1));
+
+ printf("%s: 0x%08x\n", __func__, rcw_src);
+
+ switch (rcw_src) {
+ case 8:
+ *instance = 0;
+ return BOOTSOURCE_MMC;
+ case 9:
+ *instance = 1;
+ return BOOTSOURCE_MMC;
+ case 0xa:
+ return BOOTSOURCE_I2C;
+ case 0xd:
+ case 0xc:
+ return BOOTSOURCE_NAND;
+ case 0xf:
+ return BOOTSOURCE_SPI_NOR;
+ }
+
+ return BOOTSOURCE_UNKNOWN;
+}
+
+void ls1028a_bootsource_init(void)
+{
+ int instance = BOOTSOURCE_INSTANCE_UNKNOWN;
+ enum bootsource source = ls1028a_bootsource_get(&instance);
+
+ bootsource_set_raw(source, instance);
+}
diff --git a/arch/arm/mach-layerscape/soc.c b/arch/arm/mach-layerscape/soc.c
index a50aafc954..462405ea87 100644
--- a/arch/arm/mach-layerscape/soc.c
+++ b/arch/arm/mach-layerscape/soc.c
@@ -92,6 +92,7 @@ static int ls1028a_init(void)
if (!cpu_is_ls1028a())
return -EINVAL;
+ ls1028a_bootsource_init();
layerscape_register_pbl_image_handler();
ls1028a_setup_icids();
diff --git a/include/mach/layerscape/layerscape.h b/include/mach/layerscape/layerscape.h
index a9037125c8..bf4a751b92 100644
--- a/include/mach/layerscape/layerscape.h
+++ b/include/mach/layerscape/layerscape.h
@@ -54,6 +54,7 @@ struct dram_regions_info {
};
void ls1021a_bootsource_init(void);
+void ls1028a_bootsource_init(void);
void ls1046a_bootsource_init(void);
void layerscape_register_pbl_image_handler(void);
void ls102xa_smmu_stream_id_init(void);
--
2.39.2
^ permalink raw reply [flat|nested] 22+ messages in thread* [PATCH v2 19/21] ARM: Layerscape: LS1028a: extend layerscape image filetype detection for LS1028a
2024-01-09 16:15 [PATCH v2 00/21] Add more Layerscape LS1028a stuff Sascha Hauer
` (17 preceding siblings ...)
2024-01-09 16:15 ` [PATCH v2 18/21] ARM: Layerscape: LS1028a: implement bootsource detection Sascha Hauer
@ 2024-01-09 16:15 ` Sascha Hauer
2024-01-09 16:15 ` [PATCH v2 20/21] ARM: Layerscape: LS1028a: Add barebox update handler Sascha Hauer
2024-01-09 16:15 ` [PATCH v2 21/21] ARM: Layerscape: add basic support for NXP LS1028a RDB Sascha Hauer
20 siblings, 0 replies; 22+ messages in thread
From: Sascha Hauer @ 2024-01-09 16:15 UTC (permalink / raw)
To: Barebox List
The LS1028a images differ slightly from LS1046a images, extend its
filetype detection accordingly.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
common/filetype.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/common/filetype.c b/common/filetype.c
index 43d292c27b..14948db446 100644
--- a/common/filetype.c
+++ b/common/filetype.c
@@ -349,6 +349,8 @@ enum filetype file_detect_type(const void *_buf, size_t bufsize)
return filetype_layerscape_image;
if (buf[0] == 0x01ee0100 && buf[1] == 0xaa55aa55)
return filetype_layerscape_qspi_image;
+ if (buf[0] == 0xaa55aa55 && buf[1] == 0x80100000)
+ return filetype_layerscape_image;
if (le32_to_cpu(buf[0]) == 0x00112233 && le32_to_cpu(buf[1]) == 0x1)
return filetype_mxs_sd_image;
--
2.39.2
^ permalink raw reply [flat|nested] 22+ messages in thread* [PATCH v2 20/21] ARM: Layerscape: LS1028a: Add barebox update handler
2024-01-09 16:15 [PATCH v2 00/21] Add more Layerscape LS1028a stuff Sascha Hauer
` (18 preceding siblings ...)
2024-01-09 16:15 ` [PATCH v2 19/21] ARM: Layerscape: LS1028a: extend layerscape image filetype detection for LS1028a Sascha Hauer
@ 2024-01-09 16:15 ` Sascha Hauer
2024-01-09 16:15 ` [PATCH v2 21/21] ARM: Layerscape: add basic support for NXP LS1028a RDB Sascha Hauer
20 siblings, 0 replies; 22+ messages in thread
From: Sascha Hauer @ 2024-01-09 16:15 UTC (permalink / raw)
To: Barebox List
The LS1028a image can be written straight to SD/eMMC at offset 0x100.
Add a barebox update handler for it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
include/mach/layerscape/bbu.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/include/mach/layerscape/bbu.h b/include/mach/layerscape/bbu.h
index d018ec9a9d..186185699b 100644
--- a/include/mach/layerscape/bbu.h
+++ b/include/mach/layerscape/bbu.h
@@ -5,6 +5,14 @@
#include <bbu.h>
+static inline int ls1028a_bbu_mmc_register_handler(const char *name,
+ const char *devicefile,
+ unsigned long flags)
+{
+ return bbu_register_std_file_update(name, flags, devicefile,
+ filetype_layerscape_image);
+}
+
static inline int ls1046a_bbu_mmc_register_handler(const char *name,
const char *devicefile,
unsigned long flags)
--
2.39.2
^ permalink raw reply [flat|nested] 22+ messages in thread* [PATCH v2 21/21] ARM: Layerscape: add basic support for NXP LS1028a RDB
2024-01-09 16:15 [PATCH v2 00/21] Add more Layerscape LS1028a stuff Sascha Hauer
` (19 preceding siblings ...)
2024-01-09 16:15 ` [PATCH v2 20/21] ARM: Layerscape: LS1028a: Add barebox update handler Sascha Hauer
@ 2024-01-09 16:15 ` Sascha Hauer
20 siblings, 0 replies; 22+ messages in thread
From: Sascha Hauer @ 2024-01-09 16:15 UTC (permalink / raw)
To: Barebox List; +Cc: Uwe Kleine-König
From: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
The NXP LS1028a RDB is a LS1028a Eval board. Currently supported are
SD/MMC, ethernet and SD image generation.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/Makefile | 1 +
arch/arm/boards/ls1028ardb/Makefile | 5 +
arch/arm/boards/ls1028ardb/board.c | 45 ++++++
arch/arm/boards/ls1028ardb/lowlevel.c | 142 ++++++++++++++++++
arch/arm/boards/ls1028ardb/ls1028ardb_pbi.cfg | 14 ++
.../boards/ls1028ardb/ls1028ardb_rcw_sd.cfg | 14 ++
arch/arm/boards/ls1028ardb/start.S | 19 +++
arch/arm/configs/layerscape_defconfig | 5 +-
arch/arm/dts/Makefile | 1 +
arch/arm/dts/fsl-ls1028a-rdb.dts | 59 ++++++++
arch/arm/mach-layerscape/Kconfig | 15 +-
images/Makefile.layerscape | 9 ++
12 files changed, 326 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/boards/ls1028ardb/Makefile
create mode 100644 arch/arm/boards/ls1028ardb/board.c
create mode 100644 arch/arm/boards/ls1028ardb/lowlevel.c
create mode 100644 arch/arm/boards/ls1028ardb/ls1028ardb_pbi.cfg
create mode 100644 arch/arm/boards/ls1028ardb/ls1028ardb_rcw_sd.cfg
create mode 100644 arch/arm/boards/ls1028ardb/start.S
create mode 100644 arch/arm/dts/fsl-ls1028a-rdb.dts
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index d27252c4a7..875d011573 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -187,6 +187,7 @@ obj-$(CONFIG_MACH_ZII_IMX8MQ_DEV) += zii-imx8mq-dev/
obj-$(CONFIG_MACH_ZII_VF610_DEV) += zii-vf610-dev/
obj-$(CONFIG_MACH_ZII_IMX7D_DEV) += zii-imx7d-dev/
obj-$(CONFIG_MACH_WAGO_PFC_AM35XX) += wago-pfc-am35xx/
+obj-$(CONFIG_MACH_LS1028ARDB) += ls1028ardb/
obj-$(CONFIG_MACH_LS1046ARDB) += ls1046ardb/
obj-$(CONFIG_MACH_TQMLS1046A) += tqmls1046a/
obj-$(CONFIG_MACH_LS1021AIOT) += ls1021aiot/
diff --git a/arch/arm/boards/ls1028ardb/Makefile b/arch/arm/boards/ls1028ardb/Makefile
new file mode 100644
index 0000000000..df60a21844
--- /dev/null
+++ b/arch/arm/boards/ls1028ardb/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+lwl-y += lowlevel.o
+lwl-y += start.o
+obj-y += board.o
diff --git a/arch/arm/boards/ls1028ardb/board.c b/arch/arm/boards/ls1028ardb/board.c
new file mode 100644
index 0000000000..094d72e6fc
--- /dev/null
+++ b/arch/arm/boards/ls1028ardb/board.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <deep-probe.h>
+#include <bootsource.h>
+#include <driver.h>
+#include <init.h>
+#include <of.h>
+#include <asm/memory.h>
+#include <mach/layerscape/layerscape.h>
+#include <mach/layerscape/bbu.h>
+#include <linux/sizes.h>
+
+static int ls1028ardb_probe(struct device *dev)
+{
+ unsigned long sd_bbu_flags = 0;
+ unsigned long emmc_bbu_flags = 0;
+
+ arm_add_mem_device("ram1", LS1028A_DDR_SDRAM_HIGHMEM_BASE, SZ_2G);
+
+ if (bootsource_get() == BOOTSOURCE_MMC && bootsource_get_instance() == 0) {
+ sd_bbu_flags = BBU_HANDLER_FLAG_DEFAULT;
+ of_device_enable_path("/chosen/environment-sd");
+ } else {
+ emmc_bbu_flags = BBU_HANDLER_FLAG_DEFAULT;
+ of_device_enable_path("/chosen/environment-emmc");
+ }
+
+ ls1028a_bbu_mmc_register_handler("sd", "/dev/mmc0.barebox", sd_bbu_flags);
+ ls1028a_bbu_mmc_register_handler("emmc", "/dev/mmc1.barebox", emmc_bbu_flags);
+
+ return 0;
+}
+
+static const struct of_device_id ls1028a_of_match[] = {
+ { .compatible = "fsl,ls1028a-rdb" },
+ { /* sentinel */ },
+};
+BAREBOX_DEEP_PROBE_ENABLE(ls1028a_of_match);
+
+static struct driver ls1028ardb_board_driver = {
+ .name = "ls1028a-rdb",
+ .probe = ls1028ardb_probe,
+ .of_compatible = ls1028a_of_match,
+};
+device_platform_driver(ls1028ardb_board_driver);
diff --git a/arch/arm/boards/ls1028ardb/lowlevel.c b/arch/arm/boards/ls1028ardb/lowlevel.c
new file mode 100644
index 0000000000..00db0b1cf8
--- /dev/null
+++ b/arch/arm/boards/ls1028ardb/lowlevel.c
@@ -0,0 +1,142 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <debug_ll.h>
+#include <ddr_spd.h>
+#include <image-metadata.h>
+#include <platform_data/mmc-esdhc-imx.h>
+#include <soc/fsl/fsl_ddr_sdram.h>
+#include <soc/fsl/immap_lsch2.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+#include <asm/syscounter.h>
+#include <asm/cache.h>
+#include <mach/layerscape/lowlevel.h>
+#include <mach/layerscape/xload.h>
+#include <mach/layerscape/errata.h>
+#include <mach/layerscape/layerscape.h>
+#include <linux/bitfield.h>
+
+static struct fsl_ddr_controller ddrc = {
+ .memctl_opts.ddrtype = SDRAM_TYPE_DDR4,
+ .base = IOMEM(LSCH2_DDR_ADDR),
+ .ddr_freq = 1600000000,
+ .erratum_A009942 = 1,
+ .erratum_A009663 = 1,
+ .chip_selects_per_ctrl = 4,
+ .fsl_ddr_config_reg = {
+ .cs[0].bnds = 0x000000ff,
+ .cs[0].config = 0x80040422,
+ .cs[0].config_2 = 0,
+ .cs[1].bnds = 0,
+ .cs[1].config = 0,
+ .cs[1].config_2 = 0,
+
+ .timing_cfg_3 = 0x01111000,
+ .timing_cfg_0 = 0xd0550018,
+ .timing_cfg_1 = 0xFAFC0C42,
+ .timing_cfg_2 = 0x0048c114,
+ .ddr_sdram_cfg = 0xe50c000c,
+ .ddr_sdram_cfg_2 = 0x00401110,
+ .ddr_sdram_mode = 0x01010230,
+ .ddr_sdram_mode_2 = 0x0,
+
+ .ddr_sdram_md_cntl = 0x0600001f,
+ .ddr_sdram_interval = 0x18600618,
+ .ddr_data_init = 0xdeadbeef,
+
+ .ddr_sdram_clk_cntl = 0x02000000,
+ .ddr_init_addr = 0,
+ .ddr_init_ext_addr = 0,
+
+ .timing_cfg_4 = 0x00000002,
+ .timing_cfg_5 = 0x07401400,
+ .timing_cfg_6 = 0x0,
+ .timing_cfg_7 = 0x23300000,
+
+ .ddr_zq_cntl = 0x8A090705,
+ .ddr_wrlvl_cntl = 0x86550607,
+ .ddr_sr_cntr = 0,
+ .ddr_sdram_rcw_1 = 0,
+ .ddr_sdram_rcw_2 = 0,
+ .ddr_wrlvl_cntl_2 = 0x0708080A,
+ .ddr_wrlvl_cntl_3 = 0x0A0B0C09,
+
+ .ddr_sdram_mode_9 = 0x00000400,
+ .ddr_sdram_mode_10 = 0x04000000,
+
+ .timing_cfg_8 = 0x06115600,
+
+ .dq_map_0 = 0x5b65b658,
+ .dq_map_1 = 0xd96d8000,
+ .dq_map_2 = 0,
+ .dq_map_3 = 0x01600000,
+
+ .ddr_cdr1 = 0x80040000,
+ .ddr_cdr2 = 0x000000C1
+ },
+};
+
+extern char __dtb_z_fsl_ls1028a_rdb_start[];
+
+#define MEM_PLL_RAT GENMASK(15, 10)
+
+static unsigned long get_ddr_freq(void)
+{
+ unsigned long freq = 100000000;
+ u32 rcwsr1 = readl(0x1e00100);
+ u32 mult;
+
+ mult = FIELD_GET(MEM_PLL_RAT, rcwsr1);
+
+ return freq * mult;
+}
+
+struct dram_regions_info dram_info = {
+ .num_dram_regions = 2,
+ .total_dram_size = SZ_4G,
+ .region = {
+ {
+ .addr = LS1028A_DDR_SDRAM_BASE,
+ .size = SZ_2G,
+ }, {
+ .addr = LS1028A_DDR_SDRAM_HIGHMEM_BASE,
+ .size = SZ_2G,
+ },
+ },
+};
+
+static noinline __noreturn void ls1028ardb_r_entry(unsigned long memsize)
+{
+ unsigned long membase = LS1028A_DDR_SDRAM_BASE;
+
+ if (get_pc() >= membase)
+ barebox_arm_entry(membase, SZ_2G - LS1028A_TFA_RESERVED_SIZE,
+ __dtb_z_fsl_ls1028a_rdb_start);
+
+ arm_cpu_lowlevel_init();
+ ls1028a_init_lowlevel();
+ ddrc.ddr_freq = get_ddr_freq();
+
+ fsl_ddr_set_memctl_regs(&ddrc, 0, true);
+
+ ls1028a_tzc400_init(SZ_4G);
+
+ ls1028a_errata_post_ddr();
+
+ ls1028a_esdhc1_start_image(&dram_info);
+
+ hang();
+}
+
+void ls1028ardb_entry(unsigned long r0, unsigned long r1, unsigned long r2);
+
+__noreturn void ls1028ardb_entry(unsigned long r0, unsigned long r1, unsigned long r2)
+{
+ ls1028a_uart_setup(IOMEM(LSCH2_NS16550_COM1));
+
+ relocate_to_current_adr();
+ setup_c();
+
+ ls1028ardb_r_entry(r0);
+}
diff --git a/arch/arm/boards/ls1028ardb/ls1028ardb_pbi.cfg b/arch/arm/boards/ls1028ardb/ls1028ardb_pbi.cfg
new file mode 100644
index 0000000000..53cfb20327
--- /dev/null
+++ b/arch/arm/boards/ls1028ardb/ls1028ardb_pbi.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+31e00400 18010000
+31e00404 00000000
+33400890 00800401
+33500890 00800401
+334008bc 00000001
+33400154 47474747
+33400158 47474747
+335008bc 00000001
+33500154 47474747
+33500158 47474747
+334008bc 00000000
+335008bc 00000000
diff --git a/arch/arm/boards/ls1028ardb/ls1028ardb_rcw_sd.cfg b/arch/arm/boards/ls1028ardb/ls1028ardb_rcw_sd.cfg
new file mode 100644
index 0000000000..2183991112
--- /dev/null
+++ b/arch/arm/boards/ls1028ardb/ls1028ardb_rcw_sd.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+#PBL preamble and RCW header
+aa55aa55 80100000
+# RCW
+34004010 00000030 00000000 00000000
+00000000 00bf0000 0030c000 00000000
+01e03150 00002580 00000000 00003496
+00000000 00000010 00000000 00000000
+00000000 00000000 00000000 00000000
+00000000 00000000 00000000 00000000
+00000000 00000000 200e705a 00000000
+bb580000 00000000 00000000 00000000
+
diff --git a/arch/arm/boards/ls1028ardb/start.S b/arch/arm/boards/ls1028ardb/start.S
new file mode 100644
index 0000000000..fd410b744a
--- /dev/null
+++ b/arch/arm/boards/ls1028ardb/start.S
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#include <linux/linkage.h>
+#include <asm/barebox-arm64.h>
+#include <asm/assembler64.h>
+
+#define STACK_TOP 0x18040000
+
+ENTRY_PROC(start_ls1028ardb)
+ switch_el x3, 3f, 2f, 1f
+3:
+ mov x3, #STACK_TOP
+ mov sp, x3
+ b ls1028ardb_entry
+2:
+1:
+ mov x3, 0x90000000
+ mov sp, x3
+ b ls1028ardb_entry
+ENTRY_PROC_END(start_ls1028ardb)
diff --git a/arch/arm/configs/layerscape_defconfig b/arch/arm/configs/layerscape_defconfig
index 5a5ea784e1..8103da3226 100644
--- a/arch/arm/configs/layerscape_defconfig
+++ b/arch/arm/configs/layerscape_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARCH_LAYERSCAPE=y
CONFIG_ARCH_LAYERSCAPE_PPA=y
+CONFIG_MACH_LS1028ARDB=y
CONFIG_MACH_LS1046ARDB=y
CONFIG_MACH_TQMLS1046A=y
CONFIG_64BIT=y
@@ -83,6 +84,7 @@ CONFIG_NET=y
CONFIG_NET_NETCONSOLE=y
CONFIG_OF_BAREBOX_DRIVERS=y
CONFIG_DRIVER_SERIAL_NS16550=y
+CONFIG_DRIVER_NET_FSL_ENETC=y
CONFIG_DRIVER_NET_FSL_FMAN=y
CONFIG_DP83867_PHY=y
CONFIG_REALTEK_PHY=y
@@ -112,12 +114,13 @@ CONFIG_WATCHDOG_IMX=y
CONFIG_GPIO_PCA953X=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED=y
+CONFIG_PCI_LAYERSCAPE=y
+CONFIG_PCI_ECAM_GENERIC=y
CONFIG_FS_EXT4=y
CONFIG_FS_TFTP=y
CONFIG_FS_NFS=y
CONFIG_FS_FAT=y
CONFIG_FS_FAT_WRITE=y
-CONFIG_FS_FAT_LFN=y
CONFIG_FS_UBIFS=y
CONFIG_FS_UBIFS_COMPRESSION_LZO=y
CONFIG_ZLIB=y
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 04af3bd646..301014eaff 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -214,6 +214,7 @@ lwl-$(CONFIG_MACH_XILINX_ZCU106) += zynqmp-zcu106-revA.dtb.o
lwl-$(CONFIG_MACH_ZII_IMX7D_DEV) += imx7d-zii-rpu2.dtb.o imx7d-zii-rmu2.dtb.o
lwl-$(CONFIG_MACH_WAGO_PFC_AM35XX) += am35xx-pfc-750_820x.dtb.o
+lwl-$(CONFIG_MACH_LS1028ARDB) += fsl-ls1028a-rdb.dtb.o
lwl-$(CONFIG_MACH_LS1046ARDB) += fsl-ls1046a-rdb.dtb.o
lwl-$(CONFIG_MACH_TQMLS1046A) += fsl-tqmls1046a-mbls10xxa.dtb.o
lwl-$(CONFIG_MACH_LS1021AIOT) += fsl-ls1021a-iot.dtb.o
diff --git a/arch/arm/dts/fsl-ls1028a-rdb.dts b/arch/arm/dts/fsl-ls1028a-rdb.dts
new file mode 100644
index 0000000000..671c97413b
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1028a-rdb.dts
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <arm64/freescale/fsl-ls1028a-rdb.dts>
+#include "fsl-ls1028a.dtsi"
+
+/ {
+ chosen {
+ environment-sd {
+ status = "disabled";
+ compatible = "barebox,environment";
+ device-path = &part_env_sd;
+ };
+
+ environment-emmc {
+ status = "disabled";
+ compatible = "barebox,environment";
+ device-path = &part_env_emmc;
+ };
+ };
+
+ memory@80000000 {
+ /* Upstream dts has size 4GiB here which is wrong */
+ reg = <0x0 0x80000000 0x0 0x80000000>;
+ };
+};
+
+/* SD */
+&esdhc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@1000 {
+ label = "barebox";
+ reg = <0x1000 0x1df000>;
+ };
+
+ part_env_sd: partition@1e0000 {
+ label = "barebox-environment";
+ reg = <0x1e0000 0x20000>;
+ };
+};
+
+/* eMMC */
+&esdhc1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@1000 {
+ label = "barebox";
+ reg = <0x1000 0x1df000>;
+ };
+
+ part_env_emmc: partition@1e0000 {
+ label = "barebox-environment";
+ reg = <0x1e0000 0x20000>;
+ };
+};
diff --git a/arch/arm/mach-layerscape/Kconfig b/arch/arm/mach-layerscape/Kconfig
index 52527f0c15..5658a63b33 100644
--- a/arch/arm/mach-layerscape/Kconfig
+++ b/arch/arm/mach-layerscape/Kconfig
@@ -7,7 +7,6 @@ config ARCH_LAYERSCAPE_PPA
select ARM_PSCI_OF
select ARM_SMCCC
select FITIMAGE
- bool
help
The "Primary Protected Application" (PPA) is a PSCI compliant firmware
distributed by NXP. It is needed to start the secondary cores on
@@ -15,12 +14,24 @@ config ARCH_LAYERSCAPE_PPA
work properly. The precompiled firmware images can be found here:
https://github.com/NXP/qoriq-ppa-binary
-config ARCH_LS1046
+config ARCH_LS1028
+ bool
select CPU_V8
+ select SYS_SUPPORTS_64BIT_KERNEL
+ select ARM_ATF
+ select FIRMWARE_LS1028A_ATF
+
+config ARCH_LS1046
bool
+ select CPU_V8
+ select SYS_SUPPORTS_64BIT_KERNEL
if 64BIT
+config MACH_LS1028ARDB
+ bool "QorIQ LS1028A Reference Design Board"
+ select ARCH_LS1028
+
config MACH_LS1046ARDB
bool "QorIQ LS1046A Reference Design Board"
select ARCH_LS1046
diff --git a/images/Makefile.layerscape b/images/Makefile.layerscape
index e36dc5000a..9cb88270d7 100644
--- a/images/Makefile.layerscape
+++ b/images/Makefile.layerscape
@@ -21,6 +21,15 @@ quiet_cmd_lspbl_spi_image = LSPBL-SPI-IMG $@
$(objtree)/scripts/pblimage -o $@ -r $(lspbl-rcw-tmp) -s \
-c $(2) -m $($(patsubst $(obj)/%.pblb,PBL_CODE_SIZE_%,$<)) -p $(lspbl-pbi-tmp) -i $<
+pbl-$(CONFIG_MACH_LS1028ARDB) += start_ls1028ardb.pbl
+
+$(obj)/barebox-ls1028ardb-sd.image: $(obj)/start_ls1028ardb.pblb \
+ $(board)/ls1028ardb/ls1028ardb_rcw_sd.cfg \
+ $(board)/ls1028ardb/ls1028ardb_pbi.cfg
+ $(call if_changed,lspbl_image,ls1028a)
+
+image-$(CONFIG_MACH_LS1028ARDB) += barebox-ls1028ardb-sd.image
+
pbl-$(CONFIG_MACH_LS1046ARDB) += start_ls1046ardb.pbl
$(obj)/barebox-ls1046ardb-sd.image: $(obj)/start_ls1046ardb.pblb \
--
2.39.2
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