[PATCH v2 00/11] ARM64: layerscape: make LS1046 DMA coherent

[PATCH v2 00/11] ARM64: layerscape: make LS1046 DMA coherent

[Ahmad Fatoum]

Upstream DT changed /soc of NXP Layerscape LS1046A to be dma-coherent.
This means that:

 1) Linux v6.1 expects bootloader to configure DMA masters to snoop
    caches
 2) bootloader needs to skip cache maintenance when talking to DMA
    master when it has set snoop bits

 This series does that and thereby restores USB functionality when
 booting Linux v6.1 with barebox. For older kernels, dma-coherent
 is fixed up into kernel DT, so newer barebox versions can boot both
 kernels.

This v2 incorporates Sascha's feedback on v1 and fixes bugs that
I noticed after further testing on LS1046A boards. I tested against
Linux v6.6.4.

v1 was here:
https://lore.barebox.org/barebox/20230221080524.607241-1-a.fatoum@pengutronix.de/

Ahmad Fatoum (11):
  dma: rename OF_DMA_DEFAULT_COHERENT to ARCH_DMA_DEFAULT_COHERENT
  dma: select ARCH_DMA_DEFAULT_COHERENT for x86 and sandbox
  dma: introduce CONFIG_OF_DMA_COHERENCY
  RISC-V: StarFive: J7100: set /soc/dma-noncoherent
  ARM: dts: layerscape: add header for barebox DT overrides
  ARM: dts: layerscape: mark ls1046a SoC DMA incoherent in DT
  of: populate new device_d::dma_coherent attribute
  dma: fix dma_sync when not all device DMA is equally coherent
  dma: align barebox DMA coherency setting with kernel's
  ARM: layerscape: configure all DMA masters to be cache-coherent
  ARM: layerscape: enable DWC3 snooping on ls1046a

 arch/Kconfig                                |  7 ++++
 arch/arm/Kconfig                            |  1 +
 arch/arm/dts/fsl-ls1046a-rdb.dts            |  2 +-
 arch/arm/dts/fsl-ls1046a.dtsi               |  7 ++++
 arch/arm/dts/fsl-tqmls1046a-mbls10xxa.dts   |  2 +-
 arch/arm/mach-layerscape/lowlevel-ls1046a.c | 10 +++---
 arch/arm/mach-layerscape/soc.c              | 32 +++++++++++++++++
 arch/riscv/Kconfig                          |  2 +-
 arch/riscv/Kconfig.socs                     |  1 +
 arch/riscv/dts/jh7100.dtsi                  |  1 +
 arch/sandbox/Kconfig                        |  1 +
 arch/x86/Kconfig                            |  1 +
 commands/devinfo.c                          |  4 +++
 drivers/dma/Kconfig                         | 13 +++++++
 drivers/dma/Makefile                        |  1 +
 drivers/dma/map.c                           | 12 ++++---
 drivers/dma/of_fixups.c                     | 40 +++++++++++++++++++++
 drivers/of/Kconfig                          |  4 ---
 drivers/of/platform.c                       | 17 +++++----
 include/driver.h                            | 22 ++++++++++++
 include/soc/fsl/immap_lsch2.h               |  7 ++++
 21 files changed, 165 insertions(+), 22 deletions(-)
 create mode 100644 arch/arm/dts/fsl-ls1046a.dtsi
 create mode 100644 drivers/dma/of_fixups.c

-- 
2.39.2

[PATCH v2 01/11] dma: rename OF_DMA_DEFAULT_COHERENT to ARCH_DMA_DEFAULT_COHERENT

[Ahmad Fatoum]

The symbol is not visible and only used by of_dma_is_coherent, which
has no current callers.

It was added to extend devices with a DMA coherency attribute like done
in Linux and was renamed there in commit c00a60d6f4a1 ("of: address: always
use dma_default_coherent for default coherency"), so have barebox follow
suit.

No functional change.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
v1 -> v2:
  - new patch to sync with Linux
---
 arch/Kconfig          | 7 +++++++
 arch/riscv/Kconfig    | 2 +-
 drivers/of/Kconfig    | 4 ----
 drivers/of/platform.c | 2 +-
 4 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/arch/Kconfig b/arch/Kconfig
index 1a9d32370422..2212b8928829 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -11,3 +11,10 @@ source "arch/$(SRCARCH)/Kconfig"
 
 config ARCH_HAS_CTRLC
 	bool
+
+#
+# Select this option if the architecture assumes DMA devices are coherent
+# by default.
+#
+config ARCH_DMA_DEFAULT_COHERENT
+        bool
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index afbd55aa3e6f..c31c39454a25 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -10,7 +10,7 @@ config RISCV
 	select COMMON_CLK_OF_PROVIDER
 	select CLKDEV_LOOKUP
 	select HAS_DMA
-	select OF_DMA_DEFAULT_COHERENT
+	select ARCH_DMA_DEFAULT_COHERENT
 	select HAVE_PBL_IMAGE
 	select HAVE_PBL_MULTI_IMAGES
 	select HAVE_IMAGE_COMPRESSION
diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig
index 816aff0063b0..71f6103f0e69 100644
--- a/drivers/of/Kconfig
+++ b/drivers/of/Kconfig
@@ -35,10 +35,6 @@ config FEATURE_CONTROLLER_FIXUP
 config OF_ADDRESS_PCI
 	bool
 
-config OF_DMA_DEFAULT_COHERENT
-	# arches should select this if DMA is coherent by default for OF devices
-	bool
-
 config OF_GPIO
 	depends on GPIOLIB
 	depends on OFDEVICE
diff --git a/drivers/of/platform.c b/drivers/of/platform.c
index 9ba4438812c1..dc6c53b7163b 100644
--- a/drivers/of/platform.c
+++ b/drivers/of/platform.c
@@ -109,7 +109,7 @@ bool of_dma_is_coherent(struct device_node *node)
 		node = of_get_next_dma_parent(node);
 	}
 
-	return IS_ENABLED(CONFIG_OF_DMA_DEFAULT_COHERENT);
+	return IS_ENABLED(CONFIG_ARCH_DMA_DEFAULT_COHERENT);
 }
 EXPORT_SYMBOL_GPL(of_dma_is_coherent);
 
-- 
2.39.2

[PATCH v2 02/11] dma: select ARCH_DMA_DEFAULT_COHERENT for x86 and sandbox

[Ahmad Fatoum]

Linux only considers the value of CONFIG_ARCH_DMA_DEFAULT_COHERENT if
the architecture also defines either of:

  - CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE
  - CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU
  - CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL

We don't have those in barebox and also have less architectures to
support, so we'll just select ARCH_DMA_DEFAULT_COHERENT from all
architectures where this applies to: x86, sandbox and RISC-V.
RISC-V already selects it, so we add it to the other two.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
  v1 -> v2:
    - select symbol for sandbox as well
---
 arch/sandbox/Kconfig | 1 +
 arch/x86/Kconfig     | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/sandbox/Kconfig b/arch/sandbox/Kconfig
index 136a97b1ad30..3419b6e4f686 100644
--- a/arch/sandbox/Kconfig
+++ b/arch/sandbox/Kconfig
@@ -18,6 +18,7 @@ config SANDBOX
 	select ARCH_HAS_SJLJ
 	select ARCH_HAS_CTRLC
 	select HAS_DEBUG_LL
+	select ARCH_DMA_DEFAULT_COHERENT
 	default y
 
 config ARCH_TEXT_BASE
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index bd6a94bd0b0e..b982ea32cb3a 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -5,6 +5,7 @@ config X86
 	select HAS_KALLSYMS
 	select HAS_DMA
 	select GENERIC_FIND_NEXT_BIT
+	select ARCH_DMA_DEFAULT_COHERENT
 	default y
 
 config ARCH_TEXT_BASE
-- 
2.39.2

[PATCH v2 03/11] dma: introduce CONFIG_OF_DMA_COHERENCY

[Ahmad Fatoum]

Some architectures are either exclusively cache-coherent or not, but
some others can have only some devices that snoop the bus, while the
rest doesn't. This information can be encoded in the device tree, but
we don't want to look this up in the device tree for the vast majority
of platforms that are either completely coherent or aren't.

Therefore provide a new CONFIG_OF_DMA_COHERENCY symbol for selections
by platforms that require this functionality.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
v1 -> v2:
  - make of_dma_is_coherent DT walking dependent on
    CONFIG_OF_DMA_COHERENCY
---
 drivers/dma/Kconfig   | 10 ++++++++++
 drivers/of/platform.c | 14 ++++++++------
 2 files changed, 18 insertions(+), 6 deletions(-)

diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 46b9b90d8231..635b11c7af7d 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -7,4 +7,14 @@ config MXS_APBH_DMA
 	select STMP_DEVICE
 	help
 	  Experimental!
+
+config OF_DMA_COHERENCY
+	bool "Respect device tree DMA coherency settings" if COMPILE_TEST
+	depends on HAS_DMA && OFDEVICE
+	help
+	  For most platforms supported, either all DMA is coherent or it isn't.
+	  Platforms that have DMA masters of mixed coherency or that differ
+	  from the architecture default will select this option to parse
+	  DMA coherency out of the DT.
+
 endmenu
diff --git a/drivers/of/platform.c b/drivers/of/platform.c
index dc6c53b7163b..edfeb192d434 100644
--- a/drivers/of/platform.c
+++ b/drivers/of/platform.c
@@ -101,12 +101,14 @@ static struct device_node *of_get_next_dma_parent(const struct device_node *np)
  */
 bool of_dma_is_coherent(struct device_node *node)
 {
-	while (node) {
-		if (of_property_read_bool(node, "dma-coherent"))
-			return true;
-		if (of_property_read_bool(node, "dma-noncoherent"))
-			return false;
-		node = of_get_next_dma_parent(node);
+	if (IS_ENABLED(CONFIG_OF_DMA_COHERENCY)) {
+		while (node) {
+			if (of_property_read_bool(node, "dma-coherent"))
+				return true;
+			if (of_property_read_bool(node, "dma-noncoherent"))
+				return false;
+			node = of_get_next_dma_parent(node);
+		}
 	}
 
 	return IS_ENABLED(CONFIG_ARCH_DMA_DEFAULT_COHERENT);
-- 
2.39.2

[PATCH v2 04/11] RISC-V: StarFive: J7100: set /soc/dma-noncoherent

[Ahmad Fatoum]

With upcoming changes, cache handling will be skipped on RISC-V, because
arch is cache-coherent by default. StarFive JH7100 has non-coherent DMA
masters though, so note that in the DT.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
v1 -> v2:
  - no change
---
 arch/riscv/Kconfig.socs    | 1 +
 arch/riscv/dts/jh7100.dtsi | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 56ba5ecf5865..cef9cd52300c 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -88,6 +88,7 @@ config SOC_STARFIVE_JH7100
 	bool
 	select SOC_STARFIVE_JH71XX
 	select SIFIVE_L2
+	select OF_DMA_COHERENCY
 	help
 	  Unlike JH7110 and later, CPU on the JH7100 are not cache-coherent
 	  with respect to DMA masters like GMAC and DW MMC controller.
diff --git a/arch/riscv/dts/jh7100.dtsi b/arch/riscv/dts/jh7100.dtsi
index e3990582af97..b11801553bf7 100644
--- a/arch/riscv/dts/jh7100.dtsi
+++ b/arch/riscv/dts/jh7100.dtsi
@@ -212,6 +212,7 @@ soc {
 		#clock-cells = <1>;
 		compatible = "simple-bus";
 		ranges;
+		dma-noncoherent;
 
 		intram0: sram@18000000 {
 			compatible = "mmio-sram";
-- 
2.39.2

[PATCH v2 05/11] ARM: dts: layerscape: add header for barebox DT overrides

[Ahmad Fatoum]

We don't use the ls1046a-rdb kernel device tree as-is for barebox, but
instead include it and override some nodes. Some overrides can be
applicable to all SoCs so add a new file that's ls1046a-specific.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
v1 -> v2:
  - new patch
---
 arch/arm/dts/fsl-ls1046a-rdb.dts          | 2 +-
 arch/arm/dts/fsl-ls1046a.dtsi             | 7 +++++++
 arch/arm/dts/fsl-tqmls1046a-mbls10xxa.dts | 2 +-
 3 files changed, 9 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/dts/fsl-ls1046a.dtsi

diff --git a/arch/arm/dts/fsl-ls1046a-rdb.dts b/arch/arm/dts/fsl-ls1046a-rdb.dts
index 5a75212bb5e6..37023fae9be0 100644
--- a/arch/arm/dts/fsl-ls1046a-rdb.dts
+++ b/arch/arm/dts/fsl-ls1046a-rdb.dts
@@ -3,11 +3,11 @@
 /dts-v1/;
 
 #include <arm64/freescale/fsl-ls1046a-rdb.dts>
+#include "fsl-ls1046a.dtsi"
 
 / {
 	aliases {
 		eeprom = &{i2c0/eeprom@52};
-		mmc0 = &esdhc;
 	};
 
 	chosen {
diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
new file mode 100644
index 000000000000..a661cb0c8970
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/ {
+	aliases {
+		mmc0 = &esdhc;
+	};
+};
diff --git a/arch/arm/dts/fsl-tqmls1046a-mbls10xxa.dts b/arch/arm/dts/fsl-tqmls1046a-mbls10xxa.dts
index 13ce24a8895a..650e89bffe8a 100644
--- a/arch/arm/dts/fsl-tqmls1046a-mbls10xxa.dts
+++ b/arch/arm/dts/fsl-tqmls1046a-mbls10xxa.dts
@@ -11,6 +11,7 @@
 #include <dt-bindings/gpio/gpio.h>
 
 #include "fsl-tqmls1046a.dtsi"
+#include "fsl-ls1046a.dtsi"
 
 / {
 	model = "TQ TQMLS1046A SoM on MBLS10xxA board";
@@ -19,7 +20,6 @@ / {
 	aliases {
 		serial0 = &duart0;
 		serial1 = &duart1;
-		mmc0 = &esdhc;
 		qspiflash0 = &qflash0;
 		qspiflash1 = &qflash1;
 		qsgmii_s1_p1 = &qsgmii1_phy1;
-- 
2.39.2

[PATCH v2 06/11] ARM: dts: layerscape: mark ls1046a SoC DMA incoherent in DT

[Ahmad Fatoum]

This effectively reverts in the barebox DT, Linux commit 136975c33894
("arm64: dts: ls1046a: make dma-coherent global to the SoC").

The reason for that is while the CCI-400 can be configured to make all
bus masters DMA-coherent, barebox (and older versions of U-Boot) didn't yet
do so. We will rectify this in a later commit, but for now restore
working order in case Linux is booted with the barebox DT.

Fixes: 32e2176ba050 ("dts: update to v6.1-rc1")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
v1 -> v2:
  - new patch
---
 arch/arm/dts/fsl-ls1046a.dtsi | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index a661cb0c8970..6af38f737056 100644
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -5,3 +5,24 @@ aliases {
 		mmc0 = &esdhc;
 	};
 };
+
+&soc {
+	/delete-property/ dma-coherent;
+	dma-noncoherent;
+};
+
+&crypto {
+	dma-coherent;
+};
+
+&msi1 {
+	dma-coherent;
+};
+
+&pcie2 {
+	dma-coherent;
+};
+
+&pcie3 {
+	dma-coherent;
+};
-- 
2.39.2

[PATCH v2 07/11] of: populate new device_d::dma_coherent attribute

[Ahmad Fatoum]

So far, whether device DMA is coherent was a one-time global decision.
This is insufficient, because some platforms:

 - are cache coherent, while the architecture isn't in general, e.g.
   barebox support for ARM with CONFIG_MMU=y assumes non-coherent DMA,
   but LS1046A can be fully coherent.

 - have a mix of devices that snoop caches and devices that don't
   (StarFive JH7100).

To enable dev_dma_(map|unmap)_single to take the correct device-specific
action with regards to cache maintenance, provide dev_is_dma_coherent()
with semantics similar to what Linux provides.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
v1 -> v2:
  - make dma_coherent a boolean (Sascha)
  - add dma_coherent unconditionally (Sascha)
  - Only print dma_coherent status for devices with OF node
---
 commands/devinfo.c    |  4 ++++
 drivers/of/platform.c |  1 +
 include/driver.h      | 22 ++++++++++++++++++++++
 3 files changed, 27 insertions(+)

diff --git a/commands/devinfo.c b/commands/devinfo.c
index aeb9c5533931..6001b00cfac8 100644
--- a/commands/devinfo.c
+++ b/commands/devinfo.c
@@ -105,6 +105,10 @@ static int do_devinfo(int argc, char *argv[])
 		if (dev->of_node) {
 			struct device *main_dev = dev->of_node->dev;
 
+			printf("DMA Coherent: %s%s\n",
+			       dev_is_dma_coherent(dev) ? "true" : "false",
+			       dev->dma_coherent == DEV_DMA_COHERENCE_DEFAULT ? " (default)" : "");
+
 			printf("Device node: %pOF", dev->of_node);
 			if (!main_dev) {
 			       printf(" (unpopulated)\n");
diff --git a/drivers/of/platform.c b/drivers/of/platform.c
index edfeb192d434..060fa3458bd2 100644
--- a/drivers/of/platform.c
+++ b/drivers/of/platform.c
@@ -129,6 +129,7 @@ static void of_dma_configure(struct device *dev, struct device_node *np)
 	}
 
 	dev->dma_offset = offset;
+	dev->dma_coherent = of_dma_is_coherent(np);
 }
 
 /**
diff --git a/include/driver.h b/include/driver.h
index b37b0ab192a3..c23404ca16fb 100644
--- a/include/driver.h
+++ b/include/driver.h
@@ -25,6 +25,12 @@ struct platform_device_id {
 	unsigned long driver_data;
 };
 
+enum dev_dma_coherence {
+	DEV_DMA_COHERENCE_DEFAULT = 0,
+	DEV_DMA_COHERENT,
+	DEV_DMA_NON_COHERENT,
+};
+
 /** @brief Describes a particular device present in the system */
 struct device {
 	/*! This member (and 'type' described below) is used to match
@@ -45,6 +51,8 @@ struct device {
 	 * something like eth0 or nor0. */
 	int id;
 
+	enum dev_dma_coherence dma_coherent;
+
 	struct resource *resource;
 	int num_resources;
 
@@ -720,6 +728,20 @@ static inline struct device_node *dev_of_node(struct device *dev)
 	return IS_ENABLED(CONFIG_OFDEVICE) ? dev->of_node : NULL;
 }
 
+static inline bool dev_is_dma_coherent(struct device *dev)
+{
+	switch (dev->dma_coherent) {
+	case DEV_DMA_NON_COHERENT:
+		return false;
+	case DEV_DMA_COHERENT:
+		return true;
+	case DEV_DMA_COHERENCE_DEFAULT:
+		break;
+	}
+
+	return IS_ENABLED(CONFIG_ARCH_DMA_DEFAULT_COHERENT);
+}
+
 static inline void *dev_get_priv(const struct device *dev)
 {
 	return dev->priv;
-- 
2.39.2

[PATCH v2 08/11] dma: fix dma_sync when not all device DMA is equally coherent

[Ahmad Fatoum]

The LS1046A features a cache-coherent interconnect and the drivers
configure the hardware appropriately, e.g. setting the FMan PRAM_MODE_GLOBAL
bit, so the existing Ethernet Controllers snoop caches.

Yet, we use the standard arm64 cache maintenance routines when the MMU
is enabled and thus risk memory corruption if CPU prefetches receive buffers
in the time window between dma_map_single() cleaning them to
Point-of-Coherency and dma_unmap_single() invalidating them[1].

To properly solve this issue, we need to consult the newly added per-device
dma coherent attribute to decide whether to do manual cache maintenance.

[1]: https://lore.kernel.org/all/a5d6cc26-cd23-7c31-f56e-f6d535ea39b0@arm.com/

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
v1 -> v2:
  - switch to boolean comparisons instead of comparison <= or >= to zero
---
 drivers/dma/map.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/dma/map.c b/drivers/dma/map.c
index e320f6aad4ac..ab86a8c7b139 100644
--- a/drivers/dma/map.c
+++ b/drivers/dma/map.c
@@ -9,7 +9,8 @@ void dma_sync_single_for_cpu(struct device *dev, dma_addr_t address,
 
 	debug_dma_sync_single_for_cpu(dev, address, size, dir);
 
-	arch_sync_dma_for_cpu(ptr, size, dir);
+	if (!dev_is_dma_coherent(dev))
+		arch_sync_dma_for_cpu(ptr, size, dir);
 }
 
 void dma_sync_single_for_device(struct device *dev, dma_addr_t address,
@@ -19,7 +20,8 @@ void dma_sync_single_for_device(struct device *dev, dma_addr_t address,
 
 	debug_dma_sync_single_for_device(dev, address, size, dir);
 
-	arch_sync_dma_for_device(ptr, size, dir);
+	if (!dev_is_dma_coherent(dev))
+		arch_sync_dma_for_device(ptr, size, dir);
 }
 
 dma_addr_t dma_map_single(struct device *dev, void *ptr,
@@ -29,7 +31,8 @@ dma_addr_t dma_map_single(struct device *dev, void *ptr,
 
 	debug_dma_map(dev, ptr, size, dir, dma_addr);
 
-	arch_sync_dma_for_device(ptr, size, dir);
+	if (!dev_is_dma_coherent(dev))
+		arch_sync_dma_for_device(ptr, size, dir);
 
 	return dma_addr;
 }
@@ -37,7 +40,8 @@ dma_addr_t dma_map_single(struct device *dev, void *ptr,
 void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
 				    size_t size, enum dma_data_direction dir)
 {
-	dma_sync_single_for_cpu(dev, dma_addr, size, dir);
+	if (!dev_is_dma_coherent(dev))
+		dma_sync_single_for_cpu(dev, dma_addr, size, dir);
 
 	debug_dma_unmap(dev, dma_addr, size, dir);
 }
-- 
2.39.2

[PATCH v2 09/11] dma: align barebox DMA coherency setting with kernel's

[Ahmad Fatoum]

ARM platforms that have cache-coherent peripherals should select
OF_DMA_COHERENCY. These same platforms may run into issues if kernel DT
is changed to assume cache coherency, while barebox DT wasn't.

Therefore add a fixup that fixes up barebox dma-coherent setting into
the kernel's. That way we only have to make sure that Linux and barebox
are in-sync regarding CONFIG_ARCH_DMA_DEFAULT_COHERENT.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
v1 -> v2:
  - split from Layerscape support and make it generic to all users of
    CONFIG_OF_DMA_COHERENCY
  - fixup both dma-coherent or dma-noncoherent if needed
  - don't fix up new property of coherency setting is the default
---
 drivers/dma/Kconfig     |  5 ++++-
 drivers/dma/Makefile    |  1 +
 drivers/dma/of_fixups.c | 40 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 45 insertions(+), 1 deletion(-)
 create mode 100644 drivers/dma/of_fixups.c

diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 635b11c7af7d..e7516466d9d3 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -15,6 +15,9 @@ config OF_DMA_COHERENCY
 	  For most platforms supported, either all DMA is coherent or it isn't.
 	  Platforms that have DMA masters of mixed coherency or that differ
 	  from the architecture default will select this option to parse
-	  DMA coherency out of the DT.
+	  DMA coherency out of the DT. This allows barebox to choose the
+	  correct cache maintenance operation during runtime and will cause
+	  barebox to fix up its own DMA coherency setting into the kernel
+	  DT if it differs.
 
 endmenu
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index b55c16e768d5..77bd8abba52c 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -2,3 +2,4 @@
 obj-$(CONFIG_HAS_DMA)		+= map.o
 obj-$(CONFIG_DMA_API_DEBUG)	+= debug.o
 obj-$(CONFIG_MXS_APBH_DMA)	+= apbh_dma.o
+obj-$(CONFIG_OF_DMA_COHERENCY)	+= of_fixups.o
diff --git a/drivers/dma/of_fixups.c b/drivers/dma/of_fixups.c
new file mode 100644
index 000000000000..668313bbfb57
--- /dev/null
+++ b/drivers/dma/of_fixups.c
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <of.h>
+#include <of_address.h>
+#include <driver.h>
+
+static int of_dma_coherent_fixup(struct device_node *root, void *data)
+{
+	struct device_node *soc;
+	enum dev_dma_coherence coherency = (enum dev_dma_coherence)(uintptr_t)data;
+
+	soc = of_find_node_by_path_from(root, "/soc");
+	if (!soc)
+		return -ENOENT;
+
+	of_property_write_bool(soc, "dma-noncoherent", coherency == DEV_DMA_NON_COHERENT);
+	of_property_write_bool(soc, "dma-coherent", coherency == DEV_DMA_COHERENT);
+
+	return 0;
+}
+
+static int of_dma_coherent_fixup_register(void)
+{
+	struct device_node *soc;
+	enum dev_dma_coherence soc_dma_coherency;
+
+	soc = of_find_node_by_path("/soc");
+	if (!soc)
+		return -ENOENT;
+
+	if (of_property_read_bool(soc, "dma-coherent"))
+		soc_dma_coherency = DEV_DMA_COHERENT;
+	else if (of_property_read_bool(soc, "dma-noncoherent"))
+		soc_dma_coherency = DEV_DMA_NON_COHERENT;
+	else
+		soc_dma_coherency = DEV_DMA_COHERENCE_DEFAULT;
+
+	return of_register_fixup(of_dma_coherent_fixup, (void *)(uintptr_t)soc_dma_coherency);
+}
+coredevice_initcall(of_dma_coherent_fixup_register);
-- 
2.39.2

[PATCH v2 10/11] ARM: layerscape: configure all DMA masters to be cache-coherent

[Ahmad Fatoum]

Upstream device tree now has /soc/dma-coherent, which breaks USB in
Linux v6.1 when kernel is booted with barebox. Fix this by:

  - setting the snoop bits for the DMA masters, so we properly support
    Linux >= v6.1 DTs

  - fixing up cache coherency setting into kernel DT whenever barebox
    DT has /soc/dma-coherent to support older device trees

The latter is done automatically when OF_DMA_COHERENCY is selected, so
add the missing snoop bits here.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
v1 -> v2:
  - remove DT fixups introduced earlier
  - DT fixup split into previous commit
---
 arch/arm/Kconfig                            |  1 +
 arch/arm/dts/fsl-ls1046a.dtsi               | 21 ---------------------
 arch/arm/mach-layerscape/lowlevel-ls1046a.c | 10 ++++++----
 include/soc/fsl/immap_lsch2.h               |  7 +++++++
 4 files changed, 14 insertions(+), 25 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0557567a599f..089ce43c88bd 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -246,6 +246,7 @@ config ARCH_LAYERSCAPE
 	select OFTREE
 	select OFDEVICE
 	select ARM_USE_COMPRESSED_DTB
+	select OF_DMA_COHERENCY
 
 config ARCH_OMAP_MULTI
 	bool "TI OMAP"
diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index 6af38f737056..a661cb0c8970 100644
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -5,24 +5,3 @@ aliases {
 		mmc0 = &esdhc;
 	};
 };
-
-&soc {
-	/delete-property/ dma-coherent;
-	dma-noncoherent;
-};
-
-&crypto {
-	dma-coherent;
-};
-
-&msi1 {
-	dma-coherent;
-};
-
-&pcie2 {
-	dma-coherent;
-};
-
-&pcie3 {
-	dma-coherent;
-};
diff --git a/arch/arm/mach-layerscape/lowlevel-ls1046a.c b/arch/arm/mach-layerscape/lowlevel-ls1046a.c
index 3393dc49031e..1307c05eaf6d 100644
--- a/arch/arm/mach-layerscape/lowlevel-ls1046a.c
+++ b/arch/arm/mach-layerscape/lowlevel-ls1046a.c
@@ -229,11 +229,13 @@ void ls1046a_init_lowlevel(void)
 	set_cntfrq(25000000);
 	syscnt_enable(IOMEM(LSCH2_SYS_COUNTER_ADDR));
 
-	/* Make SEC reads and writes snoopable */
+	/* Make DMA master reads and writes snoopable */
 	setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
-		SCFG_SNPCNFGCR_SECWRSNP |
-		SCFG_SNPCNFGCR_SATARDSNP |
-		SCFG_SNPCNFGCR_SATAWRSNP);
+		SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
+		SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
+		SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
+		SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
+		SCFG_SNPCNFGCR_SATAWRSNP | SCFG_SNPCNFGCR_EDMASNP);
 
 	/*
 	 * Enable snoop requests and DVM message requests for
diff --git a/include/soc/fsl/immap_lsch2.h b/include/soc/fsl/immap_lsch2.h
index 0993fa1cd85a..6a7dad3d5d0d 100644
--- a/include/soc/fsl/immap_lsch2.h
+++ b/include/soc/fsl/immap_lsch2.h
@@ -314,6 +314,13 @@ struct ls102xa_ccsr_gur {
 #define SCFG_SNPCNFGCR_SECWRSNP		0x40000000
 #define SCFG_SNPCNFGCR_SATARDSNP	0x00800000
 #define SCFG_SNPCNFGCR_SATAWRSNP	0x00400000
+#define SCFG_SNPCNFGCR_USB1RDSNP	0x00200000
+#define SCFG_SNPCNFGCR_USB1WRSNP	0x00100000
+#define SCFG_SNPCNFGCR_EDMASNP		0x00020000
+#define SCFG_SNPCNFGCR_USB2RDSNP	0x00008000
+#define SCFG_SNPCNFGCR_USB2WRSNP	0x00010000
+#define SCFG_SNPCNFGCR_USB3RDSNP	0x00002000
+#define SCFG_SNPCNFGCR_USB3WRSNP	0x00004000
 
 /* RGMIIPCR bit definitions*/
 #define SCFG_RGMIIPCR_EN_AUTO		BIT(3)
-- 
2.39.2

[PATCH v2 11/11] ARM: layerscape: enable DWC3 snooping on ls1046a

[Ahmad Fatoum]

The SCFG_SNPCNFGCR USB bits only have an effect if the
Layerscape-specific bits in each DWC instance's GSBUSCFG0 are
appropriately configured.

As the LS1046's kernel DT is configured to assume the whole SoC is dma-coherent,
we need to set these bits, so this is indeed the case.

This configuration is likewise applicable to the LS1043A, should
we add support for it and to the newly added LS1028A, if we start
configuring the CCI-400 to make the fully cache-coherent, but alas,
that's not yet the case and the LS1028A's kernel DT doesn't assume it.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
v1 -> v2:
  - new patch
---
 arch/arm/mach-layerscape/soc.c | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/arch/arm/mach-layerscape/soc.c b/arch/arm/mach-layerscape/soc.c
index 462405ea870b..1742ff58ce10 100644
--- a/arch/arm/mach-layerscape/soc.c
+++ b/arch/arm/mach-layerscape/soc.c
@@ -4,9 +4,11 @@
 #include <init.h>
 #include <memory.h>
 #include <linux/bug.h>
+#include <linux/bitfield.h>
 #include <linux/printk.h>
 #include <mach/layerscape/layerscape.h>
 #include <of.h>
+#include <of_address.h>
 
 int __layerscape_soc_type;
 
@@ -120,6 +122,35 @@ static int ls1028a_reserve_tfa(void)
 }
 mmu_initcall(ls1028a_reserve_tfa);
 
+#define DWC3_GSBUSCFG0				0xc100
+#define DWC3_GSBUSCFG0_CACHETYPE_MASK		GENMASK(31, 16)
+
+static void layerscape_usb_enable_snooping(void)
+{
+	struct device_node *np;
+
+	for_each_compatible_node(np, NULL, "snps,dwc3") {
+		struct resource res;
+
+		if (of_address_to_resource(np, 0, &res))
+			continue;
+
+		/* Set cacheable bit for all of Data read, Descriptor read,
+		 * Data write and Descriptor write. Bufferable and read/write
+		 * allocate bits are not set. This is the recommended configurationr
+		 * in LS1046ARM Rev. 3 34.2.10.2:
+		 * "For master interface DMA access, program the GSBUSCFG0
+		 * register to 0x2222000F for better performance.".
+		 * The 0x000F is configured via snps,incr-burst-type-adjustment
+		 * (which despite the name is Layerscape-specific), so below
+		 * line only manipulates the upper 16 bits.
+		 */
+		clrsetbits_le32(IOMEM(res.start) + DWC3_GSBUSCFG0,
+				DWC3_GSBUSCFG0_CACHETYPE_MASK,
+				FIELD_PREP(DWC3_GSBUSCFG0_CACHETYPE_MASK, 0x2222));
+	}
+}
+
 static int ls1046a_init(void)
 {
 	if (!cpu_is_ls1046a())
@@ -128,6 +159,7 @@ static int ls1046a_init(void)
 	ls1046a_bootsource_init();
 	ls1046a_setup_icids();
 	layerscape_register_pbl_image_handler();
+	layerscape_usb_enable_snooping();
 
 	return 0;
 }
-- 
2.39.2

Re: [PATCH v2 00/11] ARM64: layerscape: make LS1046 DMA coherent

[Sascha Hauer]

On Wed, 10 Jan 2024 17:01:02 +0100, Ahmad Fatoum wrote:
> Upstream DT changed /soc of NXP Layerscape LS1046A to be dma-coherent.
> This means that:
> 
>  1) Linux v6.1 expects bootloader to configure DMA masters to snoop
>     caches
>  2) bootloader needs to skip cache maintenance when talking to DMA
>     master when it has set snoop bits
> 
> [...]

Applied, thanks!

[01/11] dma: rename OF_DMA_DEFAULT_COHERENT to ARCH_DMA_DEFAULT_COHERENT
        commit: 6012c3867777e9e6d6b14d0117f8b37e2b860642
[02/11] dma: select ARCH_DMA_DEFAULT_COHERENT for x86 and sandbox
        commit: a16e16575ae797e33f1a499b5f6e28f6cf6c3527
[03/11] dma: introduce CONFIG_OF_DMA_COHERENCY
        commit: 62753977d4231a160e4fb3bd3fe585e151792eb4
[04/11] RISC-V: StarFive: J7100: set /soc/dma-noncoherent
        commit: 4c42bc96da90c88b2dcb2b24bb56aad1f9119f9f
[05/11] ARM: dts: layerscape: add header for barebox DT overrides
        commit: 224bbd61d5744b19963f8d0335ef5f355eed9850
[06/11] ARM: dts: layerscape: mark ls1046a SoC DMA incoherent in DT
        commit: 5961dae8f9d11c918522c035889045f6f65bca91
[07/11] of: populate new device_d::dma_coherent attribute
        commit: 804a07a7bb573334b6eeb4049c92f28421f2a00a
[08/11] dma: fix dma_sync when not all device DMA is equally coherent
        commit: f856171ad6bfd067729350d9604622f8cf09ba07
[09/11] dma: align barebox DMA coherency setting with kernel's
        commit: de265d926a92462b836749d2633faef2631b459c
[10/11] ARM: layerscape: configure all DMA masters to be cache-coherent
        commit: 475a399049ce30c40c86bf9e51cfa993f5ce573d
[11/11] ARM: layerscape: enable DWC3 snooping on ls1046a
        commit: f1f215dbef3a49754e03078f61258bd5e06286f7

Best regards,
-- 
Sascha Hauer <s.hauer@pengutronix.de>

Re: [PATCH v2 00/11] ARM64: layerscape: make LS1046 DMA coherent

[Ahmad Fatoum]

Hello Sascha,

On 11.01.24 15:11, Sascha Hauer wrote:
> 
> On Wed, 10 Jan 2024 17:01:02 +0100, Ahmad Fatoum wrote:
>> Upstream DT changed /soc of NXP Layerscape LS1046A to be dma-coherent.
>> This means that:
>>
>>  1) Linux v6.1 expects bootloader to configure DMA masters to snoop
>>     caches
>>  2) bootloader needs to skip cache maintenance when talking to DMA
>>     master when it has set snoop bits
>>
>> [...]
> 
> Applied, thanks!
> 
> [01/11] dma: rename OF_DMA_DEFAULT_COHERENT to ARCH_DMA_DEFAULT_COHERENT
>         commit: 6012c3867777e9e6d6b14d0117f8b37e2b860642

Does the commit hash mean it was applied to master? If it's also for next,
it may be confusing, because these commit hashes aren't stable.

(I don't mind this series going into master though. It fixes a bug after
 all).

Thanks,
Ahmad

> [02/11] dma: select ARCH_DMA_DEFAULT_COHERENT for x86 and sandbox
>         commit: a16e16575ae797e33f1a499b5f6e28f6cf6c3527
> [03/11] dma: introduce CONFIG_OF_DMA_COHERENCY
>         commit: 62753977d4231a160e4fb3bd3fe585e151792eb4
> [04/11] RISC-V: StarFive: J7100: set /soc/dma-noncoherent
>         commit: 4c42bc96da90c88b2dcb2b24bb56aad1f9119f9f
> [05/11] ARM: dts: layerscape: add header for barebox DT overrides
>         commit: 224bbd61d5744b19963f8d0335ef5f355eed9850
> [06/11] ARM: dts: layerscape: mark ls1046a SoC DMA incoherent in DT
>         commit: 5961dae8f9d11c918522c035889045f6f65bca91
> [07/11] of: populate new device_d::dma_coherent attribute
>         commit: 804a07a7bb573334b6eeb4049c92f28421f2a00a
> [08/11] dma: fix dma_sync when not all device DMA is equally coherent
>         commit: f856171ad6bfd067729350d9604622f8cf09ba07
> [09/11] dma: align barebox DMA coherency setting with kernel's
>         commit: de265d926a92462b836749d2633faef2631b459c
> [10/11] ARM: layerscape: configure all DMA masters to be cache-coherent
>         commit: 475a399049ce30c40c86bf9e51cfa993f5ce573d
> [11/11] ARM: layerscape: enable DWC3 snooping on ls1046a
>         commit: f1f215dbef3a49754e03078f61258bd5e06286f7
> 
> Best regards,

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

Re: [PATCH v2 00/11] ARM64: layerscape: make LS1046 DMA coherent

[Sascha Hauer]

On Thu, Jan 11, 2024 at 03:15:35PM +0100, Ahmad Fatoum wrote:
> Hello Sascha,
> 
> On 11.01.24 15:11, Sascha Hauer wrote:
> > 
> > On Wed, 10 Jan 2024 17:01:02 +0100, Ahmad Fatoum wrote:
> >> Upstream DT changed /soc of NXP Layerscape LS1046A to be dma-coherent.
> >> This means that:
> >>
> >>  1) Linux v6.1 expects bootloader to configure DMA masters to snoop
> >>     caches
> >>  2) bootloader needs to skip cache maintenance when talking to DMA
> >>     master when it has set snoop bits
> >>
> >> [...]
> > 
> > Applied, thanks!
> > 
> > [01/11] dma: rename OF_DMA_DEFAULT_COHERENT to ARCH_DMA_DEFAULT_COHERENT
> >         commit: 6012c3867777e9e6d6b14d0117f8b37e2b860642
> 
> Does the commit hash mean it was applied to master? If it's also for next,
> it may be confusing, because these commit hashes aren't stable.

No, it doesn't mean it is applied to master. I just means I am
experimenting with "b4 ty" and that b4 generates this information
automatically.

I could replace the commitish with something like:

https://git.pengutronix.de/cgit/barebox/commit/?id=6012c3867777 (commitish may not be stable)

or just a:

(no commit info)

Sascha

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |