Re: [PATCH 2/3] nvmem: ocotp: prepare adding tester3 support

[Sascha Hauer <sha@pengutronix.de>]

On Fri, Jan 19, 2024 at 11:45:21PM +0100, Ahmad Fatoum wrote:
> The tester fuses are written to the OCOTP by NXP during production.
> So far, we only evaluated tester4 to determine which peripherals
> are missing from the SoC. On the i.MX8MP, VPU and CPUs existence is
> instead encoded into the tester3 fuse word. In preparation for adding
> support for tester4, rename the existing masks to be tester4-specific.
> 
> diff --git a/drivers/soc/imx/imx8m-featctrl.c b/drivers/soc/imx/imx8m-featctrl.c
> index 9a2b66555dce..23a3f990160d 100644
> --- a/drivers/soc/imx/imx8m-featctrl.c
> +++ b/drivers/soc/imx/imx8m-featctrl.c
> @@ -33,6 +33,19 @@ static inline bool is_fused(u32 val, u32 bitmask)
>  	return bitmask && (val & bitmask) == bitmask;
>  }
>  
> +#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))

It's likely time to find a common place for this. We already have that
defined in drivers/clk/at91/pmc.h and the kernel also has this defined
three times.

Sascha


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