[PATCH v3 12/15] ARM: at91: skov-arm9cpu: configure SMC for NOR flash use

[Ahmad Fatoum <a.fatoum@pengutronix.de>]

Deployed ARM9CPU's boots from NOR, not NAND. Replace the EBI NAND configuration
taken from the EK with one appropriate for the NOR chip we have.

As this needs to happen earlier than the cfi-flash driver probe, we also
move the board code to coredevice initlevel.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
v3:
  - new patch
---
 arch/arm/boards/skov-arm9cpu/board.c | 45 +++++++++++++++-------------
 1 file changed, 24 insertions(+), 21 deletions(-)

diff --git a/arch/arm/boards/skov-arm9cpu/board.c b/arch/arm/boards/skov-arm9cpu/board.c
index ddf6b68bcc6f..1d0ecb247d8e 100644
--- a/arch/arm/boards/skov-arm9cpu/board.c
+++ b/arch/arm/boards/skov-arm9cpu/board.c
@@ -16,23 +16,32 @@
 #include <mach/at91/hardware.h>
 #include <mach/at91/iomux.h>
 
-static struct sam9_smc_config ek_nand_smc_config = {
-	.ncs_read_setup		= 0,
-	.nrd_setup		= 1,
+static struct sam9_smc_config skov_nor_smc_config = {
+	/* Setup time is 2 cycles after the CS signal */
+	.nwe_setup		= 2,
 	.ncs_write_setup	= 0,
-	.nwe_setup		= 1,
+	.nrd_setup		= 2,
+	.ncs_read_setup		= 0,
 
-	.ncs_read_pulse		= 3,
-	.nrd_pulse		= 3,
-	.ncs_write_pulse	= 3,
-	.nwe_pulse		= 3,
+	/* Set pulse long enough - pulse should be a bit shorter than the cycle */
+	.nwe_pulse		= 10,
+	.ncs_write_pulse	= 12,
+	.nrd_pulse		= 10,
+	.ncs_read_pulse		= 12,
 
-	.read_cycle		= 5,
-	.write_cycle		= 5,
+	/* Set cycle long enougth at least 12 Cycles->120ns plus a little extra */
+	.write_cycle		= 0x13,
+	.read_cycle		= 0x13,
 
+	/* Set mode: 16Bit bus width, enable read and write
+	 *   Note: pagemode + 32 byte pages do not work with the 29GL512P flash
+	 */
 	.mode			= AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
-				  AT91_SMC_EXNWMODE_DISABLE,
-	.tdf_cycles		= 2,
+				  AT91_SMC_EXNWMODE_DISABLE |
+				  AT91_SMC_BAT_WRITE |
+				  AT91_SMC_DBW_16 |
+				  AT91_SMC_TDFMODE,
+	.tdf_cycles		= 1,
 };
 
 BAREBOX_MAGICVAR(board.mem, "The detected memory size in MiB");
@@ -47,19 +56,13 @@ static int mem;
  */
 static int skov_arm9_probe(struct device *dev)
 {
-	unsigned long csa;
-
 	add_generic_device("at91sam9-smc", 0, NULL, AT91SAM9263_BASE_SMC0, 0x200,
 			   IORESOURCE_MEM, NULL);
 	add_generic_device("at91sam9-smc", 1, NULL, AT91SAM9263_BASE_SMC1, 0x200,
 			   IORESOURCE_MEM, NULL);
 
-	csa = readl(AT91SAM9263_BASE_MATRIX + AT91SAM9263_MATRIX_EBI0CSA);
-	csa |= AT91SAM9263_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA;
-	writel(csa, AT91SAM9263_BASE_MATRIX + AT91SAM9263_MATRIX_EBI0CSA);
-
-	/* configure chip-select 3 (NAND) */
-	sam9_smc_configure(0, 3, &ek_nand_smc_config);
+	/* configure chip-select 0 (NOR) */
+	sam9_smc_configure(0, 0, &skov_nor_smc_config);
 
 	mem = at91_get_sdram_size(IOMEM(AT91SAM9263_BASE_SDRAMC0));
 	mem = mem / SZ_1M;
@@ -82,4 +85,4 @@ static struct driver skov_arm9_driver = {
 	.probe = skov_arm9_probe,
 	.of_compatible = DRV_OF_COMPAT(skov_arm9_ids),
 };
-device_platform_driver(skov_arm9_driver);
+coredevice_platform_driver(skov_arm9_driver);
-- 
2.39.2