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Mon, 04 Mar 2024 20:02:46 +0100 Received: from localhost ([::1] helo=dude05.red.stw.pengutronix.de) by dude05.red.stw.pengutronix.de with esmtp (Exim 4.96) (envelope-from ) id 1rhDYL-00Ed9V-17; Mon, 04 Mar 2024 20:00:45 +0100 From: Ahmad Fatoum To: barebox@lists.infradead.org Cc: Ahmad Fatoum Date: Mon, 4 Mar 2024 19:59:36 +0100 Message-Id: <20240304190038.3486881-52-a.fatoum@pengutronix.de> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240304190038.3486881-1-a.fatoum@pengutronix.de> References: <20240304190038.3486881-1-a.fatoum@pengutronix.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240304_190249_974529_71975936 X-CRM114-Status: GOOD ( 12.52 ) X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:3::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.whiteo.stw.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-5.4 required=4.0 tests=AWL,BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: [PATCH v2 051/113] ARM: mmu-early: gracefully handle already enabled MMU X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.whiteo.stw.pengutronix.de) arm_cpu_lowlevel_init will disable the MMU, but there are valid cases to not call it on startup, e.g. when barebox is being run as EFI payload. To allow booting an EFI-stubbed barebox both as primary bootloader and as EFI payload, teach mmu_early_enable() to bail out when the MMU is already set up. Signed-off-by: Ahmad Fatoum --- arch/arm/cpu/mmu_32.c | 3 +++ arch/arm/cpu/mmu_64.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/arch/arm/cpu/mmu_32.c b/arch/arm/cpu/mmu_32.c index c6eecf9c9d2d..3a8d025ecdee 100644 --- a/arch/arm/cpu/mmu_32.c +++ b/arch/arm/cpu/mmu_32.c @@ -597,6 +597,9 @@ void mmu_early_enable(unsigned long membase, unsigned long memsize) pr_debug("enabling MMU, ttb @ 0x%p\n", ttb); + if (get_cr() & CR_M) + return; + set_ttbr(ttb); /* For the XN bit to take effect, we can't be using DOMAIN_MANAGER. */ diff --git a/arch/arm/cpu/mmu_64.c b/arch/arm/cpu/mmu_64.c index 12cd644de0c7..f907421da998 100644 --- a/arch/arm/cpu/mmu_64.c +++ b/arch/arm/cpu/mmu_64.c @@ -314,6 +314,9 @@ void mmu_early_enable(unsigned long membase, unsigned long memsize) u64 optee_membase; unsigned long ttb = arm_mem_ttb(membase + memsize); + if (get_cr() & CR_M) + return; + pr_debug("enabling MMU, ttb @ 0x%08lx\n", ttb); el = current_el(); -- 2.39.2