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a=openpgp-sha256; l=4089; i=s.trumtrar@pengutronix.de; h=from:subject:message-id; bh=s4HlH3YkfXb3iYj/aKCGYn9p0dxLrs5QiehKJBvOg4k=; b=owGbwMvMwCUmvd38QH3grB+Mp9WSGFJ/iMp6Od9xMXw0TdrtlKX8rErb+Rq2LZEPNh9hzTwrs OWfOk9pRykLgxgXg6yYIkvk2kMam4U/63w5fp4BZg4rE8gQBi5OAZjIQQZGhndxy51WrdDpqp8q FHpE6rE40xrt1RcvRf27dkY5xHaj/DJGhl/P2DcEZz3ls3Lz4hMPz6nSEmRsdRSeGCJQE59Y/UC MAQA= X-Developer-Key: i=s.trumtrar@pengutronix.de; a=openpgp; fpr=59ADC228B313F32CF4C7CF001BB737C07F519AF8 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240318_101922_913158_DAA41E09 X-CRM114-Status: GOOD ( 13.04 ) X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:3::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.whiteo.stw.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-5.2 required=4.0 tests=AWL,BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: [PATCH v4 14/15] mci: arasan-sdhci: add HS200 tuning support on ZynqMP X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.whiteo.stw.pengutronix.de) The ZynpMP 8.9a has an Arasan IP core that supports HS200 tuning. Register the callback with the mci-core. Arasan uses the SDHCI tuning method. Signed-off-by: Steffen Trumtrar Reviewed-by: Ahmad Fatoum --- drivers/mci/arasan-sdhci.c | 62 +++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 59 insertions(+), 3 deletions(-) diff --git a/drivers/mci/arasan-sdhci.c b/drivers/mci/arasan-sdhci.c index 4111b3321a..c8b5a84060 100644 --- a/drivers/mci/arasan-sdhci.c +++ b/drivers/mci/arasan-sdhci.c @@ -128,6 +128,46 @@ static int arasan_sdhci_reset(struct arasan_sdhci_host *host, u8 mask) return 0; } +static void arasan_zynqmp_dll_reset(struct arasan_sdhci_host *host, u32 deviceid) +{ + u16 clk; + + clk = sdhci_read16(&host->sdhci, SDHCI_CLOCK_CONTROL); + clk &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN); + sdhci_write16(&host->sdhci, SDHCI_CLOCK_CONTROL, clk); + + /* Issue DLL Reset */ + zynqmp_pm_sd_dll_reset(deviceid, PM_DLL_RESET_PULSE); + + clk = sdhci_read16(&host->sdhci, SDHCI_CLOCK_CONTROL); + + sdhci_enable_clk(&host->sdhci, clk); +} + +static int arasan_zynqmp_execute_tuning(struct mci_host *mci, u32 opcode) +{ + struct arasan_sdhci_host *host = to_arasan_sdhci_host(mci); + struct clk_hw *hw = &host->clk_data.sdcardclk_hw; + const char *clk_name = clk_hw_get_name(hw); + u32 device_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 : + NODE_SD_1; + int err; + + /* ZynqMP SD controller does not perform auto tuning in DDR50 mode */ + if (mci->timing == MMC_TIMING_UHS_DDR50) + return 0; + + arasan_zynqmp_dll_reset(host, device_id); + + err = sdhci_execute_tuning(&host->sdhci, opcode); + if (err) + return err; + + arasan_zynqmp_dll_reset(host, device_id); + + return 0; +} + static int arasan_sdhci_init(struct mci_host *mci, struct device *dev) { struct arasan_sdhci_host *host = to_arasan_sdhci_host(mci); @@ -228,8 +268,9 @@ static int arasan_sdhci_send_cmd(struct mci_host *mci, struct mci_cmd *cmd, &command, &xfer); sdhci_write8(&host->sdhci, SDHCI_TIMEOUT_CONTROL, TIMEOUT_VAL); - if (data) { + if (xfer) sdhci_write16(&host->sdhci, SDHCI_TRANSFER_MODE, xfer); + if (data) { sdhci_write16(&host->sdhci, SDHCI_BLOCK_SIZE, SDHCI_DMA_BOUNDARY_512K | SDHCI_TRANSFER_BLOCK_SIZE(data->blocksize)); sdhci_write16(&host->sdhci, SDHCI_BLOCK_COUNT, data->blocks); @@ -237,6 +278,10 @@ static int arasan_sdhci_send_cmd(struct mci_host *mci, struct mci_cmd *cmd, sdhci_write32(&host->sdhci, SDHCI_ARGUMENT, cmd->cmdarg); sdhci_write16(&host->sdhci, SDHCI_COMMAND, command); + /* CMD19/21 generate _only_ Buffer Read Ready interrupt */ + if (cmd->cmdidx == MMC_SEND_TUNING_BLOCK || cmd->cmdidx == MMC_SEND_TUNING_BLOCK_HS200) + mask = SDHCI_INT_DATA_AVAIL; + ret = sdhci_wait_for_done(&host->sdhci, mask); if (ret) goto error; @@ -701,8 +746,11 @@ static int arasan_sdhci_probe(struct device *dev) if (of_property_read_bool(np, "no-1-8-v")) arasan_sdhci->quirks |= SDHCI_ARASAN_QUIRK_NO_1_8_V; - if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) + if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) { + if (IS_ENABLED(CONFIG_MCI_TUNING)) + mci->execute_tuning = arasan_zynqmp_execute_tuning; arasan_sdhci->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN; + } arasan_sdhci->sdhci.base = IOMEM(iores->start); arasan_sdhci->sdhci.mci = mci; @@ -713,7 +761,15 @@ static int arasan_sdhci_probe(struct device *dev) mci->card_write_protected = arasan_sdhci_card_write_protected; mci->hw_dev = dev; - mci->f_max = clk_get_rate(clk_xin); + /* + * clk_rates on ZynqMP are rounded wrong. For HS200 clk_get_rate retunrs + * 199999998 instead of 200000000 + */ + if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) + mci->f_max = 200000000; + else + mci->f_max = clk_get_rate(clk_xin); + mci->f_min = 50000000 / 256; arasan_sdhci_register_sdclk(&arasan_sdhci->clk_data, clk_xin, dev); -- 2.43.2