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From: Sascha Hauer <s.hauer@pengutronix.de>
To: Barebox List <barebox@lists.infradead.org>
Subject: [PATCH 15/16] pci: pcie-designware: iterate over windows
Date: Tue, 26 Mar 2024 11:07:45 +0100	[thread overview]
Message-ID: <20240326100746.471532-16-s.hauer@pengutronix.de> (raw)
In-Reply-To: <20240326100746.471532-1-s.hauer@pengutronix.de>

The ranges property has already been parsed in pci_controller_init(), so
instead of iterating over the ranges again, use the result stored in
the resource_entry list to initialize the controller base addresses.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/pci/pcie-designware-host.c | 27 +++++++++++++--------------
 1 file changed, 13 insertions(+), 14 deletions(-)

diff --git a/drivers/pci/pcie-designware-host.c b/drivers/pci/pcie-designware-host.c
index 87842bf4ee..cd1d9433aa 100644
--- a/drivers/pci/pcie-designware-host.c
+++ b/drivers/pci/pcie-designware-host.c
@@ -72,9 +72,9 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	struct device *dev = pci->dev;
 	struct device_node *np = dev->of_node;
-	struct of_pci_range range;
 	struct of_pci_range_parser parser;
 	struct resource *cfg_res;
+	struct resource_entry *window;
 	int ret;
 
 	pp->pci.parent = dev;
@@ -96,19 +96,18 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
 		return -EINVAL;
 	}
 
-	/* Get the I/O and memory ranges from DT */
-	for_each_of_pci_range(&parser, &range) {
-		unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
-
-		if (restype == IORESOURCE_IO) {
-			pp->io_size = range.size;
-			pp->io_bus_addr = range.pci_addr;
-			pp->io_base = range.cpu_addr;
-		}
-		if (restype == IORESOURCE_MEM) {
-			pp->mem_size = range.size;
-			pp->mem_bus_addr = range.pci_addr;
-			pp->mem_base = range.cpu_addr;
+	resource_list_for_each_entry(window, &pp->pci.windows) {
+		switch (resource_type(window->res)) {
+		case IORESOURCE_IO:
+			pp->io_size = resource_size(window->res);
+			pp->io_bus_addr = window->res->start - window->offset;
+			pp->io_base = window->res->start;
+			break;
+		case IORESOURCE_MEM:
+			pp->mem_size = resource_size(window->res);
+			pp->mem_bus_addr = window->res->start - window->offset;
+			pp->mem_base = window->res->start;
+			break;
 		}
 	}
 
-- 
2.39.2




  parent reply	other threads:[~2024-03-26 10:36 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-26 10:07 [PATCH 00/16] PCI: support non 1:1 mappings Sascha Hauer
2024-03-26 10:07 ` [PATCH 01/16] net: phy: realtek: add phy for RTL8168 internal phy Sascha Hauer
2024-03-26 10:07 ` [PATCH 02/16] pci: add 'self' member to struct pci_bus Sascha Hauer
2024-03-26 10:07 ` [PATCH 03/16] pci: rename parent_bus to parent Sascha Hauer
2024-03-26 10:07 ` [PATCH 04/16] add support for resource lists Sascha Hauer
2024-03-26 10:07 ` [PATCH 05/16] pci: pcie-designware: remove unused variable Sascha Hauer
2024-03-26 10:07 ` [PATCH 06/16] pci: dwc: Drop support for config space in 'ranges' Sascha Hauer
2024-03-26 10:07 ` [PATCH 07/16] pci: add pci_controller_init() Sascha Hauer
2024-03-26 10:07 ` [PATCH 08/16] pci: support non 1:1 mappings Sascha Hauer
2024-03-26 10:07 ` [PATCH 09/16] pci: pcie-designware: Speed up waiting for link Sascha Hauer
2024-03-26 10:07 ` [PATCH 10/16] pci: pcie-dw-rockchip: wait " Sascha Hauer
2024-03-26 10:07 ` [PATCH 11/16] pci: drop resources from struct pci_bus Sascha Hauer
2024-03-26 10:07 ` [PATCH 12/16] pci: add of_pci_bridge_init() Sascha Hauer
2024-04-04  6:18   ` [PATCH v2] " Sascha Hauer
2024-03-26 10:07 ` [PATCH 13/16] pci: pcie-designware: drop duplicate resource assigning Sascha Hauer
2024-03-26 10:07 ` [PATCH 14/16] pci: pcie-designware: remove dra7xx quirks Sascha Hauer
2024-03-26 10:07 ` Sascha Hauer [this message]
2024-03-26 10:07 ` [PATCH 16/16] ARM: dts: rk3588-rock-5b: remove pci ranges quirks Sascha Hauer
2024-04-02  8:39 ` [PATCH 00/16] PCI: support non 1:1 mappings Sascha Hauer

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