[PATCH master 1/3] soc: sifive: l2_cache: fix 32-bit compilation

[PATCH master 1/3] soc: sifive: l2_cache: fix 32-bit compilation

[Ahmad Fatoum]

The StarFive SoCs are 64-bit, but the L2 cache driver could be
compile-tested on 32-bit as well. Currently, this would fail, because
writeq isn't defined. Fix this by emulating it using a lo-hi write.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 drivers/soc/sifive/sifive_l2_cache.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c
index aab21f9f50e6..c404143974fc 100644
--- a/drivers/soc/sifive/sifive_l2_cache.c
+++ b/drivers/soc/sifive/sifive_l2_cache.c
@@ -9,6 +9,7 @@
 #define pr_fmt(fmt) "sifive-l2: " fmt
 
 #include <io.h>
+#include <io-64-nonatomic-lo-hi.h>
 #include <linux/printk.h>
 #include <stdio.h>
 #include <driver.h>
-- 
2.39.2

[PATCH master 2/3] RISC-V: riscvemu: build overlay as DTSO

[Ahmad Fatoum]

Overlay files shouldn't include the device tree snippets from
CONFIG_EXTERNAL_DTS_FRAGMENTS, which is avoided by using the dtbo rule
instead of the dtb rule that we were using before.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/riscv/boards/riscvemu/Makefile                           | 2 +-
 arch/riscv/boards/riscvemu/board.c                            | 4 ++--
 .../riscvemu/{overlay-of-sram.dts => riscvemu-sram.dtso}      | 0
 3 files changed, 3 insertions(+), 3 deletions(-)
 rename arch/riscv/boards/riscvemu/{overlay-of-sram.dts => riscvemu-sram.dtso} (100%)

diff --git a/arch/riscv/boards/riscvemu/Makefile b/arch/riscv/boards/riscvemu/Makefile
index ec7e89479e77..baada2136ee2 100644
--- a/arch/riscv/boards/riscvemu/Makefile
+++ b/arch/riscv/boards/riscvemu/Makefile
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-only
 
 obj-y += board.o
-obj-y += overlay-of-sram.dtb.o
+obj-y += riscvemu-sram.dtbo.o
 bbenv-$(CONFIG_CMD_TUTORIAL) += defaultenv-riscvemu
 
 clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts *.dtb.z
diff --git a/arch/riscv/boards/riscvemu/board.c b/arch/riscv/boards/riscvemu/board.c
index c1d008ab5d32..afd6608ac522 100644
--- a/arch/riscv/boards/riscvemu/board.c
+++ b/arch/riscv/boards/riscvemu/board.c
@@ -33,7 +33,7 @@ static void __noreturn riscvemu_restart(struct restart_handler *rst)
 	priv->restart(riscv_hartid(), barebox_riscv_boot_dtb());
 }
 
-extern char __dtb_overlay_of_sram_start[];
+extern char __dtbo_riscvemu_sram_start[];
 
 static int riscvemu_probe(struct device *dev)
 {
@@ -42,7 +42,7 @@ static int riscvemu_probe(struct device *dev)
 	struct riscvemu_priv *priv;
 	u64 start;
 
-	overlay = of_unflatten_dtb(__dtb_overlay_of_sram_start, INT_MAX);
+	overlay = of_unflatten_dtb(__dtbo_riscvemu_sram_start, INT_MAX);
 	of_overlay_apply_tree(dev->of_node, overlay);
 	/* of_probe() will happen later at of_populate_initcall */
 
diff --git a/arch/riscv/boards/riscvemu/overlay-of-sram.dts b/arch/riscv/boards/riscvemu/riscvemu-sram.dtso
similarity index 100%
rename from arch/riscv/boards/riscvemu/overlay-of-sram.dts
rename to arch/riscv/boards/riscvemu/riscvemu-sram.dtso
-- 
2.39.2

[PATCH master 3/3] treewide: replace references to barebox.org/jsbarebox with demo

[Ahmad Fatoum]

barebox.org/jsbarebox is now a HTTP 301 (Moved permanently) redirect to
barebox.org/demo. Change all references we have to the old URL.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 Documentation/boards/riscv.rst           | 2 +-
 Documentation/devel/project-ideas.rst    | 4 ++--
 README.md                                | 2 +-
 test/riscv/tinyemu@rv64i_defconfig.yaml  | 2 +-
 test/riscv/tinyemu@virt32_defconfig.yaml | 2 +-
 5 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/Documentation/boards/riscv.rst b/Documentation/boards/riscv.rst
index 92f663cfb9e6..990bd16a640d 100644
--- a/Documentation/boards/riscv.rst
+++ b/Documentation/boards/riscv.rst
@@ -58,7 +58,7 @@ To activate add::
 
 into the config file.
 
-See https://barebox.org/jsbarebox/?graphic=1 for a live example.
+See https://barebox.org/demo/?graphic=1 for a live example.
 
 BeagleV
 -------
diff --git a/Documentation/devel/project-ideas.rst b/Documentation/devel/project-ideas.rst
index d9957e409178..da146c3e520e 100644
--- a/Documentation/devel/project-ideas.rst
+++ b/Documentation/devel/project-ideas.rst
@@ -185,13 +185,13 @@ barebox to a new board, for new users who are only interested in
 trying it out: The browser runs Tinyemu, a virtual machine in which
 barebox executes as if on real hardware and the user can manipulate the
 (virtual) hardware from the barebox shell and learn about barebox
-conveniences: barebox.org/jsbarebox/
+conveniences: barebox.org/demo/
 
 The project is about streamlining this demo: CPU usage currently is
 quite high and teaching barebox to idle the CPU (as we do on sandbox)
 didn't help. This needs to be analyzed with the profiling tools
 provided with modern browsers. The remainder of the project can then
-focus on improving the jsbarebox tutorial. e.g. by adding new
+focus on improving the tutorial inside the demo. e.g. by adding new
 peripherals to the virtual machine.
 
 Expected outcome is snappier and less CPU-intensive barebox demo.
diff --git a/README.md b/README.md
index a668f8aee224..acb4a28a8b16 100644
--- a/README.md
+++ b/README.md
@@ -6,7 +6,7 @@ that integrates DOOM with the available barebox frameworks for framebuffer,
 input, file system and so on ... etc. This allows it to run everywhere
 where barebox is running, be it on a x86 laptop under UEFI, on industrial
 machinery or even a RISC-V emulator compiled to WebAssembly.
-Head over to [barebox.org](https://barebox.org/jsbarebox/?graphic=1) to try
+Head over to [barebox.org](https://barebox.org/demo/?graphic=1) to try
 the latter out.
 
 As barebox often functions as bare metal hardware bring up kit, it can
diff --git a/test/riscv/tinyemu@rv64i_defconfig.yaml b/test/riscv/tinyemu@rv64i_defconfig.yaml
index e9624160ef0a..cb22afc68528 100644
--- a/test/riscv/tinyemu@rv64i_defconfig.yaml
+++ b/test/riscv/tinyemu@rv64i_defconfig.yaml
@@ -13,7 +13,7 @@ targets:
       - virtio-mmio
     runner:
       download:
-        bbl64.bin: https://barebox.org/jsbarebox/bbl64.bin
+        bbl64.bin: https://barebox.org/demo/bbl64.bin
 images:
   barebox-dt-2nd.img: !template "$LG_BUILDDIR/images/barebox-dt-2nd.img"
 tools:
diff --git a/test/riscv/tinyemu@virt32_defconfig.yaml b/test/riscv/tinyemu@virt32_defconfig.yaml
index 1102f36aca2b..bc6eada37684 100644
--- a/test/riscv/tinyemu@virt32_defconfig.yaml
+++ b/test/riscv/tinyemu@virt32_defconfig.yaml
@@ -13,7 +13,7 @@ targets:
       - virtio-mmio
     runner:
       download:
-        bbl32.bin: https://barebox.org/jsbarebox/bbl32.bin
+        bbl32.bin: https://barebox.org/demo/bbl32.bin
 images:
   barebox-dt-2nd.img: !template "$LG_BUILDDIR/images/barebox-dt-2nd.img"
 tools:
-- 
2.39.2

Re: [PATCH master 1/3] soc: sifive: l2_cache: fix 32-bit compilation

[Sascha Hauer]

On Tue, 02 Apr 2024 15:44:59 +0200, Ahmad Fatoum wrote:
> The StarFive SoCs are 64-bit, but the L2 cache driver could be
> compile-tested on 32-bit as well. Currently, this would fail, because
> writeq isn't defined. Fix this by emulating it using a lo-hi write.
> 
> 

Applied, thanks!

[1/3] soc: sifive: l2_cache: fix 32-bit compilation
      https://git.pengutronix.de/cgit/barebox/commit/?id=046ceb972493 (link may not be stable)
[2/3] RISC-V: riscvemu: build overlay as DTSO
      https://git.pengutronix.de/cgit/barebox/commit/?id=d75ee46bea16 (link may not be stable)
[3/3] treewide: replace references to barebox.org/jsbarebox with demo
      https://git.pengutronix.de/cgit/barebox/commit/?id=c0dde74b1c9a (link may not be stable)

Best regards,
-- 
Sascha Hauer <s.hauer@pengutronix.de>