[PATCH 0/2] net: designware-imx: fix eqos in RMII on i.MX93

[PATCH 0/2] net: designware-imx: fix eqos in RMII on i.MX93

[Steffen Trumtrar]

This series fixes the eqos ethernet on i.MX93 SoCs when used in RMII
mode.

The first patch is an adaptation of the linux patch

    commit b536f32b5b034f592df0f0ba129ad59fa0f3e532
   
      net: stmmac: dwmac-imx: use platform specific reset for imx93 SoCs
      
      The patch addresses an issue with the reset logic on the i.MX93 SoC, which
      requires configuration of the correct interface speed under RMII mode to
      complete the reset. The patch implements a fix_soc_reset function and uses
      it specifically for the i.MX93 SoCs. 

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
Steffen Trumtrar (2):
      net: designware-imx: add fix_reset callback
      net: designware-imx: i.MX93: set TX_CLK in RMII mode

 drivers/net/designware_eqos.c |  3 +++
 drivers/net/designware_eqos.h |  1 +
 drivers/net/designware_imx.c  | 33 +++++++++++++++++++++++++++++++++
 3 files changed, 37 insertions(+)
---
base-commit: c6d055d224e0b3a0aff638a05a367c30d2d0310e
change-id: 20240417-v2024-03-0-topic-imx93-designware-imx-825d80e68fb7

Best regards,
-- 
Steffen Trumtrar <s.trumtrar@pengutronix.de>

[PATCH 1/2] net: designware-imx: add fix_reset callback

[Steffen Trumtrar]

The i.MX93 needs to set the RMII speed to successfully reset. Add a
callback that does this inspired by the linux patch:

    net: stmmac: dwmac-imx: use platform specific reset for imx93 SoCs

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
 drivers/net/designware_eqos.c |  3 +++
 drivers/net/designware_eqos.h |  1 +
 drivers/net/designware_imx.c  | 21 +++++++++++++++++++++
 3 files changed, 25 insertions(+)

diff --git a/drivers/net/designware_eqos.c b/drivers/net/designware_eqos.c
index ccce51b6af..4a97cbb75e 100644
--- a/drivers/net/designware_eqos.c
+++ b/drivers/net/designware_eqos.c
@@ -431,6 +431,9 @@ static int eqos_start(struct eth_device *edev)
 	 */
 	setbits_le32(&eqos->dma_regs->mode, EQOS_DMA_MODE_SWR);
 
+	if (eqos->ops->fix_reset)
+		eqos->ops->fix_reset(eqos, &eqos->mac_regs->config);
+
 	ret = readl_poll_timeout(&eqos->dma_regs->mode, mode_set,
 				 !(mode_set & EQOS_DMA_MODE_SWR),
 				 100 * USEC_PER_MSEC);
diff --git a/drivers/net/designware_eqos.h b/drivers/net/designware_eqos.h
index 951565e8f9..9f2fc2fe6d 100644
--- a/drivers/net/designware_eqos.h
+++ b/drivers/net/designware_eqos.h
@@ -14,6 +14,7 @@ struct eqos_ops {
 	int (*get_ethaddr)(struct eth_device *dev, unsigned char *mac);
 	int (*set_ethaddr)(struct eth_device *edev, const unsigned char *mac);
 	void (*adjust_link)(struct eth_device *edev);
+	void (*fix_reset)(struct eqos *, unsigned int *reg);
 	unsigned long (*get_csr_clk_rate)(struct eqos *);
 
 	bool enh_desc;
diff --git a/drivers/net/designware_imx.c b/drivers/net/designware_imx.c
index c281d3b64b..ab60d98298 100644
--- a/drivers/net/designware_imx.c
+++ b/drivers/net/designware_imx.c
@@ -24,8 +24,11 @@
 #define MX93_GPR_ENET_QOS_INTF_SEL_RGMII	(0x1 << 1)
 #define MX93_GPR_ENET_QOS_CLK_GEN_EN		(0x1 << 0)
 
+#define RMII_RESET_SPEED			(0x3 << 14)
+
 struct eqos_imx_soc_data {
 	int (*set_interface_mode)(struct eqos *eqos);
+	void (*fix_soc_reset)(struct eqos *eqos, u32 *mac_regs);
 	bool mac_rgmii_txclk_auto_adj;
 };
 
@@ -82,6 +85,22 @@ static int eqos_set_txclk(struct eqos *eqos, int speed)
 	return ret;
 }
 
+static void eqos_fix_reset(struct eqos *eqos, u32 *reg)
+{
+	struct eqos_imx_priv *priv = eqos->priv;
+
+	if (priv->soc_data->fix_soc_reset)
+		priv->soc_data->fix_soc_reset(eqos, reg);
+}
+
+static void eqos_imx93_reset(struct eqos *eqos, u32 *mac_reg)
+{
+	if (eqos->interface == PHY_INTERFACE_MODE_RMII) {
+		udelay(200);
+		setbits_le32(mac_reg, RMII_RESET_SPEED);
+	}
+}
+
 static void eqos_adjust_link_imx(struct eth_device *edev)
 {
 	struct eqos *eqos = edev->priv;
@@ -184,6 +203,7 @@ static struct eqos_ops imx_ops = {
 	.set_ethaddr = eqos_set_ethaddr,
 	.adjust_link = eqos_adjust_link_imx,
 	.get_csr_clk_rate = eqos_get_csr_clk_rate_imx,
+	.fix_reset = eqos_fix_reset,
 
 	.clk_csr = EQOS_MDIO_ADDR_CR_250_300,
 	.config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
@@ -240,6 +260,7 @@ static void eqos_remove_imx(struct device *dev)
 
 static struct eqos_imx_soc_data imx93_soc_data = {
 	.set_interface_mode = eqos_imx93_set_interface_mode,
+	.fix_soc_reset = eqos_imx93_reset,
 	.mac_rgmii_txclk_auto_adj = true,
 };
 

-- 
2.43.2

[PATCH 2/2] net: designware-imx: i.MX93: set TX_CLK in RMII mode

[Steffen Trumtrar]

According to NXP AT14149 the TX_CLK direction must be set to output
when the ENET is used in RMII mode.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
 drivers/net/designware_imx.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/net/designware_imx.c b/drivers/net/designware_imx.c
index ab60d98298..2cc707ecac 100644
--- a/drivers/net/designware_imx.c
+++ b/drivers/net/designware_imx.c
@@ -26,6 +26,10 @@
 
 #define RMII_RESET_SPEED			(0x3 << 14)
 
+#define MX93_GPR_ENET_CLK_SEL_OFFSET		0x4
+#define MX93_ENET_CLK_ENET_QOS_TX_CLK_SEL_MASK	GENMASK(0, 0)
+#define MX93_ENET_CLK_ENET_QOS_TX_CLK_SEL	(0x1 << 0)
+
 struct eqos_imx_soc_data {
 	int (*set_interface_mode)(struct eqos *eqos);
 	void (*fix_soc_reset)(struct eqos *eqos, u32 *mac_regs);
@@ -155,6 +159,14 @@ static int eqos_imx93_set_interface_mode(struct eqos *eqos)
 		break;
 	case PHY_INTERFACE_MODE_RMII:
 		val = MX93_GPR_ENET_QOS_INTF_SEL_RMII;
+
+		/* According to NXP AN14149, the direction of the
+		 * TX_CLK must be set to output in RMII mode.
+		 */
+		regmap_update_bits(priv->intf_regmap,
+				   priv->intf_reg_off + MX93_GPR_ENET_CLK_SEL_OFFSET,
+				   MX93_ENET_CLK_ENET_QOS_TX_CLK_SEL_MASK,
+				   MX93_ENET_CLK_ENET_QOS_TX_CLK_SEL);
 		break;
 	case PHY_INTERFACE_MODE_RGMII:
 	case PHY_INTERFACE_MODE_RGMII_ID:

-- 
2.43.2

Re: [PATCH 2/2] net: designware-imx: i.MX93: set TX_CLK in RMII mode

[Sascha Hauer]

On Wed, Apr 17, 2024 at 11:11:26AM +0200, Steffen Trumtrar wrote:
> According to NXP AT14149 the TX_CLK direction must be set to output
> when the ENET is used in RMII mode.
> 
> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
> ---
>  drivers/net/designware_imx.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/drivers/net/designware_imx.c b/drivers/net/designware_imx.c
> index ab60d98298..2cc707ecac 100644
> --- a/drivers/net/designware_imx.c
> +++ b/drivers/net/designware_imx.c
> @@ -26,6 +26,10 @@
>  
>  #define RMII_RESET_SPEED			(0x3 << 14)
>  
> +#define MX93_GPR_ENET_CLK_SEL_OFFSET		0x4
> +#define MX93_ENET_CLK_ENET_QOS_TX_CLK_SEL_MASK	GENMASK(0, 0)
> +#define MX93_ENET_CLK_ENET_QOS_TX_CLK_SEL	(0x1 << 0)

No need to define an extra _MASK for single bit fields. Just use
MX93_ENET_CLK_ENET_QOS_TX_CLK_SEL instead.

> +
>  struct eqos_imx_soc_data {
>  	int (*set_interface_mode)(struct eqos *eqos);
>  	void (*fix_soc_reset)(struct eqos *eqos, u32 *mac_regs);
> @@ -155,6 +159,14 @@ static int eqos_imx93_set_interface_mode(struct eqos *eqos)
>  		break;
>  	case PHY_INTERFACE_MODE_RMII:
>  		val = MX93_GPR_ENET_QOS_INTF_SEL_RMII;
> +
> +		/* According to NXP AN14149, the direction of the
> +		 * TX_CLK must be set to output in RMII mode.
> +		 */
> +		regmap_update_bits(priv->intf_regmap,
> +				   priv->intf_reg_off + MX93_GPR_ENET_CLK_SEL_OFFSET,
> +				   MX93_ENET_CLK_ENET_QOS_TX_CLK_SEL_MASK,
> +				   MX93_ENET_CLK_ENET_QOS_TX_CLK_SEL);

I think this is ok for now as all in tree boards need this set, but what
about this comment to the corresponding kernel patch?

https://lore.kernel.org/all/f01d49cf-5955-405c-9c2b-05b0c7bb982c@armadeus.com/

Also according to the reference manual this bit is default 1 already,
how comes you have to adjust it?

Sascha

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