[PATCH 0/5] ARM: i.MX8MP: add nominal drive mode support

[PATCH 0/5] ARM: i.MX8MP: add nominal drive mode support

[Ahmad Fatoum]

Unlike the i.MX8MM and i.MX8MN SoCs added earlier, the early setup code
and device tree for the i.MX8MP configures some clocks at frequencies
that are only validated for overdrive mode, i.e. when VDD_SOC is 950 mV.

Boards may want to run their SoC at the lower voltage of 850 mV though
to reduce heat generation and power usage. For this to work, clock rates
need to adhere to the limits of the nominal drive mode.

This needs to be done across both barebox and Linux. This series handles
the barebox side and a separate series will follow for the kernel.

Ahmad Fatoum (5):
  ARM: i.MX8M: pass cpu_type parameter to __imx8m_early_clock_init
  ARM: i.MX8MP: configure PLL3 as 600MHz
  ARM: i.MX8MP: configure PLL3 as noc_io parent
  ARM: i.MX8MP: don't reparent GIC from BootROM default
  ARM: dts: i.MX8MP: Add optional nominal drive mode DTSI

 arch/arm/dts/imx8mp-nominal.dtsi  | 51 +++++++++++++++++++++++++++++++
 arch/arm/mach-imx/imx8m.c         | 42 +++++++++++++++++++------
 include/mach/imx/imx8m-ccm-regs.h |  1 +
 3 files changed, 84 insertions(+), 10 deletions(-)
 create mode 100644 arch/arm/dts/imx8mp-nominal.dtsi

-- 
2.39.2

[PATCH 1/5] ARM: i.MX8M: pass cpu_type parameter to __imx8m_early_clock_init

[Ahmad Fatoum]

We do some limited clock tree configuration in PBL and do the proper
configuration later in the barebox proper drivers.

The clock tree of the i.MX8MP is a bit different though than that of the
i.MX8MM and i.MX8MN and we'll want to add some more SoC-specific
configuration in the follow-up commit. Prepare for that by giving the
function a cpu_type parameter that can be checked.

Note that we can't use imx_cpu_type here, because it has not been set
yet.

No functional change intended.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/arm/mach-imx/imx8m.c | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-imx/imx8m.c b/arch/arm/mach-imx/imx8m.c
index 52e42ee9ef63..d798c52c6a6e 100644
--- a/arch/arm/mach-imx/imx8m.c
+++ b/arch/arm/mach-imx/imx8m.c
@@ -56,8 +56,9 @@ void imx8m_ccgr_clock_disable(int index)
 #define IMX8MM_CCM_ANALOG_SYS_PLL2_GEN_CTRL	0x104
 #define IMX8MM_CCM_ANALOG_SYS_PLL3_GEN_CTRL	0x114
 
-static void __imx8m_early_clock_init(unsigned long pll3_freq) /* and later */
+static void __imx8m_early_clock_init(int cpu_type)
 {
+	unsigned long pll3_freq;
 	void __iomem *ana = IOMEM(MX8M_ANATOP_BASE_ADDR);
 	void __iomem *ccm = IOMEM(MX8M_CCM_BASE_ADDR);
 	u32 val;
@@ -99,6 +100,11 @@ static void __imx8m_early_clock_init(unsigned long pll3_freq) /* and later */
 				   IMX8M_CCM_TARGET_ROOTn_MUX(3));
 	imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_GIC);
 
+	if (cpu_type == IMX_CPU_IMX8MN)
+		pll3_freq = 600000000UL;
+	else
+		pll3_freq = 750000000UL;
+
 	/* Configure SYS_PLL3 */
 	clk_pll1416x_early_set_rate(ana + IMX8MM_CCM_ANALOG_SYS_PLL3_GEN_CTRL,
 				    pll3_freq, 25000000UL);
@@ -126,17 +132,17 @@ static void __imx8m_early_clock_init(unsigned long pll3_freq) /* and later */
 
 void imx8mm_early_clock_init(void)
 {
-	__imx8m_early_clock_init(750000000UL);
+	__imx8m_early_clock_init(IMX_CPU_IMX8MM);
 }
 
 void imx8mn_early_clock_init(void)
 {
-	__imx8m_early_clock_init(600000000UL);
+	__imx8m_early_clock_init(IMX_CPU_IMX8MN);
 }
 
 void imx8mp_early_clock_init(void)
 {
-	__imx8m_early_clock_init(750000000UL);
+	__imx8m_early_clock_init(IMX_CPU_IMX8MP);
 }
 
 
-- 
2.39.2

[PATCH 2/5] ARM: i.MX8MP: configure PLL3 as 600MHz

[Ahmad Fatoum]

When running the i.MX8MP in nominal drive mode, a number of clocks are
validated only up to 600MHz: m7_core, audio_axi, vpu_bus, gpu_axi,
noc_io, vpu_g1.

Let's configure PLL3 as 600MHz to make it a suitable parent for these
clocks. The upstream Linux DTs don't yet use PLL3, but this aligns us
with U-Boot's boot-time configuration.

While at it, we also add a comment about how pll1 and pll2 are
configured.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/arm/mach-imx/imx8m.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/imx8m.c b/arch/arm/mach-imx/imx8m.c
index d798c52c6a6e..211b4f782199 100644
--- a/arch/arm/mach-imx/imx8m.c
+++ b/arch/arm/mach-imx/imx8m.c
@@ -77,6 +77,13 @@ static void __imx8m_early_clock_init(int cpu_type)
 
 	imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_DDR1);
 
+	/*
+	 * The gate is not exported to clk tree, so configure them here.
+	 * According to ANAMIX SPEC
+	 * sys pll1 fixed at 800MHz
+	 * sys pll2 fixed at 1GHz
+	 * Here we only enable the outputs.
+	 */
 	val = readl(ana + IMX8MM_CCM_ANALOG_SYS_PLL1_GEN_CTRL);
 	val |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
 		INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
@@ -100,7 +107,7 @@ static void __imx8m_early_clock_init(int cpu_type)
 				   IMX8M_CCM_TARGET_ROOTn_MUX(3));
 	imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_GIC);
 
-	if (cpu_type == IMX_CPU_IMX8MN)
+	if (cpu_type == IMX_CPU_IMX8MN || cpu_type == IMX_CPU_IMX8MP)
 		pll3_freq = 600000000UL;
 	else
 		pll3_freq = 750000000UL;
-- 
2.39.2

[PATCH 3/5] ARM: i.MX8MP: configure PLL3 as noc_io parent

[Ahmad Fatoum]

noc_io is clocked at 24MHz when exiting bootrom, which is a far cry
below the 600MHz it can run at in nominal drive mode.

This doesn't bother us much, because we reconfigure it to 800MHz later
on via assigned-clock-properties, but that frequency is only suitable
when running in overdrive mode (VDD_SOC = 950 mV).

Make switching to nominal mode easier by initializing NOC_IO to
the highest nominal frequency.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/arm/mach-imx/imx8m.c         | 7 +++++++
 include/mach/imx/imx8m-ccm-regs.h | 1 +
 2 files changed, 8 insertions(+)

diff --git a/arch/arm/mach-imx/imx8m.c b/arch/arm/mach-imx/imx8m.c
index 211b4f782199..56330cef500c 100644
--- a/arch/arm/mach-imx/imx8m.c
+++ b/arch/arm/mach-imx/imx8m.c
@@ -116,6 +116,13 @@ static void __imx8m_early_clock_init(int cpu_type)
 	clk_pll1416x_early_set_rate(ana + IMX8MM_CCM_ANALOG_SYS_PLL3_GEN_CTRL,
 				    pll3_freq, 25000000UL);
 
+	if (cpu_type == IMX_CPU_IMX8MP) {
+		/* 8MP ROM already set NOC to 800Mhz, only need to configure NOC_IO clk to 600Mhz */
+		imx8m_clock_set_target_val(IMX8M_NOC_IO_CLK_ROOT,
+					   IMX8M_CCM_TARGET_ROOTn_ENABLE |
+					   IMX8M_CCM_TARGET_ROOTn_MUX(2));
+	}
+
 	clrsetbits_le32(ccm + IMX8M_CCM_TARGET_ROOTn(IMX8M_ARM_A53_CLK_ROOT),
 			IMX8M_CCM_TARGET_ROOTn_MUX(7),
 			IMX8M_CCM_TARGET_ROOTn_MUX(2));
diff --git a/include/mach/imx/imx8m-ccm-regs.h b/include/mach/imx/imx8m-ccm-regs.h
index 29186eb8a7bc..035cd13ed694 100644
--- a/include/mach/imx/imx8m-ccm-regs.h
+++ b/include/mach/imx/imx8m-ccm-regs.h
@@ -22,6 +22,7 @@
  * Applications Processor Reference Manual
  */
 #define IMX8M_ARM_A53_CLK_ROOT		0
+#define IMX8M_NOC_IO_CLK_ROOT           27
 #define IMX8M_DRAM_SEL_CFG		48
 #define IMX8M_DRAM_ALT_CLK_ROOT		64
 #define IMX8M_DRAM_APB_CLK_ROOT		65
-- 
2.39.2

[PATCH 4/5] ARM: i.MX8MP: don't reparent GIC from BootROM default

[Ahmad Fatoum]

On i.MX8MP, GIC can run at up to 400 MHz in nominal drive mode and up
to 500 MHz in overdrive mode. We currently configure unconditionally
to 100 MHz on i.MX8MP.

The BootROM default is running it on 400 MHz, which works well for us on
the i.MX8MP, so skip the GIC configuration on the i.MX8MP.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/arm/mach-imx/imx8m.c | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-imx/imx8m.c b/arch/arm/mach-imx/imx8m.c
index 56330cef500c..0966f7fdf076 100644
--- a/arch/arm/mach-imx/imx8m.c
+++ b/arch/arm/mach-imx/imx8m.c
@@ -100,13 +100,6 @@ static void __imx8m_early_clock_init(int cpu_type)
 		INTPLL_DIV20_CLKE_MASK;
 	writel(val, ana + IMX8MM_CCM_ANALOG_SYS_PLL2_GEN_CTRL);
 
-	/* config GIC to sys_pll2_100m */
-	imx8m_ccgr_clock_disable(IMX8M_CCM_CCGR_GIC);
-	imx8m_clock_set_target_val(IMX8M_GIC_CLK_ROOT,
-				   IMX8M_CCM_TARGET_ROOTn_ENABLE |
-				   IMX8M_CCM_TARGET_ROOTn_MUX(3));
-	imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_GIC);
-
 	if (cpu_type == IMX_CPU_IMX8MN || cpu_type == IMX_CPU_IMX8MP)
 		pll3_freq = 600000000UL;
 	else
@@ -118,11 +111,20 @@ static void __imx8m_early_clock_init(int cpu_type)
 
 	if (cpu_type == IMX_CPU_IMX8MP) {
 		/* 8MP ROM already set NOC to 800Mhz, only need to configure NOC_IO clk to 600Mhz */
+		/* 8MP ROM already set GIC to 400Mhz, system_pll1_800m with div = 2 */
 		imx8m_clock_set_target_val(IMX8M_NOC_IO_CLK_ROOT,
 					   IMX8M_CCM_TARGET_ROOTn_ENABLE |
 					   IMX8M_CCM_TARGET_ROOTn_MUX(2));
+	} else {
+		/* config GIC to sys_pll2_100m */
+		imx8m_ccgr_clock_disable(IMX8M_CCM_CCGR_GIC);
+		imx8m_clock_set_target_val(IMX8M_GIC_CLK_ROOT,
+					   IMX8M_CCM_TARGET_ROOTn_ENABLE |
+					   IMX8M_CCM_TARGET_ROOTn_MUX(3));
+		imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_GIC);
 	}
 
+
 	clrsetbits_le32(ccm + IMX8M_CCM_TARGET_ROOTn(IMX8M_ARM_A53_CLK_ROOT),
 			IMX8M_CCM_TARGET_ROOTn_MUX(7),
 			IMX8M_CCM_TARGET_ROOTn_MUX(2));
-- 
2.39.2

Re: [PATCH 4/5] ARM: i.MX8MP: don't reparent GIC from BootROM default

[Lucas Stach]

Am Freitag, dem 19.04.2024 um 08:13 +0200 schrieb Ahmad Fatoum:
> On i.MX8MP, GIC can run at up to 400 MHz in nominal drive mode and up
> to 500 MHz in overdrive mode. We currently configure unconditionally
> to 100 MHz on i.MX8MP.
> 
> The BootROM default is running it on 400 MHz, which works well for us on
> the i.MX8MP, so skip the GIC configuration on the i.MX8MP.
> 
> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
>  arch/arm/mach-imx/imx8m.c | 16 +++++++++-------
>  1 file changed, 9 insertions(+), 7 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/imx8m.c b/arch/arm/mach-imx/imx8m.c
> index 56330cef500c..0966f7fdf076 100644
> --- a/arch/arm/mach-imx/imx8m.c
> +++ b/arch/arm/mach-imx/imx8m.c
> @@ -100,13 +100,6 @@ static void __imx8m_early_clock_init(int cpu_type)
>  		INTPLL_DIV20_CLKE_MASK;
>  	writel(val, ana + IMX8MM_CCM_ANALOG_SYS_PLL2_GEN_CTRL);
>  
> -	/* config GIC to sys_pll2_100m */
> -	imx8m_ccgr_clock_disable(IMX8M_CCM_CCGR_GIC);
> -	imx8m_clock_set_target_val(IMX8M_GIC_CLK_ROOT,
> -				   IMX8M_CCM_TARGET_ROOTn_ENABLE |
> -				   IMX8M_CCM_TARGET_ROOTn_MUX(3));
> -	imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_GIC);
> -
>  	if (cpu_type == IMX_CPU_IMX8MN || cpu_type == IMX_CPU_IMX8MP)
>  		pll3_freq = 600000000UL;
>  	else
> @@ -118,11 +111,20 @@ static void __imx8m_early_clock_init(int cpu_type)
>  
>  	if (cpu_type == IMX_CPU_IMX8MP) {
>  		/* 8MP ROM already set NOC to 800Mhz, only need to configure NOC_IO clk to 600Mhz */
> +		/* 8MP ROM already set GIC to 400Mhz, system_pll1_800m with div = 2 */

This comment change looks odd. Now it doesn't explain anymore what's
done here and why, but rather explains why the else path isn't executed
on the 8MP.
>  		imx8m_clock_set_target_val(IMX8M_NOC_IO_CLK_ROOT,
>  					   IMX8M_CCM_TARGET_ROOTn_ENABLE |
>  					   IMX8M_CCM_TARGET_ROOTn_MUX(2));
> +	} else {

Maybe move this into a separate condition != IMX_CPU_IMX8MP and move
the comment above here? Leaving the comment about NOC_IO clocks
untouched?

> +		/* config GIC to sys_pll2_100m */
> +		imx8m_ccgr_clock_disable(IMX8M_CCM_CCGR_GIC);
> +		imx8m_clock_set_target_val(IMX8M_GIC_CLK_ROOT,
> +					   IMX8M_CCM_TARGET_ROOTn_ENABLE |
> +					   IMX8M_CCM_TARGET_ROOTn_MUX(3));
> +		imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_GIC);
>  	}
>  
> +
>  	clrsetbits_le32(ccm + IMX8M_CCM_TARGET_ROOTn(IMX8M_ARM_A53_CLK_ROOT),
>  			IMX8M_CCM_TARGET_ROOTn_MUX(7),
>  			IMX8M_CCM_TARGET_ROOTn_MUX(2));

[PATCH 5/5] ARM: dts: i.MX8MP: Add optional nominal drive mode DTSI

[Ahmad Fatoum]

Unlike the i.MX8MM and i.MX8MN SoCs added earlier, the device tree for
the i.MX8MP configures some clocks at frequencies that are only
validated for overdrive mode, i.e. when VDD_SOC is 950 mV.

Boards may want to run their SoC at the lower voltage of 850 mV though
to reduce heat generation and power usage. For this to work, clock rates
need to adhere to the limits of the nominal drive mode.

Add an optional DTSI file which can be included by various boards to run
in this mode.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/arm/dts/imx8mp-nominal.dtsi | 51 ++++++++++++++++++++++++++++++++
 1 file changed, 51 insertions(+)
 create mode 100644 arch/arm/dts/imx8mp-nominal.dtsi

diff --git a/arch/arm/dts/imx8mp-nominal.dtsi b/arch/arm/dts/imx8mp-nominal.dtsi
new file mode 100644
index 000000000000..a9f46503f656
--- /dev/null
+++ b/arch/arm/dts/imx8mp-nominal.dtsi
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+&clk {
+	assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
+			  <&clk IMX8MP_CLK_A53_CORE>,
+			  <&clk IMX8MP_SYS_PLL3>,
+			  <&clk IMX8MP_CLK_NOC>,
+			  <&clk IMX8MP_CLK_NOC_IO>,
+			  <&clk IMX8MP_CLK_GIC>;
+	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
+				 <&clk IMX8MP_ARM_PLL_OUT>,
+				 <0>,
+				 <&clk IMX8MP_SYS_PLL1_800M>,
+				 <&clk IMX8MP_SYS_PLL3_OUT>,
+				 <&clk IMX8MP_SYS_PLL1_800M>;
+	assigned-clock-rates = <0>, <0>,
+			       <600000000>,
+			       <800000000>,
+			       <600000000>,
+			       <400000000>;
+};
+
+&pgc_hsiomix {
+	assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
+	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
+	assigned-clock-rates = <400000000>;
+};
+
+&pgc_gpumix {
+	assigned-clocks = <&clk IMX8MP_GPU_PLL>,
+			  <&clk IMX8MP_CLK_GPU_AXI>,
+			  <&clk IMX8MP_CLK_GPU_AHB>;
+	assigned-clock-parents = <0>,
+				 <&clk IMX8MP_GPU_PLL_OUT>,
+				 <&clk IMX8MP_GPU_PLL_OUT>;
+	assigned-clock-rates = <600000000>, <600000000>, <300000000>;
+};
+
+&media_blk_ctrl {
+	assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
+			  <&clk IMX8MP_CLK_MEDIA_APB>,
+			  <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
+			  <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,
+			  <&clk IMX8MP_VIDEO_PLL1>;
+	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
+				 <&clk IMX8MP_SYS_PLL1_800M>,
+				 <&clk IMX8MP_VIDEO_PLL1_OUT>,
+				 <&clk IMX8MP_VIDEO_PLL1_OUT>;
+	assigned-clock-rates = <400000000>, <200000000>,
+			       <0>, <0>, <1039500000>;
+};
-- 
2.39.2

Re: [PATCH 5/5] ARM: dts: i.MX8MP: Add optional nominal drive mode DTSI

[Lucas Stach]

Am Freitag, dem 19.04.2024 um 08:13 +0200 schrieb Ahmad Fatoum:
> Unlike the i.MX8MM and i.MX8MN SoCs added earlier, the device tree for
> the i.MX8MP configures some clocks at frequencies that are only
> validated for overdrive mode, i.e. when VDD_SOC is 950 mV.
> 
> Boards may want to run their SoC at the lower voltage of 850 mV though
> to reduce heat generation and power usage. For this to work, clock rates
> need to adhere to the limits of the nominal drive mode.
> 
> Add an optional DTSI file which can be included by various boards to run
> in this mode.
> 
> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
>  arch/arm/dts/imx8mp-nominal.dtsi | 51 ++++++++++++++++++++++++++++++++
>  1 file changed, 51 insertions(+)
>  create mode 100644 arch/arm/dts/imx8mp-nominal.dtsi
> 
> diff --git a/arch/arm/dts/imx8mp-nominal.dtsi b/arch/arm/dts/imx8mp-nominal.dtsi
> new file mode 100644
> index 000000000000..a9f46503f656
> --- /dev/null
> +++ b/arch/arm/dts/imx8mp-nominal.dtsi
> @@ -0,0 +1,51 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +
> +&clk {
> +	assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
> +			  <&clk IMX8MP_CLK_A53_CORE>,
> +			  <&clk IMX8MP_SYS_PLL3>,
> +			  <&clk IMX8MP_CLK_NOC>,
> +			  <&clk IMX8MP_CLK_NOC_IO>,
> +			  <&clk IMX8MP_CLK_GIC>;
> +	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
> +				 <&clk IMX8MP_ARM_PLL_OUT>,
> +				 <0>,
> +				 <&clk IMX8MP_SYS_PLL1_800M>,
> +				 <&clk IMX8MP_SYS_PLL3_OUT>,
> +				 <&clk IMX8MP_SYS_PLL1_800M>;
> +	assigned-clock-rates = <0>, <0>,
> +			       <600000000>,
> +			       <800000000>,
> +			       <600000000>,
> +			       <400000000>;
> +};
> +
> +&pgc_hsiomix {
> +	assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
> +	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
> +	assigned-clock-rates = <400000000>;
> +};
> +
> +&pgc_gpumix {
> +	assigned-clocks = <&clk IMX8MP_GPU_PLL>,
> +			  <&clk IMX8MP_CLK_GPU_AXI>,
> +			  <&clk IMX8MP_CLK_GPU_AHB>;
> +	assigned-clock-parents = <0>,
> +				 <&clk IMX8MP_GPU_PLL_OUT>,
> +				 <&clk IMX8MP_GPU_PLL_OUT>;
> +	assigned-clock-rates = <600000000>, <600000000>, <300000000>;

Use SYS_PLL3 as the parent clock, instead of GPU PLL.

> +};
> +
> +&media_blk_ctrl {
> +	assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
> +			  <&clk IMX8MP_CLK_MEDIA_APB>,
> +			  <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
> +			  <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,
> +			  <&clk IMX8MP_VIDEO_PLL1>;
> +	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
> +				 <&clk IMX8MP_SYS_PLL1_800M>,
> +				 <&clk IMX8MP_VIDEO_PLL1_OUT>,
> +				 <&clk IMX8MP_VIDEO_PLL1_OUT>;
> +	assigned-clock-rates = <400000000>, <200000000>,
> +			       <0>, <0>, <1039500000>;
> +};