* [PATCH 1/2] ARM: aarch64: fix scr_el3 register setup @ 2024-04-30 11:29 Marco Felsch 2024-04-30 11:29 ` [PATCH 2/2] ARM: i.MX8M: add support to handle ROM SError ERR050350 Marco Felsch 2024-04-30 21:10 ` [PATCH 1/2] ARM: aarch64: fix scr_el3 register setup Marco Felsch 0 siblings, 2 replies; 6+ messages in thread From: Marco Felsch @ 2024-04-30 11:29 UTC (permalink / raw) To: barebox The current code moved '1' as immediate into x0 and does OR with BIT(10). This doesn't look right since it will set the scr_el3 to 0. Instead read the scr_el3 and OR the interessting bits to fix this. The interessting bits are taken from the current U-Boot implementation. Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> --- arch/arm/cpu/lowlevel_64.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/lowlevel_64.S b/arch/arm/cpu/lowlevel_64.S index ed00c8c47057..1f5a0b73f8b3 100644 --- a/arch/arm/cpu/lowlevel_64.S +++ b/arch/arm/cpu/lowlevel_64.S @@ -10,8 +10,8 @@ ENTRY(arm_cpu_lowlevel_init) switch_el x1, 3f, 2f, 1f 3: - mov x0, #1 /* Non-Secure EL0/1 */ - orr x0, x0, #(1 << 10) /* 64-bit EL2 */ + mrs x0, scr_el3 + orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */ msr scr_el3, x0 msr cptr_el3, xzr -- 2.39.2 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/2] ARM: i.MX8M: add support to handle ROM SError ERR050350 2024-04-30 11:29 [PATCH 1/2] ARM: aarch64: fix scr_el3 register setup Marco Felsch @ 2024-04-30 11:29 ` Marco Felsch 2024-04-30 11:48 ` Marco Felsch 2024-05-03 7:20 ` Sascha Hauer 2024-04-30 21:10 ` [PATCH 1/2] ARM: aarch64: fix scr_el3 register setup Marco Felsch 1 sibling, 2 replies; 6+ messages in thread From: Marco Felsch @ 2024-04-30 11:29 UTC (permalink / raw) To: barebox This ports U-Boot commit: | commit 2f3c92060dcd6bc9cfd3e2e344a3e1745ca39f09 | Author: Peng Fan <peng.fan@nxp.com> | Date: Thu Jul 9 13:39:26 2020 +0800 | | imx8m: workaround ROM serror | | ROM SError happens on two cases: | | 1. ERR050342, on iMX8MQ HDCP enabled parts ROM writes to GPV1 register, but | when ROM patch lock is fused, this write will cause SError. | | 2. ERR050350, on iMX8MQ/MM/MN, when the field return fuse is burned, HAB | is field return mode, but the last 4K of ROM is still protected and cause | SError. | | Since ROM mask SError until ATF unmask it, so then ATF always meets the | exception. This patch works around the issue in SPL by enabling SPL | Exception vectors table and the SError exception, take the exception | to eret immediately to clear the SError. | | Signed-off-by: Ye Li <ye.li@nxp.com> | Signed-off-by: Peng Fan <peng.fan@nxp.com> Other than U-Boot we don't support exceptions in PBL and therefore we can handle it simpler by installing an dummy exception table which does nothing. The table gets overriden by TF-A later on anyway. Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> --- Hi all, I'm not sure if the relocation should be done within the erratum handler or if we should move it into the lowlevel code per default for all i.MX8M platforms since the board files call it anyway after the lowlevel init. In the later case this would be an separate patch to drop the pattern: lowlevel_setup(); relocate_to_current_adr(); from the board files. Regards, Marco arch/arm/mach-imx/Makefile | 1 + arch/arm/mach-imx/cpu_init.c | 12 +++++- arch/arm/mach-imx/errata.c | 22 ++++++++++ arch/arm/mach-imx/imx8m_early_exceptions_64.S | 42 +++++++++++++++++++ include/mach/imx/errata.h | 12 ++++++ 5 files changed, 88 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-imx/errata.c create mode 100644 arch/arm/mach-imx/imx8m_early_exceptions_64.S create mode 100644 include/mach/imx/errata.h diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index ce8af486aed4..d182f95673f5 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_BAREBOX_UPDATE_IMX_EXTERNAL_NAND) += imx-bbu-external-nand.o pbl-$(CONFIG_USB_GADGET_DRIVER_ARC_PBL) += imx-udc.o obj-$(CONFIG_RESET_IMX_SRC) += src.o lwl-y += cpu_init.o +lwl-y += errata.o imx8m_early_exceptions_64.o pbl-y += xload-spi.o xload-common.o xload-imx-nand.o xload-gpmi-nand.o pbl-y += xload-qspi.o obj-pbl-$(CONFIG_ARCH_IMX9) += ele.o diff --git a/arch/arm/mach-imx/cpu_init.c b/arch/arm/mach-imx/cpu_init.c index c5a47d9b9154..aebbd3defaec 100644 --- a/arch/arm/mach-imx/cpu_init.c +++ b/arch/arm/mach-imx/cpu_init.c @@ -6,6 +6,7 @@ #include <asm/errata.h> #include <linux/types.h> #include <linux/bitops.h> +#include <mach/imx/errata.h> #include <mach/imx/generic.h> #include <mach/imx/imx7-regs.h> #include <mach/imx/imx8mq-regs.h> @@ -75,17 +76,26 @@ void imx8mm_cpu_lowlevel_init(void) imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_SCTR); imx8m_cpu_lowlevel_init(); + + erratum_050350_imx8m(); } void imx8mn_cpu_lowlevel_init(void) __alias(imx8mm_cpu_lowlevel_init); void imx8mp_cpu_lowlevel_init(void) - __alias(imx8mm_cpu_lowlevel_init); +{ + /* ungate system counter */ + imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_SCTR); + + imx8m_cpu_lowlevel_init(); +} void imx8mq_cpu_lowlevel_init(void) { imx8m_cpu_lowlevel_init(); + + erratum_050350_imx8m(); } #define CCM_AUTHEN_TZ_NS BIT(9) diff --git a/arch/arm/mach-imx/errata.c b/arch/arm/mach-imx/errata.c new file mode 100644 index 000000000000..ef8de91a9278 --- /dev/null +++ b/arch/arm/mach-imx/errata.c @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <asm/barebox-arm.h> +#include <asm/system.h> +#include <mach/imx/errata.h> + +#ifdef CONFIG_CPU_V8 + +extern unsigned long early_imx8m_vectors; + +void erratum_050350_imx8m(void) +{ + if (current_el() != 3) + return; + + relocate_to_current_adr(); + + asm volatile("msr vbar_el3, %0" : : "r" (&early_imx8m_vectors) : "cc"); + asm volatile("msr daifclr, #4;isb"); +} + +#endif /* CONFIG_CPU_V8 */ diff --git a/arch/arm/mach-imx/imx8m_early_exceptions_64.S b/arch/arm/mach-imx/imx8m_early_exceptions_64.S new file mode 100644 index 000000000000..cd91e1a07b9c --- /dev/null +++ b/arch/arm/mach-imx/imx8m_early_exceptions_64.S @@ -0,0 +1,42 @@ +/* + * (C) Copyright 2013 + * David Feng <fenghua@phytium.com.cn> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/linkage.h> + +#ifdef CONFIG_CPU_V8 + +/* + * Early exception vectors. + */ + .align 11 + .globl early_imx8m_vectors +early_imx8m_vectors: + .align 7 + eret + + .align 7 + eret + + .align 7 + eret + + .align 7 + eret + + .align 7 + eret + + .align 7 + eret + + .align 7 + eret + + .align 7 + eret + +#endif /* CONFIG_CPU_V8 */ diff --git a/include/mach/imx/errata.h b/include/mach/imx/errata.h new file mode 100644 index 000000000000..f63342d446fc --- /dev/null +++ b/include/mach/imx/errata.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MACH_IMX_ERRATA_H +#define __MACH_IMX_ERRATA_H + +#ifdef CONFIG_CPU_V8 + +void erratum_050350_imx8m(void); + +#endif /* CONFIG_CPU_V8 */ + +#endif /* __MACH_IMX_ERRATA_H */ -- 2.39.2 ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] ARM: i.MX8M: add support to handle ROM SError ERR050350 2024-04-30 11:29 ` [PATCH 2/2] ARM: i.MX8M: add support to handle ROM SError ERR050350 Marco Felsch @ 2024-04-30 11:48 ` Marco Felsch 2024-05-03 7:20 ` Sascha Hauer 1 sibling, 0 replies; 6+ messages in thread From: Marco Felsch @ 2024-04-30 11:48 UTC (permalink / raw) To: barebox On 24-04-30, Marco Felsch wrote: > This ports U-Boot commit: > > | commit 2f3c92060dcd6bc9cfd3e2e344a3e1745ca39f09 > | Author: Peng Fan <peng.fan@nxp.com> > | Date: Thu Jul 9 13:39:26 2020 +0800 > | > | imx8m: workaround ROM serror > | > | ROM SError happens on two cases: > | > | 1. ERR050342, on iMX8MQ HDCP enabled parts ROM writes to GPV1 register, but > | when ROM patch lock is fused, this write will cause SError. > | > | 2. ERR050350, on iMX8MQ/MM/MN, when the field return fuse is burned, HAB > | is field return mode, but the last 4K of ROM is still protected and cause > | SError. > | > | Since ROM mask SError until ATF unmask it, so then ATF always meets the > | exception. This patch works around the issue in SPL by enabling SPL > | Exception vectors table and the SError exception, take the exception > | to eret immediately to clear the SError. > | > | Signed-off-by: Ye Li <ye.li@nxp.com> > | Signed-off-by: Peng Fan <peng.fan@nxp.com> > > Other than U-Boot we don't support exceptions in PBL and therefore we > can handle it simpler by installing an dummy exception table which does > nothing. The table gets overriden by TF-A later on anyway. > > Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> > --- > Hi all, > > I'm not sure if the relocation should be done within the erratum > handler or if we should move it into the lowlevel code per default for > all i.MX8M platforms since the board files call it anyway after the > lowlevel init. In the later case this would be an separate patch to drop > the pattern: > > lowlevel_setup(); > relocate_to_current_adr(); > > from the board files. ... > diff --git a/arch/arm/mach-imx/errata.c b/arch/arm/mach-imx/errata.c > new file mode 100644 > index 000000000000..ef8de91a9278 > --- /dev/null > +++ b/arch/arm/mach-imx/errata.c > @@ -0,0 +1,22 @@ > +// SPDX-License-Identifier: GPL-2.0+ > + > +#include <asm/barebox-arm.h> > +#include <asm/system.h> > +#include <mach/imx/errata.h> > + > +#ifdef CONFIG_CPU_V8 > + > +extern unsigned long early_imx8m_vectors; > + > +void erratum_050350_imx8m(void) > +{ > + if (current_el() != 3) > + return; > + > + relocate_to_current_adr(); If I use: extern char early_imx8m_vectors[]; addr = runtime_address(early_imx8m_vectors); it does work without relocation too. This seems to fit better here. I will send a v2 if you're okay with that. Regards, Marco > + > + asm volatile("msr vbar_el3, %0" : : "r" (&early_imx8m_vectors) : "cc"); > + asm volatile("msr daifclr, #4;isb"); > +} ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] ARM: i.MX8M: add support to handle ROM SError ERR050350 2024-04-30 11:29 ` [PATCH 2/2] ARM: i.MX8M: add support to handle ROM SError ERR050350 Marco Felsch 2024-04-30 11:48 ` Marco Felsch @ 2024-05-03 7:20 ` Sascha Hauer 2024-05-06 7:58 ` Marco Felsch 1 sibling, 1 reply; 6+ messages in thread From: Sascha Hauer @ 2024-05-03 7:20 UTC (permalink / raw) To: Marco Felsch; +Cc: barebox On Tue, Apr 30, 2024 at 01:29:41PM +0200, Marco Felsch wrote: > This ports U-Boot commit: > > | commit 2f3c92060dcd6bc9cfd3e2e344a3e1745ca39f09 > | Author: Peng Fan <peng.fan@nxp.com> > | Date: Thu Jul 9 13:39:26 2020 +0800 > | > | imx8m: workaround ROM serror > | > | ROM SError happens on two cases: > | > | 1. ERR050342, on iMX8MQ HDCP enabled parts ROM writes to GPV1 register, but > | when ROM patch lock is fused, this write will cause SError. > | > | 2. ERR050350, on iMX8MQ/MM/MN, when the field return fuse is burned, HAB > | is field return mode, but the last 4K of ROM is still protected and cause > | SError. > | > | Since ROM mask SError until ATF unmask it, so then ATF always meets the > | exception. This patch works around the issue in SPL by enabling SPL > | Exception vectors table and the SError exception, take the exception > | to eret immediately to clear the SError. > | > | Signed-off-by: Ye Li <ye.li@nxp.com> > | Signed-off-by: Peng Fan <peng.fan@nxp.com> > > Other than U-Boot we don't support exceptions in PBL and therefore we > can handle it simpler by installing an dummy exception table which does > nothing. The table gets overriden by TF-A later on anyway. > > Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> > --- > Hi all, > > I'm not sure if the relocation should be done within the erratum > handler or if we should move it into the lowlevel code per default for > all i.MX8M platforms since the board files call it anyway after the > lowlevel init. In the later case this would be an separate patch to drop > the pattern: > > lowlevel_setup(); > relocate_to_current_adr(); > > from the board files. > > Regards, > Marco > > arch/arm/mach-imx/Makefile | 1 + > arch/arm/mach-imx/cpu_init.c | 12 +++++- > arch/arm/mach-imx/errata.c | 22 ++++++++++ > arch/arm/mach-imx/imx8m_early_exceptions_64.S | 42 +++++++++++++++++++ > include/mach/imx/errata.h | 12 ++++++ > 5 files changed, 88 insertions(+), 1 deletion(-) > create mode 100644 arch/arm/mach-imx/errata.c > create mode 100644 arch/arm/mach-imx/imx8m_early_exceptions_64.S > create mode 100644 include/mach/imx/errata.h > > diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile > index ce8af486aed4..d182f95673f5 100644 > --- a/arch/arm/mach-imx/Makefile > +++ b/arch/arm/mach-imx/Makefile > @@ -34,6 +34,7 @@ obj-$(CONFIG_BAREBOX_UPDATE_IMX_EXTERNAL_NAND) += imx-bbu-external-nand.o > pbl-$(CONFIG_USB_GADGET_DRIVER_ARC_PBL) += imx-udc.o > obj-$(CONFIG_RESET_IMX_SRC) += src.o > lwl-y += cpu_init.o > +lwl-y += errata.o imx8m_early_exceptions_64.o Should likely be: lwl-$(CONFIG_ARCH_IMX8M) += imx8m_early_exceptions_64.o Also you can drop the _64 suffix from the filename as the imx8m_ preifx already implies this. > pbl-y += xload-spi.o xload-common.o xload-imx-nand.o xload-gpmi-nand.o > pbl-y += xload-qspi.o > obj-pbl-$(CONFIG_ARCH_IMX9) += ele.o > diff --git a/arch/arm/mach-imx/cpu_init.c b/arch/arm/mach-imx/cpu_init.c > index c5a47d9b9154..aebbd3defaec 100644 > --- a/arch/arm/mach-imx/cpu_init.c > +++ b/arch/arm/mach-imx/cpu_init.c > @@ -6,6 +6,7 @@ > #include <asm/errata.h> > #include <linux/types.h> > #include <linux/bitops.h> > +#include <mach/imx/errata.h> > #include <mach/imx/generic.h> > #include <mach/imx/imx7-regs.h> > #include <mach/imx/imx8mq-regs.h> > @@ -75,17 +76,26 @@ void imx8mm_cpu_lowlevel_init(void) > imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_SCTR); > > imx8m_cpu_lowlevel_init(); > + > + erratum_050350_imx8m(); > } > > void imx8mn_cpu_lowlevel_init(void) > __alias(imx8mm_cpu_lowlevel_init); > > void imx8mp_cpu_lowlevel_init(void) > - __alias(imx8mm_cpu_lowlevel_init); > +{ > + /* ungate system counter */ > + imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_SCTR); > + > + imx8m_cpu_lowlevel_init(); > +} > > void imx8mq_cpu_lowlevel_init(void) > { > imx8m_cpu_lowlevel_init(); > + > + erratum_050350_imx8m(); > } > > #define CCM_AUTHEN_TZ_NS BIT(9) > diff --git a/arch/arm/mach-imx/errata.c b/arch/arm/mach-imx/errata.c > new file mode 100644 > index 000000000000..ef8de91a9278 > --- /dev/null > +++ b/arch/arm/mach-imx/errata.c > @@ -0,0 +1,22 @@ > +// SPDX-License-Identifier: GPL-2.0+ > + > +#include <asm/barebox-arm.h> > +#include <asm/system.h> > +#include <mach/imx/errata.h> > + > +#ifdef CONFIG_CPU_V8 > + > +extern unsigned long early_imx8m_vectors; > + > +void erratum_050350_imx8m(void) > +{ > + if (current_el() != 3) > + return; > + > + relocate_to_current_adr(); > + > + asm volatile("msr vbar_el3, %0" : : "r" (&early_imx8m_vectors) : "cc"); > + asm volatile("msr daifclr, #4;isb"); > +} > + > +#endif /* CONFIG_CPU_V8 */ > diff --git a/arch/arm/mach-imx/imx8m_early_exceptions_64.S b/arch/arm/mach-imx/imx8m_early_exceptions_64.S > new file mode 100644 > index 000000000000..cd91e1a07b9c > --- /dev/null > +++ b/arch/arm/mach-imx/imx8m_early_exceptions_64.S > @@ -0,0 +1,42 @@ > +/* > + * (C) Copyright 2013 > + * David Feng <fenghua@phytium.com.cn> > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <linux/linkage.h> > + > +#ifdef CONFIG_CPU_V8 > + > +/* > + * Early exception vectors. > + */ > + .align 11 > + .globl early_imx8m_vectors > +early_imx8m_vectors: > + .align 7 > + eret > + > + .align 7 > + eret > + > + .align 7 > + eret > + > + .align 7 > + eret > + > + .align 7 > + eret > + > + .align 7 > + eret > + > + .align 7 > + eret > + > + .align 7 > + eret > + > +#endif /* CONFIG_CPU_V8 */ > diff --git a/include/mach/imx/errata.h b/include/mach/imx/errata.h > new file mode 100644 > index 000000000000..f63342d446fc > --- /dev/null > +++ b/include/mach/imx/errata.h > @@ -0,0 +1,12 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > + > +#ifndef __MACH_IMX_ERRATA_H > +#define __MACH_IMX_ERRATA_H > + > +#ifdef CONFIG_CPU_V8 No need to ifdef function prototypes. Sascha -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] ARM: i.MX8M: add support to handle ROM SError ERR050350 2024-05-03 7:20 ` Sascha Hauer @ 2024-05-06 7:58 ` Marco Felsch 0 siblings, 0 replies; 6+ messages in thread From: Marco Felsch @ 2024-05-06 7:58 UTC (permalink / raw) To: Sascha Hauer; +Cc: barebox On 24-05-03, Sascha Hauer wrote: > On Tue, Apr 30, 2024 at 01:29:41PM +0200, Marco Felsch wrote: > > This ports U-Boot commit: > > > > | commit 2f3c92060dcd6bc9cfd3e2e344a3e1745ca39f09 > > | Author: Peng Fan <peng.fan@nxp.com> > > | Date: Thu Jul 9 13:39:26 2020 +0800 > > | > > | imx8m: workaround ROM serror > > | > > | ROM SError happens on two cases: > > | > > | 1. ERR050342, on iMX8MQ HDCP enabled parts ROM writes to GPV1 register, but > > | when ROM patch lock is fused, this write will cause SError. > > | > > | 2. ERR050350, on iMX8MQ/MM/MN, when the field return fuse is burned, HAB > > | is field return mode, but the last 4K of ROM is still protected and cause > > | SError. > > | > > | Since ROM mask SError until ATF unmask it, so then ATF always meets the > > | exception. This patch works around the issue in SPL by enabling SPL > > | Exception vectors table and the SError exception, take the exception > > | to eret immediately to clear the SError. > > | > > | Signed-off-by: Ye Li <ye.li@nxp.com> > > | Signed-off-by: Peng Fan <peng.fan@nxp.com> > > > > Other than U-Boot we don't support exceptions in PBL and therefore we > > can handle it simpler by installing an dummy exception table which does > > nothing. The table gets overriden by TF-A later on anyway. > > > > Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> > > --- > > Hi all, > > > > I'm not sure if the relocation should be done within the erratum > > handler or if we should move it into the lowlevel code per default for > > all i.MX8M platforms since the board files call it anyway after the > > lowlevel init. In the later case this would be an separate patch to drop > > the pattern: > > > > lowlevel_setup(); > > relocate_to_current_adr(); > > > > from the board files. > > > > Regards, > > Marco > > > > arch/arm/mach-imx/Makefile | 1 + > > arch/arm/mach-imx/cpu_init.c | 12 +++++- > > arch/arm/mach-imx/errata.c | 22 ++++++++++ > > arch/arm/mach-imx/imx8m_early_exceptions_64.S | 42 +++++++++++++++++++ > > include/mach/imx/errata.h | 12 ++++++ > > 5 files changed, 88 insertions(+), 1 deletion(-) > > create mode 100644 arch/arm/mach-imx/errata.c > > create mode 100644 arch/arm/mach-imx/imx8m_early_exceptions_64.S > > create mode 100644 include/mach/imx/errata.h > > > > diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile > > index ce8af486aed4..d182f95673f5 100644 > > --- a/arch/arm/mach-imx/Makefile > > +++ b/arch/arm/mach-imx/Makefile > > @@ -34,6 +34,7 @@ obj-$(CONFIG_BAREBOX_UPDATE_IMX_EXTERNAL_NAND) += imx-bbu-external-nand.o > > pbl-$(CONFIG_USB_GADGET_DRIVER_ARC_PBL) += imx-udc.o > > obj-$(CONFIG_RESET_IMX_SRC) += src.o > > lwl-y += cpu_init.o > > +lwl-y += errata.o imx8m_early_exceptions_64.o > > Should likely be: > > lwl-$(CONFIG_ARCH_IMX8M) += imx8m_early_exceptions_64.o > > Also you can drop the _64 suffix from the filename as the imx8m_ preifx > already implies this. Sure. > > pbl-y += xload-spi.o xload-common.o xload-imx-nand.o xload-gpmi-nand.o > > pbl-y += xload-qspi.o > > obj-pbl-$(CONFIG_ARCH_IMX9) += ele.o > > diff --git a/arch/arm/mach-imx/cpu_init.c b/arch/arm/mach-imx/cpu_init.c > > index c5a47d9b9154..aebbd3defaec 100644 > > --- a/arch/arm/mach-imx/cpu_init.c > > +++ b/arch/arm/mach-imx/cpu_init.c > > @@ -6,6 +6,7 @@ > > #include <asm/errata.h> > > #include <linux/types.h> > > #include <linux/bitops.h> > > +#include <mach/imx/errata.h> > > #include <mach/imx/generic.h> > > #include <mach/imx/imx7-regs.h> > > #include <mach/imx/imx8mq-regs.h> > > @@ -75,17 +76,26 @@ void imx8mm_cpu_lowlevel_init(void) > > imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_SCTR); > > > > imx8m_cpu_lowlevel_init(); > > + > > + erratum_050350_imx8m(); > > } > > > > void imx8mn_cpu_lowlevel_init(void) > > __alias(imx8mm_cpu_lowlevel_init); > > > > void imx8mp_cpu_lowlevel_init(void) > > - __alias(imx8mm_cpu_lowlevel_init); > > +{ > > + /* ungate system counter */ > > + imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_SCTR); > > + > > + imx8m_cpu_lowlevel_init(); > > +} > > > > void imx8mq_cpu_lowlevel_init(void) > > { > > imx8m_cpu_lowlevel_init(); > > + > > + erratum_050350_imx8m(); > > } > > > > #define CCM_AUTHEN_TZ_NS BIT(9) > > diff --git a/arch/arm/mach-imx/errata.c b/arch/arm/mach-imx/errata.c > > new file mode 100644 > > index 000000000000..ef8de91a9278 > > --- /dev/null > > +++ b/arch/arm/mach-imx/errata.c > > @@ -0,0 +1,22 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > + > > +#include <asm/barebox-arm.h> > > +#include <asm/system.h> > > +#include <mach/imx/errata.h> > > + > > +#ifdef CONFIG_CPU_V8 > > + > > +extern unsigned long early_imx8m_vectors; > > + > > +void erratum_050350_imx8m(void) > > +{ > > + if (current_el() != 3) > > + return; > > + > > + relocate_to_current_adr(); > > + > > + asm volatile("msr vbar_el3, %0" : : "r" (&early_imx8m_vectors) : "cc"); > > + asm volatile("msr daifclr, #4;isb"); > > +} > > + > > +#endif /* CONFIG_CPU_V8 */ > > diff --git a/arch/arm/mach-imx/imx8m_early_exceptions_64.S b/arch/arm/mach-imx/imx8m_early_exceptions_64.S > > new file mode 100644 > > index 000000000000..cd91e1a07b9c > > --- /dev/null > > +++ b/arch/arm/mach-imx/imx8m_early_exceptions_64.S > > @@ -0,0 +1,42 @@ > > +/* > > + * (C) Copyright 2013 > > + * David Feng <fenghua@phytium.com.cn> > > + * > > + * SPDX-License-Identifier: GPL-2.0+ > > + */ > > + > > +#include <linux/linkage.h> > > + > > +#ifdef CONFIG_CPU_V8 > > + > > +/* > > + * Early exception vectors. > > + */ > > + .align 11 > > + .globl early_imx8m_vectors > > +early_imx8m_vectors: > > + .align 7 > > + eret > > + > > + .align 7 > > + eret > > + > > + .align 7 > > + eret > > + > > + .align 7 > > + eret > > + > > + .align 7 > > + eret > > + > > + .align 7 > > + eret > > + > > + .align 7 > > + eret > > + > > + .align 7 > > + eret > > + > > +#endif /* CONFIG_CPU_V8 */ > > diff --git a/include/mach/imx/errata.h b/include/mach/imx/errata.h > > new file mode 100644 > > index 000000000000..f63342d446fc > > --- /dev/null > > +++ b/include/mach/imx/errata.h > > @@ -0,0 +1,12 @@ > > +/* SPDX-License-Identifier: GPL-2.0-only */ > > + > > +#ifndef __MACH_IMX_ERRATA_H > > +#define __MACH_IMX_ERRATA_H > > + > > +#ifdef CONFIG_CPU_V8 > > No need to ifdef function prototypes. Yes you're right. Regards, Marco > > Sascha > > -- > Pengutronix e.K. | | > Steuerwalder Str. 21 | http://www.pengutronix.de/ | > 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | > ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] ARM: aarch64: fix scr_el3 register setup 2024-04-30 11:29 [PATCH 1/2] ARM: aarch64: fix scr_el3 register setup Marco Felsch 2024-04-30 11:29 ` [PATCH 2/2] ARM: i.MX8M: add support to handle ROM SError ERR050350 Marco Felsch @ 2024-04-30 21:10 ` Marco Felsch 1 sibling, 0 replies; 6+ messages in thread From: Marco Felsch @ 2024-04-30 21:10 UTC (permalink / raw) To: barebox Hi, On 24-04-30, Marco Felsch wrote: > The current code moved '1' as immediate into x0 and does OR with > BIT(10). This doesn't look right since it will set the scr_el3 to 0. > > Instead read the scr_el3 and OR the interessting bits to fix this. The > interessting bits are taken from the current U-Boot implementation. please ignore this message which is complete off, my head tricked me :/ I will fix this in v2. But still, I'm out of glue regarding the 64-bit EL2 setting. We set this since the very beginning but without mentioning the reason. Therefore I would like to drop it and align our code with U-Boot. Regards, Marco > > Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> > --- > arch/arm/cpu/lowlevel_64.S | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/cpu/lowlevel_64.S b/arch/arm/cpu/lowlevel_64.S > index ed00c8c47057..1f5a0b73f8b3 100644 > --- a/arch/arm/cpu/lowlevel_64.S > +++ b/arch/arm/cpu/lowlevel_64.S > @@ -10,8 +10,8 @@ ENTRY(arm_cpu_lowlevel_init) > switch_el x1, 3f, 2f, 1f > > 3: > - mov x0, #1 /* Non-Secure EL0/1 */ > - orr x0, x0, #(1 << 10) /* 64-bit EL2 */ > + mrs x0, scr_el3 > + orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */ > msr scr_el3, x0 > msr cptr_el3, xzr > > -- > 2.39.2 > > > ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2024-05-06 7:58 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2024-04-30 11:29 [PATCH 1/2] ARM: aarch64: fix scr_el3 register setup Marco Felsch 2024-04-30 11:29 ` [PATCH 2/2] ARM: i.MX8M: add support to handle ROM SError ERR050350 Marco Felsch 2024-04-30 11:48 ` Marco Felsch 2024-05-03 7:20 ` Sascha Hauer 2024-05-06 7:58 ` Marco Felsch 2024-04-30 21:10 ` [PATCH 1/2] ARM: aarch64: fix scr_el3 register setup Marco Felsch
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