Re: [PATCH 1/2] ARM: aarch64: fix scr_el3 register setup

[Marco Felsch <m.felsch@pengutronix.de>]

Hi,

On 24-04-30, Marco Felsch wrote:
> The current code moved '1' as immediate into x0 and does OR with
> BIT(10). This doesn't look right since it will set the scr_el3 to 0.
> 
> Instead read the scr_el3 and OR the interessting bits to fix this. The
> interessting bits are taken from the current U-Boot implementation.

please ignore this message which is complete off, my head tricked me :/

I will fix this in v2. But still, I'm out of glue regarding the 64-bit
EL2 setting. We set this since the very beginning but without mentioning
the reason. Therefore I would like to drop it and align our code with
U-Boot.

Regards,
  Marco

> 
> Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
> ---
>  arch/arm/cpu/lowlevel_64.S | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/cpu/lowlevel_64.S b/arch/arm/cpu/lowlevel_64.S
> index ed00c8c47057..1f5a0b73f8b3 100644
> --- a/arch/arm/cpu/lowlevel_64.S
> +++ b/arch/arm/cpu/lowlevel_64.S
> @@ -10,8 +10,8 @@ ENTRY(arm_cpu_lowlevel_init)
>  	switch_el x1, 3f, 2f, 1f
>  
>  3:
> -	mov	x0, #1			/* Non-Secure EL0/1 */
> -	orr	x0, x0, #(1 << 10)	/* 64-bit EL2 */
> +	mrs	x0, scr_el3
> +	orr	x0, x0, #0xf			/* SCR_EL3.NS|IRQ|FIQ|EA */
>  	msr	scr_el3, x0
>  	msr	cptr_el3, xzr
>  
> -- 
> 2.39.2
> 
> 
>