* [PATCH 00/14] ARM: SoCFPGA: arria10: clean up early bitstream loading
@ 2024-06-17 11:36 Steffen Trumtrar
2024-06-17 11:36 ` [PATCH 01/14] ARM: arria10: system-manager: add handoff registers Steffen Trumtrar
` (14 more replies)
0 siblings, 15 replies; 16+ messages in thread
From: Steffen Trumtrar @ 2024-06-17 11:36 UTC (permalink / raw)
To: barebox; +Cc: Steffen Trumtrar
This series cleans up/reworks the early bitstream loading in the Arria10
xloader code.
Some useful defines are added on the way.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
Steffen Trumtrar (14):
ARM: arria10: system-manager: add handoff registers
ARM: Arria10: reset manager: document reset source
ARM: socfpga: Arria10: PE1: remove arm_cpu_lowlevel_init
ARM: arria10: reset-manager: don't touch l4 wdog
ARM: Arria10: PE1: disable l4wd0 in bringup
ARM: Arria10: xload: rework __arria10_load_fpga
ARM: arria10: xload: fix __arria10_load_fpga
ARM: Arria10: xload: kick watchdog
ARM: arria10: mark image in OCRAM as valid
ARM: Arria10: arria10_finish_io: remove unused param
ARM: Arria10: xload: remove useless writel
ARM: Arria10: xload: refactor wait loops
ARM: Arria10: xload: reduce timeout on condone
ARM: arria10-xload: rework broken bitstream handling
arch/arm/boards/enclustra-aa1/lowlevel.c | 7 +-
arch/arm/boards/reflex-achilles/lowlevel.c | 4 +-
arch/arm/mach-socfpga/arria10-generic.c | 4 +
arch/arm/mach-socfpga/arria10-init.c | 4 +-
arch/arm/mach-socfpga/arria10-reset-manager.c | 9 ++-
arch/arm/mach-socfpga/arria10-xload.c | 106 ++++++++++++++------------
include/mach/socfpga/arria10-fpga.h | 1 +
include/mach/socfpga/arria10-reset-manager.h | 31 ++++++++
include/mach/socfpga/arria10-system-manager.h | 12 ++-
include/mach/socfpga/generic.h | 16 +++-
10 files changed, 131 insertions(+), 63 deletions(-)
---
base-commit: bafdf4b35d777d159ac4058efc86d36622ce5ccf
change-id: 20240617-v2024-05-0-topic-socfpga-arria10-xloader-eae42963348a
Best regards,
--
Steffen Trumtrar <s.trumtrar@pengutronix.de>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 01/14] ARM: arria10: system-manager: add handoff registers
2024-06-17 11:36 [PATCH 00/14] ARM: SoCFPGA: arria10: clean up early bitstream loading Steffen Trumtrar
@ 2024-06-17 11:36 ` Steffen Trumtrar
2024-06-17 11:36 ` [PATCH 02/14] ARM: Arria10: reset manager: document reset source Steffen Trumtrar
` (13 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Steffen Trumtrar @ 2024-06-17 11:36 UTC (permalink / raw)
To: barebox; +Cc: Steffen Trumtrar
The isw handoff registers are free to use for the bootloader. Add their
offsets for lowlevel debugging purposes.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
include/mach/socfpga/arria10-system-manager.h | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/include/mach/socfpga/arria10-system-manager.h b/include/mach/socfpga/arria10-system-manager.h
index f92025ae32..536baf6bc3 100644
--- a/include/mach/socfpga/arria10-system-manager.h
+++ b/include/mach/socfpga/arria10-system-manager.h
@@ -53,6 +53,15 @@
#define ARRIA10_SYSMGR_FPGA2SOC_CTRL (ARRIA10_SYSMGR_ADDR + 0xd8)
#define ARRIA10_SYSMGR_ROM_INITSWLASTLD (ARRIA10_SYSMGR_ADDR + 0x10)
+#define ARRIA10_SYSMGR_ROM_ISW0 (ARRIA10_SYSMGR_ADDR + 0x230)
+#define ARRIA10_SYSMGR_ROM_ISW1 (ARRIA10_SYSMGR_ADDR + 0x234)
+#define ARRIA10_SYSMGR_ROM_ISW2 (ARRIA10_SYSMGR_ADDR + 0x238)
+#define ARRIA10_SYSMGR_ROM_ISW3 (ARRIA10_SYSMGR_ADDR + 0x23c)
+#define ARRIA10_SYSMGR_ROM_ISW4 (ARRIA10_SYSMGR_ADDR + 0x240)
+#define ARRIA10_SYSMGR_ROM_ISW5 (ARRIA10_SYSMGR_ADDR + 0x244)
+#define ARRIA10_SYSMGR_ROM_ISW6 (ARRIA10_SYSMGR_ADDR + 0x248)
+#define ARRIA10_SYSMGR_ROM_ISW7 (ARRIA10_SYSMGR_ADDR + 0x24c)
+
#define ARRIA10_SYSMGR_BOOTINFO_BSEL_MASK 0x00007000
--
2.43.2
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 02/14] ARM: Arria10: reset manager: document reset source
2024-06-17 11:36 [PATCH 00/14] ARM: SoCFPGA: arria10: clean up early bitstream loading Steffen Trumtrar
2024-06-17 11:36 ` [PATCH 01/14] ARM: arria10: system-manager: add handoff registers Steffen Trumtrar
@ 2024-06-17 11:36 ` Steffen Trumtrar
2024-06-17 11:36 ` [PATCH 03/14] ARM: socfpga: Arria10: PE1: remove arm_cpu_lowlevel_init Steffen Trumtrar
` (12 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Steffen Trumtrar @ 2024-06-17 11:36 UTC (permalink / raw)
To: barebox; +Cc: Steffen Trumtrar
Add defines for the reset manager reset source bits in the STAT register.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
include/mach/socfpga/arria10-reset-manager.h | 31 ++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/include/mach/socfpga/arria10-reset-manager.h b/include/mach/socfpga/arria10-reset-manager.h
index 2033de77a3..45a48aba7c 100644
--- a/include/mach/socfpga/arria10-reset-manager.h
+++ b/include/mach/socfpga/arria10-reset-manager.h
@@ -40,6 +40,37 @@
#define ARRIA10_RSTMGR_HMCGPOUT 0x78
#define ARRIA10_RSTMGR_HMCGPIN 0x7c
+/* Built-in HPS POR voltage detector triggered a cold reset. */
+#define ARRIA10_RSTMGR_STAT_PORHPSVOLTRST BIT(0)
+/* Built-in FPGA POR voltage detector triggered a cold reset. */
+#define ARRIA10_RSTMGR_STAT_PORFPGAVOLTRST BIT(1)
+/* nPOR pin triggered a col reset (por_pin_req = 1) */
+#define ARRIA10_RSTMGR_STAT_NPORPINRST BIT(2)
+/* FPGA core triggered a cold reset (f2s_cold_rst_req = 1) */
+#define ARRIA10_RSTMGR_STAT_FPGACOLDRST BIT(3)
+/* FPGA entered CONFIG_IO mode and triggered a cold reset */
+#define ARRIA10_RSTMGR_STAT_CONFIGIOCOLDRST BIT(4)
+/* Software wrote CTRL.SWCOLDRSTREQ to 1 and triggered a cold reset */
+#define ARRIA10_RSTMGR_STAT_SWCOLDRST BIT(5)
+/* nRST pin triggered a hardware sequenced warm reset */
+#define ARRIA10_RSTMGR_STAT_NRSTPINRST BIT(8)
+/* FPGA core triggered a hardware sequenced warm reset */
+#define ARRIA10_RSTMGR_STAT_FPGAWARMRST BIT(9)
+/* Software wrote CTRL.SWWARMRSTREQ to 1 and triggered a hardware sequenced warm reset. */
+#define ARRIA10_RSTMGR_STAT_SWWARMRST BIT(10)
+/* MPU watchdog 0 triggered a hardware sequenced warm reset */
+#define ARRIA10_RSTMGR_STAT_MPUWD0WARMRST BIT(11)
+/* MPU watchdog 1 triggered a hardware sequenced warm reset */
+#define ARRIA10_RSTMGR_STAT_MPUWD1WARMRST BIT(12)
+/* L4 watchdog 0 triggered a hardware sequenced warm reset */
+#define ARRIA10_RSTMGR_STAT_L4WD0WARMRST BIT(13)
+/* L4 watchdog 1 triggered a hardware sequenced warm reset */
+#define ARRIA10_RSTMGR_STAT_L4WD1WARMRST BIT(14)
+/* FPGA triggered debug reset */
+#define ARRIA10_RSTMGR_STAT_FPGADBGRST BIT(16)
+/* DAP triggered debug reset */
+#define ARRIA10_RSTMGR_STAT_CDBGRST BIT(17)
+
#define ARRIA10_RSTMGR_CTL_SWWARMRSTREQ BIT(1)
#define ARRIA10_RSTMGR_PER0MODRST_EMAC0 BIT(0)
#define ARRIA10_RSTMGR_PER0MODRST_EMAC1 BIT(1)
--
2.43.2
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 03/14] ARM: socfpga: Arria10: PE1: remove arm_cpu_lowlevel_init
2024-06-17 11:36 [PATCH 00/14] ARM: SoCFPGA: arria10: clean up early bitstream loading Steffen Trumtrar
2024-06-17 11:36 ` [PATCH 01/14] ARM: arria10: system-manager: add handoff registers Steffen Trumtrar
2024-06-17 11:36 ` [PATCH 02/14] ARM: Arria10: reset manager: document reset source Steffen Trumtrar
@ 2024-06-17 11:36 ` Steffen Trumtrar
2024-06-17 11:36 ` [PATCH 04/14] ARM: arria10: reset-manager: don't touch l4 wdog Steffen Trumtrar
` (11 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Steffen Trumtrar @ 2024-06-17 11:36 UTC (permalink / raw)
To: barebox; +Cc: Steffen Trumtrar
The bringup image is intedend to be loaded via JTAG.
The arm_cpu_lowlevel_init() call often results in bringup errors,
because for some unknown reason we hang in relocate_to_current_adr if
arm_cpu_lowlevel_init is run beforehand. Without it, starting barebox
over JTAG works fine.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
arch/arm/boards/enclustra-aa1/lowlevel.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/boards/enclustra-aa1/lowlevel.c b/arch/arm/boards/enclustra-aa1/lowlevel.c
index ba4d562e5f..ada7cb5a9f 100644
--- a/arch/arm/boards/enclustra-aa1/lowlevel.c
+++ b/arch/arm/boards/enclustra-aa1/lowlevel.c
@@ -103,7 +103,6 @@ ENTRY_FUNCTION_WITHSTACK(start_socfpga_aa1_bringup, ARRIA10_STACKTOP, r0, r1, r2
{
void *fdt;
- arm_cpu_lowlevel_init();
arria10_cpu_lowlevel_init();
relocate_to_current_adr();
--
2.43.2
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 04/14] ARM: arria10: reset-manager: don't touch l4 wdog
2024-06-17 11:36 [PATCH 00/14] ARM: SoCFPGA: arria10: clean up early bitstream loading Steffen Trumtrar
` (2 preceding siblings ...)
2024-06-17 11:36 ` [PATCH 03/14] ARM: socfpga: Arria10: PE1: remove arm_cpu_lowlevel_init Steffen Trumtrar
@ 2024-06-17 11:36 ` Steffen Trumtrar
2024-06-17 11:36 ` [PATCH 05/14] ARM: Arria10: PE1: disable l4wd0 in bringup Steffen Trumtrar
` (10 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Steffen Trumtrar @ 2024-06-17 11:36 UTC (permalink / raw)
To: barebox; +Cc: Steffen Trumtrar
Leave the L4 watchdog 0 running.
If a watchdog reset happens while booting, the bootrom attempts to load
the last valid bootloader identified by the initswlastld register.
As we now hang() in arria10-xload after 10 failed FPGA writing attempts,
we need the watchdog to trigger so that the bootrom can try to start the
next bootloader image as fallback.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
arch/arm/mach-socfpga/arria10-reset-manager.c | 9 ++++++---
arch/arm/mach-socfpga/arria10-xload.c | 5 +++++
include/mach/socfpga/generic.h | 2 ++
3 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-socfpga/arria10-reset-manager.c b/arch/arm/mach-socfpga/arria10-reset-manager.c
index 05440cf903..6f209e7045 100644
--- a/arch/arm/mach-socfpga/arria10-reset-manager.c
+++ b/arch/arm/mach-socfpga/arria10-reset-manager.c
@@ -33,9 +33,13 @@ void arria10_reset_peripherals(void)
}
/* disable all components except the ECC_OCP and bootsource */
- writel(0xffffffff, ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER1MODRST);
writel(~mask, ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST);
+ mask = ARRIA10_RSTMGR_PER1MODRST_WATCHDOG0 |
+ ARRIA10_RSTMGR_PER1MODRST_L4SYSTIMER0;
+ /* disable all components except L4 watchdog */
+ writel(~mask, ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER1MODRST);
+
mask = 0xffffffff;
if (src == BOOTSOURCE_MMC) {
@@ -65,8 +69,7 @@ void arria10_reset_deassert_dedicated_peripherals(void)
clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST, mask);
- mask = ARRIA10_RSTMGR_PER1MODRST_L4SYSTIMER0 |
- ARRIA10_RSTMGR_PER1MODRST_UART1 |
+ mask = ARRIA10_RSTMGR_PER1MODRST_UART1 |
ARRIA10_RSTMGR_PER1MODRST_UART0;
clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER1MODRST, mask);
diff --git a/arch/arm/mach-socfpga/arria10-xload.c b/arch/arm/mach-socfpga/arria10-xload.c
index db3cc209ee..7b0d6f00fb 100644
--- a/arch/arm/mach-socfpga/arria10-xload.c
+++ b/arch/arm/mach-socfpga/arria10-xload.c
@@ -437,6 +437,11 @@ void arria10_start_image(int offset)
if (ret)
hang();
+ /* mark image in OCRAM as valid */
+ writel(ARRIA10_SYSMGR_ROM_INITSWSTATE_VALID, ARRIA10_SYSMGR_ROM_INITSWSTATE);
+
+ arria10_watchdog_disable();
+
bb = buf;
bb();
diff --git a/include/mach/socfpga/generic.h b/include/mach/socfpga/generic.h
index 6c359e2abb..1af086140f 100644
--- a/include/mach/socfpga/generic.h
+++ b/include/mach/socfpga/generic.h
@@ -85,6 +85,8 @@ static inline int arria10_device_init(struct arria10_mainpll_cfg *mainpll,
{
return 0;
}
+static void arria10_kick_l4wd0(void) {}
+static void arria10_watchdog_disable(void) {}
#endif
static inline void __udelay(unsigned us)
--
2.43.2
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 05/14] ARM: Arria10: PE1: disable l4wd0 in bringup
2024-06-17 11:36 [PATCH 00/14] ARM: SoCFPGA: arria10: clean up early bitstream loading Steffen Trumtrar
` (3 preceding siblings ...)
2024-06-17 11:36 ` [PATCH 04/14] ARM: arria10: reset-manager: don't touch l4 wdog Steffen Trumtrar
@ 2024-06-17 11:36 ` Steffen Trumtrar
2024-06-17 11:36 ` [PATCH 06/14] ARM: Arria10: xload: rework __arria10_load_fpga Steffen Trumtrar
` (9 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Steffen Trumtrar @ 2024-06-17 11:36 UTC (permalink / raw)
To: barebox; +Cc: Steffen Trumtrar
The l4wd0 is now left running from the BootROM. Disable it in the
bringup image, because it would only make problems and has no benefit in
that case.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
arch/arm/boards/enclustra-aa1/lowlevel.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boards/enclustra-aa1/lowlevel.c b/arch/arm/boards/enclustra-aa1/lowlevel.c
index ada7cb5a9f..10a2095e19 100644
--- a/arch/arm/boards/enclustra-aa1/lowlevel.c
+++ b/arch/arm/boards/enclustra-aa1/lowlevel.c
@@ -110,6 +110,8 @@ ENTRY_FUNCTION_WITHSTACK(start_socfpga_aa1_bringup, ARRIA10_STACKTOP, r0, r1, r2
arria10_init(&mainpll_cfg, &perpll_cfg, pinmux);
+ arria10_watchdog_disable();
+
/* wait for fpga_usermode */
a10_wait_for_usermode(0x1000000);
--
2.43.2
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 06/14] ARM: Arria10: xload: rework __arria10_load_fpga
2024-06-17 11:36 [PATCH 00/14] ARM: SoCFPGA: arria10: clean up early bitstream loading Steffen Trumtrar
` (4 preceding siblings ...)
2024-06-17 11:36 ` [PATCH 05/14] ARM: Arria10: PE1: disable l4wd0 in bringup Steffen Trumtrar
@ 2024-06-17 11:36 ` Steffen Trumtrar
2024-06-17 11:36 ` [PATCH 07/14] ARM: arria10: xload: fix __arria10_load_fpga Steffen Trumtrar
` (8 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Steffen Trumtrar @ 2024-06-17 11:36 UTC (permalink / raw)
To: barebox; +Cc: Steffen Trumtrar
When arria10_load_fpga was reworked to try writing the FPGA multiple
times, some decisions where made regarding what is a failure and when to
try it again.
Some of these assumptions turn out to be premature optimizations that
actually make it worse:
- when a10_fpga_write returns ENOSPC this is not a reason to try
again. Just try writing the FPGA and see if it succeeds. Try again,
if that fails.
- ignore arria10_read_blocks errors (as before)
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
arch/arm/mach-socfpga/arria10-xload.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/arch/arm/mach-socfpga/arria10-xload.c b/arch/arm/mach-socfpga/arria10-xload.c
index 7b0d6f00fb..d4370945a1 100644
--- a/arch/arm/mach-socfpga/arria10-xload.c
+++ b/arch/arm/mach-socfpga/arria10-xload.c
@@ -368,13 +368,10 @@ static inline int __arria10_load_fpga(void *buf, uint32_t count, uint32_t size)
while (count <= size) {
ret = a10_fpga_write(buf, SZ_16K);
if (ret == -ENOSPC)
- return -EAGAIN;
+ break;
count += SZ_16K / SECTOR_SIZE;
ret = arria10_read_blocks(buf, count, SZ_16K);
- // Reading failed, consider this a failed attempt to configure the FPGA and retry
- if (ret)
- return -EAGAIN;
}
ret = a10_fpga_write_complete();
--
2.43.2
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 07/14] ARM: arria10: xload: fix __arria10_load_fpga
2024-06-17 11:36 [PATCH 00/14] ARM: SoCFPGA: arria10: clean up early bitstream loading Steffen Trumtrar
` (5 preceding siblings ...)
2024-06-17 11:36 ` [PATCH 06/14] ARM: Arria10: xload: rework __arria10_load_fpga Steffen Trumtrar
@ 2024-06-17 11:36 ` Steffen Trumtrar
2024-06-17 11:36 ` [PATCH 08/14] ARM: Arria10: xload: kick watchdog Steffen Trumtrar
` (7 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Steffen Trumtrar @ 2024-06-17 11:36 UTC (permalink / raw)
To: barebox; +Cc: Steffen Trumtrar
If arria10_load_fpga is called with an offset the (count < size)
comparison must handle that; increasing the count variable doesn't make
the bitstream size smaller.
As the function actually works with sectors, rename the variables to
make that clearer and add the offset to the bitstream_size to get the
correct end_sector up until __arria10_load_fpga needs to read.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
arch/arm/mach-socfpga/arria10-xload.c | 21 +++++++++++----------
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-socfpga/arria10-xload.c b/arch/arm/mach-socfpga/arria10-xload.c
index d4370945a1..e9a12ca9bb 100644
--- a/arch/arm/mach-socfpga/arria10-xload.c
+++ b/arch/arm/mach-socfpga/arria10-xload.c
@@ -353,25 +353,25 @@ int arria10_prepare_mmc(int barebox_part, int rbf_part)
return 0;
}
-static inline int __arria10_load_fpga(void *buf, uint32_t count, uint32_t size)
+static inline int __arria10_load_fpga(void *buf, uint32_t sector, uint32_t end)
{
int ret;
- arria10_read_blocks(buf, count + bitstream.first_sec, SZ_16K);
+ arria10_read_blocks(buf, sector + bitstream.first_sec, SZ_16K);
- count += SZ_16K / SECTOR_SIZE;
+ sector += SZ_16K / SECTOR_SIZE;
ret = a10_fpga_init(buf);
if (ret)
return -EAGAIN;
- while (count <= size) {
+ while (sector <= end) {
ret = a10_fpga_write(buf, SZ_16K);
if (ret == -ENOSPC)
break;
- count += SZ_16K / SECTOR_SIZE;
- ret = arria10_read_blocks(buf, count, SZ_16K);
+ sector += SZ_16K / SECTOR_SIZE;
+ ret = arria10_read_blocks(buf, sector, SZ_16K);
}
ret = a10_fpga_write_complete();
@@ -385,8 +385,8 @@ int arria10_load_fpga(int offset, int bitstream_size)
{
int ret;
void *buf = (void *)0xffe00000 + SZ_256K - 256 - SZ_16K;
- uint32_t count;
- uint32_t size = bitstream_size / SECTOR_SIZE;
+ uint32_t sector_count;
+ uint32_t end_sector = (bitstream_size + offset) / SECTOR_SIZE;
uint32_t retryCount;
if (offset)
@@ -397,9 +397,10 @@ int arria10_load_fpga(int offset, int bitstream_size)
* some margin and try up to 10 times
*/
for (retryCount = 0; retryCount < 10; ++retryCount) {
- count = offset;
- ret = __arria10_load_fpga(buf, count, size);
+ sector_count = offset;
+
+ ret = __arria10_load_fpga(buf, sector_count, end_sector);
if (!ret)
return 0;
else if (ret == -EAGAIN)
--
2.43.2
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 08/14] ARM: Arria10: xload: kick watchdog
2024-06-17 11:36 [PATCH 00/14] ARM: SoCFPGA: arria10: clean up early bitstream loading Steffen Trumtrar
` (6 preceding siblings ...)
2024-06-17 11:36 ` [PATCH 07/14] ARM: arria10: xload: fix __arria10_load_fpga Steffen Trumtrar
@ 2024-06-17 11:36 ` Steffen Trumtrar
2024-06-17 11:36 ` [PATCH 09/14] ARM: arria10: mark image in OCRAM as valid Steffen Trumtrar
` (6 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Steffen Trumtrar @ 2024-06-17 11:36 UTC (permalink / raw)
To: barebox; +Cc: Steffen Trumtrar
To be sure, that the watchdog doesn't prematurely triggers, kick it when
things are expected to take a little bit longer.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
arch/arm/mach-socfpga/arria10-xload.c | 6 ++++++
include/mach/socfpga/arria10-fpga.h | 1 +
include/mach/socfpga/generic.h | 11 +++++++++++
3 files changed, 18 insertions(+)
diff --git a/arch/arm/mach-socfpga/arria10-xload.c b/arch/arm/mach-socfpga/arria10-xload.c
index e9a12ca9bb..f846781e8f 100644
--- a/arch/arm/mach-socfpga/arria10-xload.c
+++ b/arch/arm/mach-socfpga/arria10-xload.c
@@ -46,6 +46,7 @@ static int a10_fpga_wait_for_condone(void)
if (reg & A10_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN)
return 0;
+ arria10_kick_l4wd0();
if ((reg & A10_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN) == 0)
return -EIO;
@@ -69,6 +70,7 @@ static void a10_fpga_generate_dclks(uint32_t count)
timeout = 10000000;
while (!readl(ARRIA10_FPGAMGRREGS_ADDR + A10_FPGAMGR_DCLKSTAT_OFST)) {
+ arria10_kick_l4wd0();
if (timeout-- < 0)
return;
}
@@ -357,10 +359,12 @@ static inline int __arria10_load_fpga(void *buf, uint32_t sector, uint32_t end)
{
int ret;
+ arria10_kick_l4wd0();
arria10_read_blocks(buf, sector + bitstream.first_sec, SZ_16K);
sector += SZ_16K / SECTOR_SIZE;
+ arria10_kick_l4wd0();
ret = a10_fpga_init(buf);
if (ret)
return -EAGAIN;
@@ -370,10 +374,12 @@ static inline int __arria10_load_fpga(void *buf, uint32_t sector, uint32_t end)
if (ret == -ENOSPC)
break;
+ arria10_kick_l4wd0();
sector += SZ_16K / SECTOR_SIZE;
ret = arria10_read_blocks(buf, sector, SZ_16K);
}
+ arria10_kick_l4wd0();
ret = a10_fpga_write_complete();
if (ret)
return -EAGAIN;
diff --git a/include/mach/socfpga/arria10-fpga.h b/include/mach/socfpga/arria10-fpga.h
index 3efad9a4f5..f76582eed7 100644
--- a/include/mach/socfpga/arria10-fpga.h
+++ b/include/mach/socfpga/arria10-fpga.h
@@ -20,6 +20,7 @@
#define __A10_FPGAMGR_H__
#include <linux/bitops.h>
+#include <mach/socfpga/generic.h>
#include <mach/socfpga/arria10-regs.h>
#define A10_FPGAMGR_DCLKCNT_OFST 0x08
diff --git a/include/mach/socfpga/generic.h b/include/mach/socfpga/generic.h
index 1af086140f..270c309d7b 100644
--- a/include/mach/socfpga/generic.h
+++ b/include/mach/socfpga/generic.h
@@ -3,6 +3,8 @@
#ifndef __MACH_SOCFPGA_GENERIC_H
#define __MACH_SOCFPGA_GENERIC_H
+#include <mach/socfpga/arria10-regs.h>
+#include <mach/socfpga/arria10-reset-manager.h>
#include <linux/types.h>
struct socfpga_cm_config;
@@ -57,6 +59,15 @@ int arria10_device_init(struct arria10_mainpll_cfg *mainpll,
struct arria10_perpll_cfg *perpll,
uint32_t *pinmux);
enum bootsource arria10_get_bootsource(void);
+static void inline arria10_kick_l4wd0(void)
+{
+ writel(0x76, ARRIA10_L4WD0_ADDR + 0xc);
+}
+static void inline arria10_watchdog_disable(void)
+{
+ setbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER1MODRST,
+ ARRIA10_RSTMGR_PER1MODRST_WATCHDOG0);
+}
#else
static inline void socfpga_arria10_mmc_init(void)
{
--
2.43.2
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 09/14] ARM: arria10: mark image in OCRAM as valid
2024-06-17 11:36 [PATCH 00/14] ARM: SoCFPGA: arria10: clean up early bitstream loading Steffen Trumtrar
` (7 preceding siblings ...)
2024-06-17 11:36 ` [PATCH 08/14] ARM: Arria10: xload: kick watchdog Steffen Trumtrar
@ 2024-06-17 11:36 ` Steffen Trumtrar
2024-06-17 11:36 ` [PATCH 10/14] ARM: Arria10: arria10_finish_io: remove unused param Steffen Trumtrar
` (5 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Steffen Trumtrar @ 2024-06-17 11:36 UTC (permalink / raw)
To: barebox; +Cc: Steffen Trumtrar
The bootrom checks on warm reset if there is already a valid image in
ocram and boots it. Otherwise the next boot slot is loaded.
When barebox gets to this stage, mark it as successfully loaded to ocram.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
arch/arm/mach-socfpga/arria10-generic.c | 4 ++++
include/mach/socfpga/arria10-system-manager.h | 5 +++--
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-socfpga/arria10-generic.c b/arch/arm/mach-socfpga/arria10-generic.c
index fc2ef3e292..d7ce6d84ab 100644
--- a/arch/arm/mach-socfpga/arria10-generic.c
+++ b/arch/arm/mach-socfpga/arria10-generic.c
@@ -74,6 +74,10 @@ static int arria10_generic_init(void)
pr_debug("Register restart handler\n");
restart_handler_register_fn("soc", arria10_restart_soc);
+ /* mark image in OCRAM as valid and finally disable the l4wd0 */
+ writel(ARRIA10_SYSMGR_ROM_INITSWSTATE_VALID, ARRIA10_SYSMGR_ROM_INITSWSTATE);
+ arria10_watchdog_disable();
+
return 0;
}
postcore_initcall(arria10_generic_init);
diff --git a/include/mach/socfpga/arria10-system-manager.h b/include/mach/socfpga/arria10-system-manager.h
index 536baf6bc3..b0654408a5 100644
--- a/include/mach/socfpga/arria10-system-manager.h
+++ b/include/mach/socfpga/arria10-system-manager.h
@@ -52,7 +52,8 @@
#define ARRIA10_SYSMGR_NOC_IDLESTATUS (ARRIA10_SYSMGR_ADDR + 0xd4)
#define ARRIA10_SYSMGR_FPGA2SOC_CTRL (ARRIA10_SYSMGR_ADDR + 0xd8)
-#define ARRIA10_SYSMGR_ROM_INITSWLASTLD (ARRIA10_SYSMGR_ADDR + 0x10)
+#define ARRIA10_SYSMGR_ROM_INITSWSTATE (ARRIA10_SYSMGR_ADDR + 0x20c)
+#define ARRIA10_SYSMGR_ROM_INITSWLASTLD (ARRIA10_SYSMGR_ADDR + 0x210)
#define ARRIA10_SYSMGR_ROM_ISW0 (ARRIA10_SYSMGR_ADDR + 0x230)
#define ARRIA10_SYSMGR_ROM_ISW1 (ARRIA10_SYSMGR_ADDR + 0x234)
#define ARRIA10_SYSMGR_ROM_ISW2 (ARRIA10_SYSMGR_ADDR + 0x238)
@@ -62,7 +63,7 @@
#define ARRIA10_SYSMGR_ROM_ISW6 (ARRIA10_SYSMGR_ADDR + 0x248)
#define ARRIA10_SYSMGR_ROM_ISW7 (ARRIA10_SYSMGR_ADDR + 0x24c)
-
+#define ARRIA10_SYSMGR_ROM_INITSWSTATE_VALID 0x49535756
#define ARRIA10_SYSMGR_BOOTINFO_BSEL_MASK 0x00007000
#define ARRIA10_SYSMGR_BOOTINFO_BSEL_SHIFT 12
--
2.43.2
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 10/14] ARM: Arria10: arria10_finish_io: remove unused param
2024-06-17 11:36 [PATCH 00/14] ARM: SoCFPGA: arria10: clean up early bitstream loading Steffen Trumtrar
` (8 preceding siblings ...)
2024-06-17 11:36 ` [PATCH 09/14] ARM: arria10: mark image in OCRAM as valid Steffen Trumtrar
@ 2024-06-17 11:36 ` Steffen Trumtrar
2024-06-17 11:36 ` [PATCH 11/14] ARM: Arria10: xload: remove useless writel Steffen Trumtrar
` (4 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Steffen Trumtrar @ 2024-06-17 11:36 UTC (permalink / raw)
To: barebox; +Cc: Steffen Trumtrar
arria10_finish_io() doesn't use mainpll_cfg, perpll_cfg.
Remove them from the parameter list.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
arch/arm/boards/enclustra-aa1/lowlevel.c | 4 ++--
arch/arm/boards/reflex-achilles/lowlevel.c | 4 ++--
arch/arm/mach-socfpga/arria10-init.c | 4 +---
include/mach/socfpga/generic.h | 3 +--
4 files changed, 6 insertions(+), 9 deletions(-)
diff --git a/arch/arm/boards/enclustra-aa1/lowlevel.c b/arch/arm/boards/enclustra-aa1/lowlevel.c
index 10a2095e19..fc6b2779c9 100644
--- a/arch/arm/boards/enclustra-aa1/lowlevel.c
+++ b/arch/arm/boards/enclustra-aa1/lowlevel.c
@@ -83,7 +83,7 @@ ENTRY_FUNCTION_WITHSTACK(start_socfpga_aa1_xload, ARRIA10_STACKTOP, r0, r1, r2)
arria10_load_fpga(bitstream, SZ_32M);
- arria10_finish_io(&mainpll_cfg, &perpll_cfg, pinmux);
+ arria10_finish_io(pinmux);
arria10_ddr_calibration_sequence();
@@ -115,7 +115,7 @@ ENTRY_FUNCTION_WITHSTACK(start_socfpga_aa1_bringup, ARRIA10_STACKTOP, r0, r1, r2
/* wait for fpga_usermode */
a10_wait_for_usermode(0x1000000);
- arria10_finish_io(&mainpll_cfg, &perpll_cfg, pinmux);
+ arria10_finish_io(pinmux);
arria10_ddr_calibration_sequence();
diff --git a/arch/arm/boards/reflex-achilles/lowlevel.c b/arch/arm/boards/reflex-achilles/lowlevel.c
index 12ead6d6dd..a6548605ec 100644
--- a/arch/arm/boards/reflex-achilles/lowlevel.c
+++ b/arch/arm/boards/reflex-achilles/lowlevel.c
@@ -74,7 +74,7 @@ ENTRY_FUNCTION_WITHSTACK(start_socfpga_achilles_xload, ARRIA10_STACKTOP, r0, r1,
arria10_load_fpga(bitstream, SZ_64M);
- arria10_finish_io(&mainpll_cfg, &perpll_cfg, pinmux);
+ arria10_finish_io(pinmux);
arria10_ddr_calibration_sequence();
@@ -105,7 +105,7 @@ ENTRY_FUNCTION_WITHSTACK(start_socfpga_achilles_bringup, ARRIA10_STACKTOP, r0, r
/* wait for fpga_usermode */
a10_wait_for_usermode(0x1000000);
- arria10_finish_io(&mainpll_cfg, &perpll_cfg, pinmux);
+ arria10_finish_io(pinmux);
arria10_ddr_calibration_sequence();
diff --git a/arch/arm/mach-socfpga/arria10-init.c b/arch/arm/mach-socfpga/arria10-init.c
index d1586c2d40..f8a15ec8b4 100644
--- a/arch/arm/mach-socfpga/arria10-init.c
+++ b/arch/arm/mach-socfpga/arria10-init.c
@@ -127,9 +127,7 @@ static void arria10_mask_ecc_errors(void)
writel(0x0007FFFF, ARRIA10_SYSMGR_ADDR + 0x94);
}
-void arria10_finish_io(struct arria10_mainpll_cfg *mainpll,
- struct arria10_perpll_cfg *perpll,
- uint32_t *pinmux)
+void arria10_finish_io(uint32_t *pinmux)
{
int i;
diff --git a/include/mach/socfpga/generic.h b/include/mach/socfpga/generic.h
index 270c309d7b..23fcdabc3e 100644
--- a/include/mach/socfpga/generic.h
+++ b/include/mach/socfpga/generic.h
@@ -17,8 +17,7 @@ struct arria10_pinmux_cfg;
void arria10_init(struct arria10_mainpll_cfg *mainpll,
struct arria10_perpll_cfg *perpll, uint32_t *pinmux);
-void arria10_finish_io(struct arria10_mainpll_cfg *mainpll,
- struct arria10_perpll_cfg *perpll, uint32_t *pinmux);
+void arria10_finish_io(uint32_t *pinmux);
void socfpga_lowlevel_init(struct socfpga_cm_config *cm_config,
struct socfpga_io_config *io_config);
--
2.43.2
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 11/14] ARM: Arria10: xload: remove useless writel
2024-06-17 11:36 [PATCH 00/14] ARM: SoCFPGA: arria10: clean up early bitstream loading Steffen Trumtrar
` (9 preceding siblings ...)
2024-06-17 11:36 ` [PATCH 10/14] ARM: Arria10: arria10_finish_io: remove unused param Steffen Trumtrar
@ 2024-06-17 11:36 ` Steffen Trumtrar
2024-06-17 11:36 ` [PATCH 12/14] ARM: Arria10: xload: refactor wait loops Steffen Trumtrar
` (3 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Steffen Trumtrar @ 2024-06-17 11:36 UTC (permalink / raw)
To: barebox; +Cc: Steffen Trumtrar
0xffd0628 is a handoff register. This looks like a debugging writel that
was accidentally commited, as the write to this register is useless otherwise.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
arch/arm/mach-socfpga/arria10-xload.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/arm/mach-socfpga/arria10-xload.c b/arch/arm/mach-socfpga/arria10-xload.c
index f846781e8f..22b23d2dc7 100644
--- a/arch/arm/mach-socfpga/arria10-xload.c
+++ b/arch/arm/mach-socfpga/arria10-xload.c
@@ -220,10 +220,8 @@ static int a10_fpga_init(void *buf)
/* wait for nstatus == 1 */
timeout = 1000000;
while ((socfpga_a10_fpga_read_stat() & mask) != mask) {
- if (timeout-- < 0) {
- writel(socfpga_a10_fpga_read_stat(), 0xFFD06238);
+ if (timeout-- < 0)
return -ETIMEDOUT;
- }
}
stat = socfpga_a10_fpga_read_stat();
--
2.43.2
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 12/14] ARM: Arria10: xload: refactor wait loops
2024-06-17 11:36 [PATCH 00/14] ARM: SoCFPGA: arria10: clean up early bitstream loading Steffen Trumtrar
` (10 preceding siblings ...)
2024-06-17 11:36 ` [PATCH 11/14] ARM: Arria10: xload: remove useless writel Steffen Trumtrar
@ 2024-06-17 11:36 ` Steffen Trumtrar
2024-06-17 11:36 ` [PATCH 13/14] ARM: Arria10: xload: reduce timeout on condone Steffen Trumtrar
` (2 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Steffen Trumtrar @ 2024-06-17 11:36 UTC (permalink / raw)
To: barebox; +Cc: Steffen Trumtrar
wait_on_timeout uses get_time_ns() which we don't have.
Instead define our own variant of wait_on_timeout() and replace all wait
loops with this one define.
While at it, reduce the "chosen-by-dice" timeouts where appropriate
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
arch/arm/mach-socfpga/arria10-xload.c | 55 +++++++++++++++--------------------
1 file changed, 24 insertions(+), 31 deletions(-)
diff --git a/arch/arm/mach-socfpga/arria10-xload.c b/arch/arm/mach-socfpga/arria10-xload.c
index 22b23d2dc7..5ec6e93e96 100644
--- a/arch/arm/mach-socfpga/arria10-xload.c
+++ b/arch/arm/mach-socfpga/arria10-xload.c
@@ -16,6 +16,22 @@
#include <mach/socfpga/generic.h>
#include <linux/sizes.h>
+#define __wait_on_timeout(timeout, condition) \
+({ \
+ int __ret = 0; \
+ int __timeout = timeout; \
+ \
+ while ((condition)) { \
+ if (__timeout-- < 0) { \
+ __ret = -ETIMEDOUT; \
+ break; \
+ } \
+ arria10_kick_l4wd0(); \
+ __udelay(1); \
+ } \
+ __ret; \
+})
+
int a10_update_bits(unsigned int reg, unsigned int mask,
unsigned int val)
{
@@ -57,8 +73,6 @@ static int a10_fpga_wait_for_condone(void)
static void a10_fpga_generate_dclks(uint32_t count)
{
- int32_t timeout;
-
/* Clear any existing DONE status. */
writel(A10_FPGAMGR_DCLKSTAT_DCLKDONE, ARRIA10_FPGAMGRREGS_ADDR +
A10_FPGAMGR_DCLKSTAT_OFST);
@@ -67,13 +81,9 @@ static void a10_fpga_generate_dclks(uint32_t count)
writel(count, ARRIA10_FPGAMGRREGS_ADDR + A10_FPGAMGR_DCLKCNT_OFST);
/* wait till the dclkcnt done */
- timeout = 10000000;
-
- while (!readl(ARRIA10_FPGAMGRREGS_ADDR + A10_FPGAMGR_DCLKSTAT_OFST)) {
- arria10_kick_l4wd0();
- if (timeout-- < 0)
- return;
- }
+ __wait_on_timeout(1000,
+ !readl(ARRIA10_FPGAMGRREGS_ADDR +
+ A10_FPGAMGR_DCLKSTAT_OFST));
/* Clear DONE status. */
writel(A10_FPGAMGR_DCLKSTAT_DCLKDONE, ARRIA10_FPGAMGRREGS_ADDR +
@@ -140,7 +150,6 @@ static int a10_fpga_init(void *buf)
{
uint32_t stat, mask;
uint32_t val;
- int timeout;
val = CFGWDTH_32 << A10_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SHIFT;
a10_update_bits(A10_FPGAMGR_IMGCFG_CTL_02_OFST,
@@ -151,11 +160,7 @@ static int a10_fpga_init(void *buf)
mask = A10_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN |
A10_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN;
/* Make sure no external devices are interfering */
- timeout = 10000;
- while ((socfpga_a10_fpga_read_stat() & mask) != mask) {
- if (timeout-- < 0)
- return -ETIMEDOUT;
- }
+ __wait_on_timeout(100000, (socfpga_a10_fpga_read_stat() & mask) != mask);
/* S2F_NCE = 1 */
a10_update_bits(A10_FPGAMGR_IMGCFG_CTL_01_OFST,
@@ -195,22 +200,14 @@ static int a10_fpga_init(void *buf)
mask = A10_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN |
A10_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN;
- timeout = 100000;
- while ((socfpga_a10_fpga_read_stat() & mask) != mask) {
- if (timeout-- < 0)
- return -ETIMEDOUT;
- }
+ __wait_on_timeout(100000, (socfpga_a10_fpga_read_stat() & mask) != mask);
/* reset the configuration */
a10_update_bits(A10_FPGAMGR_IMGCFG_CTL_00_OFST,
A10_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG, 0);
- timeout = 1000000;
- while ((socfpga_a10_fpga_read_stat() &
- A10_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN) != 0) {
- if (timeout-- < 0)
- return -ETIMEDOUT;
- }
+ mask = A10_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN;
+ __wait_on_timeout(100000, (socfpga_a10_fpga_read_stat() & mask) != 0);
a10_update_bits(A10_FPGAMGR_IMGCFG_CTL_00_OFST,
A10_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG,
@@ -218,11 +215,7 @@ static int a10_fpga_init(void *buf)
mask = A10_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN;
/* wait for nstatus == 1 */
- timeout = 1000000;
- while ((socfpga_a10_fpga_read_stat() & mask) != mask) {
- if (timeout-- < 0)
- return -ETIMEDOUT;
- }
+ __wait_on_timeout(100000, (socfpga_a10_fpga_read_stat() & mask) != mask);
stat = socfpga_a10_fpga_read_stat();
if ((stat & A10_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN) != 0)
--
2.43.2
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 13/14] ARM: Arria10: xload: reduce timeout on condone
2024-06-17 11:36 [PATCH 00/14] ARM: SoCFPGA: arria10: clean up early bitstream loading Steffen Trumtrar
` (11 preceding siblings ...)
2024-06-17 11:36 ` [PATCH 12/14] ARM: Arria10: xload: refactor wait loops Steffen Trumtrar
@ 2024-06-17 11:36 ` Steffen Trumtrar
2024-06-17 11:36 ` [PATCH 14/14] ARM: arria10-xload: rework broken bitstream handling Steffen Trumtrar
2024-06-18 6:48 ` [PATCH 00/14] ARM: SoCFPGA: arria10: clean up early bitstream loading Sascha Hauer
14 siblings, 0 replies; 16+ messages in thread
From: Steffen Trumtrar @ 2024-06-17 11:36 UTC (permalink / raw)
To: barebox; +Cc: Steffen Trumtrar
Reduce the timeout while waiting for condone pin.
Also, kick the l4wd0 while waiting.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
arch/arm/mach-socfpga/arria10-xload.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-socfpga/arria10-xload.c b/arch/arm/mach-socfpga/arria10-xload.c
index 5ec6e93e96..3921ace3aa 100644
--- a/arch/arm/mach-socfpga/arria10-xload.c
+++ b/arch/arm/mach-socfpga/arria10-xload.c
@@ -57,15 +57,17 @@ static int a10_fpga_wait_for_condone(void)
{
u32 reg, i;
- for (i = 0; i < 0x1000000 ; i++) {
+ for (i = 0; i < 1000; i++) {
reg = socfpga_a10_fpga_read_stat();
if (reg & A10_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN)
return 0;
- arria10_kick_l4wd0();
if ((reg & A10_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN) == 0)
return -EIO;
+
+ arria10_kick_l4wd0();
+ __udelay(1);
}
return -ETIMEDOUT;
--
2.43.2
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 14/14] ARM: arria10-xload: rework broken bitstream handling
2024-06-17 11:36 [PATCH 00/14] ARM: SoCFPGA: arria10: clean up early bitstream loading Steffen Trumtrar
` (12 preceding siblings ...)
2024-06-17 11:36 ` [PATCH 13/14] ARM: Arria10: xload: reduce timeout on condone Steffen Trumtrar
@ 2024-06-17 11:36 ` Steffen Trumtrar
2024-06-18 6:48 ` [PATCH 00/14] ARM: SoCFPGA: arria10: clean up early bitstream loading Sascha Hauer
14 siblings, 0 replies; 16+ messages in thread
From: Steffen Trumtrar @ 2024-06-17 11:36 UTC (permalink / raw)
To: barebox; +Cc: Steffen Trumtrar
When after 10 tries, the bitstream still couldn't be loaded, mark the
boot as failed in ARRIA10_SYSMGR_ROM_INITSWSTATE.
This information can be retrieved on barebox start (in lowlevel.c) to
decide what to do.
The bootROM will *not* boot the next boot slot, but will just try again
booting the failed bootloader slot.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
arch/arm/mach-socfpga/arria10-xload.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-socfpga/arria10-xload.c b/arch/arm/mach-socfpga/arria10-xload.c
index 3921ace3aa..afec55c33a 100644
--- a/arch/arm/mach-socfpga/arria10-xload.c
+++ b/arch/arm/mach-socfpga/arria10-xload.c
@@ -364,7 +364,7 @@ static inline int __arria10_load_fpga(void *buf, uint32_t sector, uint32_t end)
while (sector <= end) {
ret = a10_fpga_write(buf, SZ_16K);
- if (ret == -ENOSPC)
+ if (ret)
break;
arria10_kick_l4wd0();
@@ -375,7 +375,7 @@ static inline int __arria10_load_fpga(void *buf, uint32_t sector, uint32_t end)
arria10_kick_l4wd0();
ret = a10_fpga_write_complete();
if (ret)
- return -EAGAIN;
+ return ret;
return 0;
}
@@ -391,6 +391,8 @@ int arria10_load_fpga(int offset, int bitstream_size)
if (offset)
offset = offset / SECTOR_SIZE;
+ writel(0x0, ARRIA10_SYSMGR_ROM_ISW7);
+
/* Up to 4 retries have been seen on the Enclustra Mercury AA1+ board, as
* FPGA configuration is mandatory to be able to continue the boot, take
* some margin and try up to 10 times
@@ -402,10 +404,14 @@ int arria10_load_fpga(int offset, int bitstream_size)
ret = __arria10_load_fpga(buf, sector_count, end_sector);
if (!ret)
return 0;
+ else if (ret == -EIO)
+ break;
else if (ret == -EAGAIN)
continue;
}
+ writel(0x64616544, ARRIA10_SYSMGR_ROM_ISW7);
+
hang();
return -EIO;
}
--
2.43.2
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 00/14] ARM: SoCFPGA: arria10: clean up early bitstream loading
2024-06-17 11:36 [PATCH 00/14] ARM: SoCFPGA: arria10: clean up early bitstream loading Steffen Trumtrar
` (13 preceding siblings ...)
2024-06-17 11:36 ` [PATCH 14/14] ARM: arria10-xload: rework broken bitstream handling Steffen Trumtrar
@ 2024-06-18 6:48 ` Sascha Hauer
14 siblings, 0 replies; 16+ messages in thread
From: Sascha Hauer @ 2024-06-18 6:48 UTC (permalink / raw)
To: barebox, Steffen Trumtrar
On Mon, 17 Jun 2024 13:36:22 +0200, Steffen Trumtrar wrote:
> This series cleans up/reworks the early bitstream loading in the Arria10
> xloader code.
>
> Some useful defines are added on the way.
>
>
>
> [...]
Applied, thanks!
[01/14] ARM: arria10: system-manager: add handoff registers
https://git.pengutronix.de/cgit/barebox/commit/?id=b22ad95de63c (link may not be stable)
[02/14] ARM: Arria10: reset manager: document reset source
https://git.pengutronix.de/cgit/barebox/commit/?id=9c1fba4af288 (link may not be stable)
[03/14] ARM: socfpga: Arria10: PE1: remove arm_cpu_lowlevel_init
https://git.pengutronix.de/cgit/barebox/commit/?id=29de11adfc0e (link may not be stable)
[04/14] ARM: arria10: reset-manager: don't touch l4 wdog
https://git.pengutronix.de/cgit/barebox/commit/?id=8b89da8eafe2 (link may not be stable)
[05/14] ARM: Arria10: PE1: disable l4wd0 in bringup
https://git.pengutronix.de/cgit/barebox/commit/?id=2d17c531768c (link may not be stable)
[06/14] ARM: Arria10: xload: rework __arria10_load_fpga
https://git.pengutronix.de/cgit/barebox/commit/?id=974d9d7892cc (link may not be stable)
[07/14] ARM: arria10: xload: fix __arria10_load_fpga
https://git.pengutronix.de/cgit/barebox/commit/?id=050398e77dc1 (link may not be stable)
[08/14] ARM: Arria10: xload: kick watchdog
https://git.pengutronix.de/cgit/barebox/commit/?id=ed3372c6e07e (link may not be stable)
[09/14] ARM: arria10: mark image in OCRAM as valid
https://git.pengutronix.de/cgit/barebox/commit/?id=b06718ef03d2 (link may not be stable)
[10/14] ARM: Arria10: arria10_finish_io: remove unused param
https://git.pengutronix.de/cgit/barebox/commit/?id=eb720580ca67 (link may not be stable)
[11/14] ARM: Arria10: xload: remove useless writel
https://git.pengutronix.de/cgit/barebox/commit/?id=5698989b30c4 (link may not be stable)
[12/14] ARM: Arria10: xload: refactor wait loops
https://git.pengutronix.de/cgit/barebox/commit/?id=11e342fb4227 (link may not be stable)
[13/14] ARM: Arria10: xload: reduce timeout on condone
https://git.pengutronix.de/cgit/barebox/commit/?id=fd0ed4c334c0 (link may not be stable)
[14/14] ARM: arria10-xload: rework broken bitstream handling
https://git.pengutronix.de/cgit/barebox/commit/?id=7ead869ce2ab (link may not be stable)
Best regards,
--
Sascha Hauer <s.hauer@pengutronix.de>
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2024-06-18 6:49 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-06-17 11:36 [PATCH 00/14] ARM: SoCFPGA: arria10: clean up early bitstream loading Steffen Trumtrar
2024-06-17 11:36 ` [PATCH 01/14] ARM: arria10: system-manager: add handoff registers Steffen Trumtrar
2024-06-17 11:36 ` [PATCH 02/14] ARM: Arria10: reset manager: document reset source Steffen Trumtrar
2024-06-17 11:36 ` [PATCH 03/14] ARM: socfpga: Arria10: PE1: remove arm_cpu_lowlevel_init Steffen Trumtrar
2024-06-17 11:36 ` [PATCH 04/14] ARM: arria10: reset-manager: don't touch l4 wdog Steffen Trumtrar
2024-06-17 11:36 ` [PATCH 05/14] ARM: Arria10: PE1: disable l4wd0 in bringup Steffen Trumtrar
2024-06-17 11:36 ` [PATCH 06/14] ARM: Arria10: xload: rework __arria10_load_fpga Steffen Trumtrar
2024-06-17 11:36 ` [PATCH 07/14] ARM: arria10: xload: fix __arria10_load_fpga Steffen Trumtrar
2024-06-17 11:36 ` [PATCH 08/14] ARM: Arria10: xload: kick watchdog Steffen Trumtrar
2024-06-17 11:36 ` [PATCH 09/14] ARM: arria10: mark image in OCRAM as valid Steffen Trumtrar
2024-06-17 11:36 ` [PATCH 10/14] ARM: Arria10: arria10_finish_io: remove unused param Steffen Trumtrar
2024-06-17 11:36 ` [PATCH 11/14] ARM: Arria10: xload: remove useless writel Steffen Trumtrar
2024-06-17 11:36 ` [PATCH 12/14] ARM: Arria10: xload: refactor wait loops Steffen Trumtrar
2024-06-17 11:36 ` [PATCH 13/14] ARM: Arria10: xload: reduce timeout on condone Steffen Trumtrar
2024-06-17 11:36 ` [PATCH 14/14] ARM: arria10-xload: rework broken bitstream handling Steffen Trumtrar
2024-06-18 6:48 ` [PATCH 00/14] ARM: SoCFPGA: arria10: clean up early bitstream loading Sascha Hauer
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox