From: Sascha Hauer <s.hauer@pengutronix.de>
To: "open list:BAREBOX" <barebox@lists.infradead.org>
Subject: [PATCH v2 06/12] ARM: Layerscape: remove register arguments
Date: Tue, 22 Oct 2024 09:46:30 +0200 [thread overview]
Message-ID: <20241022-arm-layerscape-tfa-v2-6-69ac70ceb0ff@pengutronix.de> (raw)
In-Reply-To: <20241022-arm-layerscape-tfa-v2-0-69ac70ceb0ff@pengutronix.de>
The various Layerscape xload_start_image functions all take r0, r1 and
r2 arguments. These are all unused in the code, so remove them.
The ls1021aiot board passes the memory size in r0 in one case, but this
is never used, so it's safe to remove that as well.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/ls1021aiot/lowlevel.c | 6 +++---
arch/arm/boards/ls1046ardb/lowlevel.c | 6 +++---
arch/arm/boards/tqmls1046a/lowlevel.c | 10 +++++-----
arch/arm/mach-layerscape/xload-qspi.c | 17 +++++++----------
arch/arm/mach-layerscape/xload.c | 12 +++++-------
drivers/mci/imx-esdhc-pbl.c | 10 ++++------
include/mach/layerscape/xload.h | 14 +++++---------
7 files changed, 32 insertions(+), 43 deletions(-)
diff --git a/arch/arm/boards/ls1021aiot/lowlevel.c b/arch/arm/boards/ls1021aiot/lowlevel.c
index d2d4237c3d..887f0e39db 100644
--- a/arch/arm/boards/ls1021aiot/lowlevel.c
+++ b/arch/arm/boards/ls1021aiot/lowlevel.c
@@ -97,7 +97,7 @@ static noinline __noreturn void ls1021aiot_r_entry(void)
ls1021a_errata_post_ddr();
- ls1021a_xload_start_image(SZ_1G, 0, 0);
+ ls1021a_xload_start_image();
pr_err("Booting failed\n");
@@ -105,10 +105,10 @@ static noinline __noreturn void ls1021aiot_r_entry(void)
;
}
-void ls1021aiot_entry(unsigned long r0, unsigned long r1, unsigned long r2);
+void ls1021aiot_entry(void);
__noreturn void
-ls1021aiot_entry(unsigned long r0, unsigned long r1, unsigned long r2)
+ls1021aiot_entry(void)
{
relocate_to_current_adr();
setup_c();
diff --git a/arch/arm/boards/ls1046ardb/lowlevel.c b/arch/arm/boards/ls1046ardb/lowlevel.c
index 9c3f1a8375..753fca3272 100644
--- a/arch/arm/boards/ls1046ardb/lowlevel.c
+++ b/arch/arm/boards/ls1046ardb/lowlevel.c
@@ -210,7 +210,7 @@ static noinline __noreturn void ls1046ardb_r_entry(void)
ls1046a_errata_post_ddr();
- ls1046a_esdhc_start_image(0, 0, 0);
+ ls1046a_esdhc_start_image();
err:
pr_err("Booting failed\n");
@@ -218,9 +218,9 @@ static noinline __noreturn void ls1046ardb_r_entry(void)
while (1);
}
-void ls1046ardb_entry(unsigned long r0, unsigned long r1, unsigned long r2);
+void ls1046ardb_entry(void);
-__noreturn void ls1046ardb_entry(unsigned long r0, unsigned long r1, unsigned long r2)
+__noreturn void ls1046ardb_entry(void)
{
relocate_to_current_adr();
setup_c();
diff --git a/arch/arm/boards/tqmls1046a/lowlevel.c b/arch/arm/boards/tqmls1046a/lowlevel.c
index 9f471d001e..6531b22bd1 100644
--- a/arch/arm/boards/tqmls1046a/lowlevel.c
+++ b/arch/arm/boards/tqmls1046a/lowlevel.c
@@ -331,16 +331,16 @@ static noinline __noreturn void tqmls1046a_r_entry(bool is_8g)
ls1046a_errata_post_ddr();
- ls1046a_xload_start_image(0, 0, 0);
+ ls1046a_xload_start_image();
pr_err("Booting failed\n");
while (1);
}
-void tqmls1046a_entry(unsigned long r0, unsigned long r1, unsigned long r2);
+void tqmls1046a_entry(void);
-__noreturn void tqmls1046a_entry(unsigned long r0, unsigned long r1, unsigned long r2)
+__noreturn void tqmls1046a_entry(void)
{
relocate_to_current_adr();
setup_c();
@@ -348,9 +348,9 @@ __noreturn void tqmls1046a_entry(unsigned long r0, unsigned long r1, unsigned lo
tqmls1046a_r_entry(false);
}
-void tqmls1046a_8g_entry(unsigned long r0, unsigned long r1, unsigned long r2);
+void tqmls1046a_8g_entry(void);
-__noreturn void tqmls1046a_8g_entry(unsigned long r0, unsigned long r1, unsigned long r2)
+__noreturn void tqmls1046a_8g_entry(void)
{
relocate_to_current_adr();
setup_c();
diff --git a/arch/arm/mach-layerscape/xload-qspi.c b/arch/arm/mach-layerscape/xload-qspi.c
index 608434bf1f..11119840c3 100644
--- a/arch/arm/mach-layerscape/xload-qspi.c
+++ b/arch/arm/mach-layerscape/xload-qspi.c
@@ -19,10 +19,9 @@ struct layerscape_base_addr {
void *qspi_mem_base;
};
-static int layerscape_qspi_start_image(struct layerscape_base_addr *base,
- unsigned long r0, unsigned long r1, unsigned long r2)
+static int layerscape_qspi_start_image(struct layerscape_base_addr *base)
{
- void (*barebox)(unsigned long, unsigned long, unsigned long) = base->membase;
+ void (*barebox)(void) = base->membase;
/* Switch controller into little endian mode */
out_be32(base->qspi_reg_base, 0x000f400c);
@@ -33,15 +32,14 @@ static int layerscape_qspi_start_image(struct layerscape_base_addr *base,
printf("Starting barebox\n");
- barebox(r0, r1, r2);
+ barebox();
printf("failed\n");
return -EIO;
}
-int ls1046a_qspi_start_image(unsigned long r0, unsigned long r1,
- unsigned long r2)
+int ls1046a_qspi_start_image(void)
{
struct layerscape_base_addr base;
@@ -49,11 +47,10 @@ int ls1046a_qspi_start_image(unsigned long r0, unsigned long r1,
base.membase = IOMEM(LS1046A_DDR_SDRAM_BASE);
base.qspi_mem_base = IOMEM(0x40000000);
- return layerscape_qspi_start_image(&base, r0, r1, r2);
+ return layerscape_qspi_start_image(&base);
}
-int ls1021a_qspi_start_image(unsigned long r0, unsigned long r1,
- unsigned long r2)
+int ls1021a_qspi_start_image(void)
{
struct layerscape_base_addr base;
@@ -61,5 +58,5 @@ int ls1021a_qspi_start_image(unsigned long r0, unsigned long r1,
base.membase = IOMEM(LS1021A_DDR_SDRAM_BASE);
base.qspi_mem_base = IOMEM(0x40000000);
- return layerscape_qspi_start_image(&base, r0, r1, r2);
+ return layerscape_qspi_start_image(&base);
}
diff --git a/arch/arm/mach-layerscape/xload.c b/arch/arm/mach-layerscape/xload.c
index 32ff158b1b..9103e8b4bc 100644
--- a/arch/arm/mach-layerscape/xload.c
+++ b/arch/arm/mach-layerscape/xload.c
@@ -5,8 +5,7 @@
#include <mach/layerscape/layerscape.h>
#include <mach/layerscape/xload.h>
-int ls1046a_xload_start_image(unsigned long r0, unsigned long r1,
- unsigned long r2)
+int ls1046a_xload_start_image(void)
{
enum bootsource src;
@@ -14,10 +13,10 @@ int ls1046a_xload_start_image(unsigned long r0, unsigned long r1,
switch (src) {
case BOOTSOURCE_SPI_NOR:
- return ls1046a_qspi_start_image(r0, r1, r2);
+ return ls1046a_qspi_start_image();
#if defined(CONFIG_MCI_IMX_ESDHC_PBL)
case BOOTSOURCE_MMC:
- return ls1046a_esdhc_start_image(r0, r1, r2);
+ return ls1046a_esdhc_start_image();
#endif
default:
pr_err("Unknown bootsource\n");
@@ -25,8 +24,7 @@ int ls1046a_xload_start_image(unsigned long r0, unsigned long r1,
}
}
-int ls1021a_xload_start_image(unsigned long r0, unsigned long r1,
- unsigned long r2)
+int ls1021a_xload_start_image(void)
{
enum bootsource src;
@@ -34,7 +32,7 @@ int ls1021a_xload_start_image(unsigned long r0, unsigned long r1,
switch (src) {
case BOOTSOURCE_SPI_NOR:
- return ls1021a_qspi_start_image(r0, r1, r2);
+ return ls1021a_qspi_start_image();
default:
pr_err("Unknown bootsource\n");
return -EINVAL;
diff --git a/drivers/mci/imx-esdhc-pbl.c b/drivers/mci/imx-esdhc-pbl.c
index 5b1d9a3cf4..3bf3a7ace6 100644
--- a/drivers/mci/imx-esdhc-pbl.c
+++ b/drivers/mci/imx-esdhc-pbl.c
@@ -352,7 +352,7 @@ static int layerscape_esdhc_load_image(struct fsl_esdhc_host *host, void *adr, u
* Return: If successful, this function does not return. A negative error
* code is returned when this function fails.
*/
-int ls1046a_esdhc_start_image(unsigned long r0, unsigned long r1, unsigned long r2)
+int ls1046a_esdhc_start_image(void)
{
int ret;
struct esdhc_soc_data data = {
@@ -364,8 +364,7 @@ int ls1046a_esdhc_start_image(unsigned long r0, unsigned long r1, unsigned long
};
void *sdram = (void *)0x80000000;
unsigned long size = ALIGN(barebox_image_size + LS1046A_SD_IMAGE_OFFSET, 512);
- void (*barebox)(unsigned long, unsigned long, unsigned long) =
- (sdram + LS1046A_SD_IMAGE_OFFSET);
+ void (*barebox)(void) = (sdram + LS1046A_SD_IMAGE_OFFSET);
ret = layerscape_esdhc_load_image(&host, sdram, size, (8 << 8) | (3 << 4));
if (ret)
@@ -373,7 +372,7 @@ int ls1046a_esdhc_start_image(unsigned long r0, unsigned long r1, unsigned long
printf("Starting barebox\n");
- barebox(r0, r1, r2);
+ barebox();
return -EINVAL;
}
@@ -393,8 +392,7 @@ static int ls1028a_esdhc_start_image(void __iomem *base, struct dram_regions_inf
void *bl31_image;
struct bl2_to_bl31_params_mem_v2 *params;
unsigned long size = ALIGN(barebox_image_size + LS1046A_SD_IMAGE_OFFSET, 512);
- void (*barebox)(unsigned long, unsigned long, unsigned long) =
- (sdram + LS1046A_SD_IMAGE_OFFSET);
+ void (*barebox)(void) = (sdram + LS1046A_SD_IMAGE_OFFSET);
int ret;
ret = layerscape_esdhc_load_image(&host, sdram, size, 8 << 4);
diff --git a/include/mach/layerscape/xload.h b/include/mach/layerscape/xload.h
index 86327c63e6..64990e2ca1 100644
--- a/include/mach/layerscape/xload.h
+++ b/include/mach/layerscape/xload.h
@@ -5,16 +5,12 @@
struct dram_regions_info;
-int ls1046a_esdhc_start_image(unsigned long r0, unsigned long r1, unsigned long r2);
+int ls1046a_esdhc_start_image(void);
int ls1028a_esdhc1_start_image(struct dram_regions_info *dram_info);
int ls1028a_esdhc2_start_image(struct dram_regions_info *dram_info);
-int ls1046a_qspi_start_image(unsigned long r0, unsigned long r1,
- unsigned long r2);
-int ls1021a_qspi_start_image(unsigned long r0, unsigned long r1,
- unsigned long r2);
-int ls1046a_xload_start_image(unsigned long r0, unsigned long r1,
- unsigned long r2);
-int ls1021a_xload_start_image(unsigned long r0, unsigned long r1,
- unsigned long r2);
+int ls1046a_qspi_start_image(void);
+int ls1021a_qspi_start_image(void);
+int ls1046a_xload_start_image(void);
+int ls1021a_xload_start_image(void);
#endif /* __MACH_LAYERSCAPE_XLOAD_H */
--
2.39.5
next prev parent reply other threads:[~2024-10-22 7:49 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-22 7:46 [PATCH v2 00/12] ARM: Layerscape: LS1046a: switch to TF-A Sascha Hauer
2024-10-22 7:46 ` [PATCH v2 01/12] ARM: Layerscape: TQMLS1046a: Update DDR timings Sascha Hauer
2024-10-22 7:46 ` [PATCH v2 02/12] ARM: Layerscape: images: fix variable name Sascha Hauer
2024-10-22 7:46 ` [PATCH v2 03/12] ARM: Layerscape: images: add missing FORCE Sascha Hauer
2024-10-22 7:46 ` [PATCH v2 04/12] ARM: Layerscape: TQMLS1046a: add support for 8GiB variant Sascha Hauer
2024-10-22 7:46 ` [PATCH v2 05/12] ARM: Layerscape: ls1046ardb: remove unused variable Sascha Hauer
2024-10-22 7:46 ` Sascha Hauer [this message]
2024-10-22 7:46 ` [PATCH v2 07/12] ARM: Layerscape: LS1046a: add TF-A support Sascha Hauer
2024-10-22 7:46 ` [PATCH v2 08/12] ARM: Layerscape: LS1046a-rdb: Switch to " Sascha Hauer
2024-10-22 7:46 ` [PATCH v2 09/12] ARM: Layerscape: TQMLS1046a: " Sascha Hauer
2024-10-22 7:46 ` [PATCH v2 10/12] ARM: Layerscape: LS1046a: remove PPA support Sascha Hauer
2024-10-22 7:46 ` [PATCH v2 11/12] ARM: Layerscape: LS1046a: add PSCI node Sascha Hauer
2024-10-22 7:46 ` [PATCH v2 12/12] ARM: Layerscape: Update Documentation for TF-A Sascha Hauer
2024-10-22 8:16 ` Ahmad Fatoum
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